An aircraft management computer software verification environment system

Abstract

This invention provides an aircraft management computer software verification environment system, relating to the field of equipment testing technology. The invention includes VMC integrated testing equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and integrated testing equipment, and constructs Ethernet, reflective memory network, and bus network for internal system use. Internally, the system uses Ethernet, reflective memory network, and bus network for data interaction and equipment control. Through verification environment cabinets, verification environment finished product cabinets, and verification environment workbenches, the operation of each test device is integrated and fixed, allowing personnel to operate the desired test device at the corresponding functional area without needing to understand the current environment architecture. This invention meets the need for simultaneous verification of aircraft management software by multiple airborne finished products, realizes a standardized and fixed paradigm for aircraft management software verification, and provides a system integration and testing verification environment for airborne finished products.

Description

Technical Field

[0001] This invention relates to the field of equipment testing technology, and in particular to an aircraft management computer software verification environment system. Background Technology

[0002] Airborne products used on aircraft need to undergo aircraft management software verification before leaving the factory; this includes airborne subsystem testing, dual-V testing, 1394 network testing, and weapons bay expansion, etc.

[0003] Traditional testing methods involve building independent verification environments for different airborne products. However, when conducting system integration and testing, it is necessary to redeploy the system integration and testing verification environment, which is inefficient and the workload increases with the number of airborne products being integrated and tested. Furthermore, the operation of each test device is complex and varied, without a standard fixed paradigm. Staff need to sort out the current environment architecture before they can go to the location of the test device to operate it.

[0004] Therefore, it is necessary to establish an aircraft management computer software verification environment system to meet the needs of multiple airborne products to simultaneously verify aircraft management software. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides an aircraft management computer software verification environment system, designed to meet the need for simultaneous verification of aircraft management software from multiple airborne products, to establish a standardized paradigm for aircraft management software verification, and to provide a system integration and testing environment for airborne products.

[0006] This invention provides an aircraft management computer software verification environment system for coordinating multiple airborne products to conduct integrated experiments simultaneously and providing a software verification environment. It includes VMC integrated testing equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and integrated testing equipment, and constructs Ethernet, reflective memory network, and bus network for internal system use; wherein,

[0007] The VMC integrated test equipment includes a programmable power supply, a VMC integrated test microservice computer, a test subsystem PXI device, a disconnection box, a VMC integrated test client computer, an MFD simulation device, and an MBT / GMP device. The programmable power supply is electrically connected to each onboard product; the VMC integrated test microservice computer is electrically connected to the test subsystem PXI device and connected to both an Ethernet network and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnection box; the disconnection box is electrically connected to each onboard product; the VMC integrated test client computer is connected to the Ethernet network; the MFD simulation device is connected to the reflective memory network; and the MBT / GMP device is connected to the Ethernet network and communicates with each onboard product via a bus network.

[0008] The bus network node simulation device includes a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein, the bus network node simulation client computer is connected to Ethernet and a reflective memory network respectively, and the bus network node simulation PXI chassis communicates with each airborne finished product through the bus network and is connected to Ethernet and a reflective memory network respectively;

[0009] The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer, and a bus data acquisition front-end PXI chassis. The disk array, server, bus data acquisition client computer, bus data acquisition front-end computer, and bus data acquisition front-end PXI chassis are all connected to an Ethernet network. The bus data acquisition front-end PXI chassis is connected to a reflective memory network and communicates with each onboard product via the bus network. The development and integration testing equipment is configured via a VMC debugging computer and is electrically connected to each onboard product. Each onboard product also communicates with a bus repeater via the bus network.

[0010] As a further solution, the bus network is a 1394 bus network based on the 1394 protocol with added AS5643 protocol group enhancement, connecting the devices to achieve device-to-device bus communication; the reflective memory network connects the reflective memory cards of the devices through a reflective memory switch, and achieves memory-to-memory communication between the connected devices; the Ethernet connects the 10 Gigabit network cards of the devices through a network switch, and achieves device-to-device network communication between the connected devices.

[0011] As a further solution, testing instruments and equipment are also provided; wherein, the testing instruments and equipment include a digital multimeter, an oscilloscope and a signal generator, and the disconnect box is electrically connected to the digital multimeter, the oscilloscope and the signal generator respectively.

[0012] As a further solution, the VMC integrated test equipment includes a VMC integrated test equipment-PXI chassis, a cascade card, a first remote control card, a power SPST card group, a signal SPDT card group, and a single-line matrix card group; wherein, the first remote control card is electrically connected to the second remote control card of the VMC integrated test microservice computer, and the power SPST card group, the signal SPDT card group, and the single-line matrix card group are respectively electrically connected to the disconnect box.

[0013] As a further solution, the bus network node emulation PXI chassis is equipped with a PXI host card, a first CPCI bus emulation card group, and a reflective memory card; wherein, the first CPCI bus emulation card group establishes bus communication connections with each airborne product through a 1394 bus network, and the bus network node emulation PXI chassis establishes memory communication connections with a reflective memory switch through the reflective memory card.

[0014] As a further solution, the PXI chassis for the bus data acquisition front-end is equipped with a third remote control card, a second CPCI bus emulation card group, a 10 Gigabit Ethernet card, and a reflective memory card. The third remote control card is electrically connected to a fourth remote control card of the bus data acquisition front-end computer. The second CPCI bus emulation card group establishes bus communication connections with each onboard product via a 1394 bus network. The PXI chassis for the bus data acquisition front-end establishes a memory communication connection with a reflective memory switch via the reflective memory card and a network communication connection with a network switch via the 10 Gigabit Ethernet card.

[0015] As a further solution, a KVM switch is also provided and electrically connected to the MFD simulation equipment, the VMC integrated test client computer, the bus network node simulation client computer, and the MBT / GMP equipment, respectively. Among them, the bus network node simulation client computer is also configured as an automatic dual-V test computer, and the MBT / GMP equipment is equipped with a PCI bus simulation card and establishes bus communication connections with each airborne finished product through a 1394 bus network.

[0016] As a further solution, verification environment cabinets, verification environment finished product cabinets, and verification environment workbenches are also provided, and the various devices are categorized and configured accordingly; among them,

[0017] The verification environment cabinet is equipped with a programmable power supply, digital multimeter, oscilloscope, signal generator, disconnection box, VMC integrated test equipment - PXI chassis, PXI adapter, KVM monitor, VCM integrated test microservice computer, VMC integrated test client computer, MBT / GMP equipment and automatic dual V test computer;

[0018] The verification environment cabinet is equipped with network switches, reflective memory switches, development and integrated testing equipment, bus data acquisition front-end PXI chassis and bus repeaters; the verification environment workbench is equipped with bus data acquisition client computers, bus data acquisition front-end computers, MFD simulation equipment, servers, disk arrays and reserved equipment slots.

[0019] Compared with the prior art, the aircraft management computer software verification environment system provided by the present invention has the following advantages:

[0020] This invention includes a VMC integrated test equipment, a bus network node simulation equipment, a bus data acquisition and analysis equipment, and a development and integrated test equipment. It also constructs an Ethernet, reflective memory network, and bus network for internal system use. The system uses Ethernet, reflective memory network, and bus network for data interaction and device control. Through a verification environment cabinet, a verification environment finished product cabinet, and a verification environment workbench, the operation of each test device is integrated and fixed, allowing personnel to operate the desired test device at the corresponding functional area without needing to understand the current environment architecture. This invention meets the requirement of simultaneously verifying aircraft management software for multiple airborne finished products, realizing a standardized and fixed paradigm for aircraft management software verification, and providing a system integration and testing verification environment for airborne finished products. Attached Figure Description

[0021] Figure 1 A schematic diagram of an aircraft management computer software verification environment system architecture provided by the present invention;

[0022] Figure 2 This is a schematic diagram of the system network connection provided by the present invention;

[0023] Figure 3 This is a schematic diagram of a ring topology for a reflective memory network provided by the present invention;

[0024] Figure 4 This is a schematic diagram of the layer relationships of the 1394 protocol provided by the present invention;

[0025] Figure 5 A basic network architecture diagram provided for this invention;

[0026] Figure 6 A schematic diagram of the architecture of the three-row 1394 bus provided by the present invention;

[0027] Figure 7 This is a schematic diagram of a typical asynchronous stream data packet structure provided by the present invention;

[0028] Figure 8 This is a schematic diagram of the STOF data packet structure provided by the present invention;

[0029] Figure 9 This is a schematic diagram of the verification environment cabinet structure provided by the present invention;

[0030] Figure 10 A schematic diagram of the finished cabinet structure for the verification environment provided by this invention;

[0031] Figure 11 A schematic diagram of the verification environment workbench structure provided by the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] Please see Figure 1 To meet the flight control computer software verification requirements of the integrated flight control and navigation system, this embodiment provides an aircraft management computer software verification environment system. This system coordinates multiple airborne products to conduct integrated experiments simultaneously and provides a software verification environment. It includes VMC integrated testing equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and integrated testing equipment. It also constructs Ethernet, reflective memory network, and bus network for internal system use.

[0034] The VMC integrated test equipment includes a programmable power supply, a VMC integrated test microservice computer, a test subsystem PXI device, a disconnection box, a VMC integrated test client computer, an MFD simulation device, and an MBT / GMP device. The programmable power supply is electrically connected to each onboard product; the VMC integrated test microservice computer is electrically connected to the test subsystem PXI device and connected to both an Ethernet network and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnection box; the disconnection box is electrically connected to each onboard product; the VMC integrated test client computer is connected to the Ethernet network; the MFD simulation device is connected to the reflective memory network; and the MBT / GMP device is connected to the Ethernet network and communicates with each onboard product via a bus network.

[0035] The bus network node simulation device includes a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein, the bus network node simulation client computer is connected to Ethernet and a reflective memory network respectively, and the bus network node simulation PXI chassis communicates with each airborne finished product through the bus network and is connected to Ethernet and a reflective memory network respectively;

[0036] The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer, and a bus data acquisition front-end PXI chassis. The disk array, server, bus data acquisition client computer, bus data acquisition front-end computer, and bus data acquisition front-end PXI chassis are all connected to an Ethernet network. The bus data acquisition front-end PXI chassis is connected to a reflective memory network and communicates with each onboard product via the bus network. The development and integration testing equipment is configured via a VMC debugging computer and is electrically connected to each onboard product. Each onboard product also communicates with a bus repeater via the bus network.

[0037] It should be noted that this embodiment implements two testing modes for the aircraft management computer software verification environment: an independent testing mode and a multi-subsystem integrated testing mode. In the independent testing mode, the aircraft management computer software verification environment exists independently and can conduct individual tests. It connects to the test environment via a 1394 bus and low-frequency cables to collect and analyze bus data and low-frequency signals, achieving data collection and testing of the VMC airborne product to support software development and dynamic dual-V testing of the system. Automatic dual-V testing is achieved by sending commands via reflected memory fiber optic or Ethernet signals to control hardware resources. In the multi-subsystem integrated testing mode, the aircraft management computer software verification environment connects to the subsystem bus network via a 1394 bus derived from the bus network node simulation system, achieving association with the subsystem cluster and completing joint testing and debugging of multiple systems.

[0038] Test Principle: In the aircraft management computer software verification environment, the VMC integrated test equipment mainly detects the low-frequency electrical signals of the airborne finished VMC. The bus network node simulation equipment and bus data acquisition and analysis equipment complete the acquisition and analysis of bus data and low-frequency signals. The development and integrated test equipment is responsible for the software debugging of the airborne finished product. The information equipment in each subsystem is equipped with relevant signal function cards to realize the signal acquisition and processing functions.

[0039] like Figure 2 As shown, the subsystems are connected via experimental Ethernet, 1394 bus, reflective memory network, and low-frequency cables. The experimental Ethernet transmits experimental control commands and status information from the measurement and control equipment, enabling experimental status management, equipment control, and file transfer. The 1394 bus network transmits data packets from the VMC airborne product on the aircraft management bus network and airborne product data packets from other subsystems for joint testing. The reflective memory network is primarily used for transmitting data exchanged with the flight simulation system during pilot-in-the-loop testing. The low-frequency cables are mainly used for transmitting and conducting low-frequency electrical signals.

[0040] The following sections provide a detailed explanation of Ethernet, 1394 bus networks, and reflective memory networks:

[0041] Reflective memory is a technology that provides efficient data transfer between interconnected computers via a local area network (LAN), and it is increasingly being adopted by designers of high-performance real-time networks. The concept of a reflective memory real-time LAN is quite simple: it involves designing a network memory board to enable memory-to-memory communication in a distributed system without any software overhead.

[0042] Reflective memory networks are mainly composed of reflective memory cards linked together through transmission media such as optical fibers. Each computer on the network inserts a reflective memory card to form a node, and the memory on the reflective memory card of each node contains a copy of the shared data of other nodes on the reflective memory network.

[0043] The reflective memory card supports high-speed local read operations. When a write operation is performed on the reflective memory locally, the written data is not only stored in the local DDR, but also transmitted to all other nodes through the reflective memory network. The transmission process is transparent to the software, requires no CPU computation, and has no additional I / O overhead.

[0044] The reflective memory network has a ring topology, such as Figure 3 As shown, network packets pass through each node sequentially and eventually return to the sending node. Each node will resend the received network packets to the next node, unless that node was the original sender of the packet or there is an error in the packet.

[0045] An interrupt packet is a special type of network packet that includes a command, sender node number, receiver node number, and 4 bytes of data. When a receiver receives an interrupt from a target that is itself, it stores the sender node number and the 4 bytes of data into the corresponding FIFO according to the command.

[0046] The reflective memory card supports four interrupt levels, each of which can be user-defined. Interrupts can be initiated by any node, targeting either a single node or all nodes in the network. Initiating an interrupt requires only a single write operation to a register. Interrupts can be used to synchronize multiple nodes or as a handshake signal following data.

[0047] There are four interrupt FIFOs, each corresponding to one of the four interrupt levels, and each FIFO has a depth of 127. If local interrupts are enabled, the reflective memory card will send an interrupt to the CPU. The software can obtain interrupt-related information by reading registers and process it.

[0048] The reflective memory series features two independent DMA channels, initiated via configuration registers. Once DMA operation is started, the reflective memory series automatically completes data transfer without CPU intervention. After data transfer is complete, the reflective memory card sends an interrupt to the CPU.

[0049] Network transmission errors can be detected through 8B / 10B encoding and CRC encoding contained in the network packet. Once the reflective memory card detects a network transmission error, it will discard the erroneous network packet and generate an interrupt.

[0050] Data storage in DDR is protected by ECC, which can correct a 1-bit error in a byte and detect a 2-bit error in a byte. The reflective memory card generates an interrupt upon detecting an unrecoverable error.

[0051] Redundancy modes can further reduce the bit error rate and improve system reliability. The reflective memory series supports two redundancy modes: single-port redundancy and dual-port redundancy.

[0052] Single-port redundancy mode can be enabled through hardware configuration. In single-port redundancy mode, each network packet to be sent is transmitted twice. When the receiving end receives the redundant network packets, it first checks the first network packet. If there are no errors, the first network packet is used and the second network packet is discarded. If the first network packet contains errors but the second network packet is correct, the second network packet is used. If both packets contain errors, both packets are discarded. In single-port redundancy mode, the effective data bandwidth is reduced to half that of normal mode.

[0053] 10 Gigabit Ethernet adapters are based on Intel's 82599ES Ethernet controller and integrate multiple GbE links into a single 10 Gigabit network to reduce cost and complexity, enabling multi-core servers with higher bandwidth and network storage to support dynamic data centers.

[0054] The target system configuration for the 82599 is a rack-mount or docking server, where it can be used as an additional NIC or LAN on the motherboard (LOM). Another system configuration is a blade server, where the 82599 can be used as an LOM or mezzanine card.

[0055] The 1394 bus emulation card is used to simulate the CC, RN, and BM node functions in the 1394 bus. It supports bus topology viewing, data logging, and error injection, and can construct a 1394 bus network to achieve data transmission. The 1394 bus is based on the IEEE-1394 protocol, with modifications and constraints, and the AS5643 protocol was proposed. This protocol achieves the functional requirements of airborne electronic systems regarding real-time performance, reliability, and determinism through key technologies such as data transmission, bus synchronization, and fault tolerance. The core functions of the 1394 series emulation card are implemented using FPGA. This design can effectively parse the AS5643 protocol of the 1394B bus standard. This design features fast FPGA logic startup, strong protocol processing capabilities, small size, and light weight, meeting the testing requirements of products in laboratory environments.

[0056] The 1394 protocol can be divided into four sub-protocol layers: the physical layer, the data link layer, the transaction layer, and the bus management layer. Each layer defines a set of related services to support bus configuration, bus management, and communication between applications and the 1394 protocol layer. The relationships between the sub-protocol layers in a single node are as follows: Figure 4 As shown.

[0057] The main functions of each layer are:

[0058] a bus management layer

[0059] The Serial Bus Management layer is used to manage and control the physical layer, link layer, and transaction layer. This includes power management of bus-connected devices, optimization of timing mechanisms, allocation of synchronization channel IDs, speed matching management, topology management, bus optimization based on topology, and handling of basic error messages.

[0060] b Transaction Layer

[0061] The Transaction Layer defines a request-response protocol that supports a CSR (Control and Status Register) architecture. Based on communication between requesting and responding nodes, the Transaction Layer handles only asynchronous data packets and is implemented by firmware; for isochronous transmissions, upper-layer applications directly manipulate the link layer without going through the Transaction Layer. For data transmission between nodes, the Transaction Layer provides three operations:

[0062] 1) Read transaction: The process of data from a specific address to a data requester.

[0063] 2) Write transaction: The process of data moving from the requester to one or more responders.

[0064] 3) Lock transaction: The process of data moving from the requester to the responder, being processed at a specific address within the responder, and then being returned to the requester.

[0065] c link layer

[0066] The link layer provides implementations for packet acknowledgment, addressing, data verification, and data framing in both isochronous and asynchronous modes. It executes actions on the bus through physical layer services and provides interface services between the link layer and higher layers, transmitting changes in the state within the link layer or on the bus to the node controller.

[0067] For asynchronous transactions, the link layer provides an interface for data exchange between the transaction layer and the physical layer, and provides services such as transaction-level addressing, data verification, frame encapsulation, and decoding / unpacking of received data packets for asynchronous data packets; for isochronous transactions, the link layer provides an interface between the bus management layer and the physical layer, and provides services directly facing the application layer for isochronous data transmission.

[0068] The main functions of the link layer are:

[0069] 1) Communication with the physical layer;

[0070] 2) Implement the sending and receiving of asynchronous packets and isochronous packets;

[0071] 3) Send an acknowledgment signal for the received asynchronous data packets;

[0072] 4) Loop controller.

[0073] d) Physical layer

[0074] The physical layer primarily provides electrical and mechanical connections between devices and cables, handles data transmission and reception, and ensures that all devices can access the bus. The physical layer provides the conversion of logic signals to physical electrical signals, enables automatic bus initialization, and allows devices to interconnect in a peer-to-peer manner.

[0075] SAE AS5643 is a set of enhancements to the IEEE-1394b standard. These include the use of asynchronous streaming packets, the elimination of asynchronous or isochronous packets, a fixed frame rate synchronized with the start of the frame packet, the addition of vertical even parity, static allocation of channel numbers, pre-allocated bandwidth, the use of anonymous user messaging, and static assignment of the root node. The root node is also known as the Control Computer (CC). The CC will be the cyclic master and bus manager for each data bus.

[0076] Figure 5A basic network architecture is provided, created using a Common Coupling (CC) and a loop, which is created by connecting port 0 back to port 1 of the CC. Loops are not allowed in IEEE-1394; IEEE-1394b PHYs automatically detect and break loops. The exact location of the loop is unknown until the new architecture tree is configured. After the PHYs break the loop, there will be two branches, one on port 0 and the other on port 1. If the cable is damaged, or the PHY layer of a node on a port should now fail, the bus will automatically reconfigure the failed node at the "end" of one branch, while other nodes will still be enabled, providing initial redundancy. Figure 6 A representative three-row 1394 bus architecture is demonstrated. These three technologies are connected across channels, thus providing another level of redundancy.

[0077] Digital data can be transmitted in any supported format. All data on the bus should be aligned to a quarter-word (32-bit word). All floating-point numbers should conform to the IEEE-754 floating-point format. Data packets should also be aligned to a quarter-word (32-bit word) and must be terminated with a quarter-word (32-bit aligned word).

[0078] All data (bytes and bits) transmitted over a 1394 network has a large tuple order format. In this large tuple order format, bit 0 is the most significant bit (msb) and bit 31 is the least significant bit (lsb).

[0079] It is allowed to support S100 (200Mbps), S200 (200Mbps), S400 (400Mbps), S800 (800Mbps), S800 (800Mbps), and S3200 (3200Mbps). The maximum packet size of the fixed and asynchronous stream transmission bit rate should be consistent with that specified in the IEEE-1394 specification.

[0080] Asynchronous stream packets are isochronous data packets that are typically sent at asynchronous time intervals. Figure 7 This shows a typical asynchronous streaming data packet seen on the bus. These packets, defined in this specification, include a hardware-inserted 1394 header, a hardware-inserted anonymous user message header, a payload data area, packet carrying, and a 1394 cyclic redundancy check.

[0081] The CC node is the root node, the cycle master, and acts as the bus manager for each data bus. If isochronous transactions are used, cycle start packets can be sent via CC; however, they are not necessarily synchronized with the packet's STOF. For this reason, under STOF packet tracking, it is unacceptable to base transmit, receive, or data pump offload in many cycle start packets.

[0082] CC should transmit the start of a frame packet (STOF) at a fixed frame rate (e.g., 10 milliseconds, 12.5 milliseconds, etc.). STOF packets (e.g....) Figure 8 (As shown) should be an asynchronous stream data packet transmitted on channel 31, without a header or STOF packet in a single packet.

[0083] The test mode memory read command provides the ability to continuously read selected memory addresses. The memory read address specifies the address of memory to be read. `Num_Quads` specifies how many 32-bit quadlets are to be read from each address and should be set to 1. `num_set` specifies how many distinct addresses are required in the command packet. The read response packet should have a pass-type response and respond to the `Num_Quads` and `num_set` fields present in the read command. In the memory read address field, the data to be read from memory at each corresponding address should be entered.

[0084] The test mode memory read command provides the ability to continuously read selected memory addresses. The memory read address specifies the address of memory to be read. `Num_Quads` specifies how many 32-bit quadlets are to be read from each address and should be set to 1. `num_set` specifies how many distinct addresses are required in the command packet. The read response packet should have a pass-type response and respond to the `Num_Quads` and `num_set` fields present in the read command. In the memory read address field, the data to be read from memory at each corresponding address should be entered.

[0085] The test mode memory write command provides the ability to write to selected memory locations in RAM. The conversion type should be set to memory write, the Num_Quads field specifies how many sequential 32-bit writes to perform at each memory write start address, and num_set specifies how many memory write start addresses are required.

[0086] The 5A power supply SPST card is a 24-channel single-pole single-throw power switch module that acquires discontinuous signals from a 5A power supply and outputs switch signals via internal relays. The 1A signal SPDT card is a 66-channel single-pole single-throw data switch module that acquires discontinuous 1A signals and outputs switch signals via internal relays. The 1A signal SPST card is a 100-channel single-pole single-throw data switch module that acquires discontinuous 1A power supply signals and outputs switch signals via internal relays.

[0087] When a CC branch needs to support multiple 1394 buses and each CC branch needs to support continuous or simultaneous operation of the buses, it is important to ensure that each 1394 interface operates in a fully self-sustaining manner. To support automated operation, it is recommended that each 1394 bus (node) store local memory in storage for transport and receive descriptors and packet payload data (such as...). Figure 5 As shown), this local memory ensures that the 1394 Link Layer Controller (LLC) transmit and receive buffers will not be overwritten, and data will not be overwritten or received if the LLC's buffer is full. Local memory can be used to store static or dynamic transport descriptor chains, automatically pull message payloads from local memory, and transmit messages on the 1394 bus. LLCs can also directly boot incoming message content from the receive buffer into local memory, where the CC's host control or processing elements can access the data. The use of dedicated local memory per bus / node eliminates the need for multiple 1394 interfaces to gain access to a single bus or memory device (such as...). Figure 6 (as shown), and eliminate the stop of host controls or processing elements in order to handshake with 1394 interfaces to store / retrieve data from system memory.

[0088] This solution utilizes PXI bus communication for data signal connections. PXI is a modular instrument platform specifically designed for industrial data acquisition and automation applications. Its specification is an extension of the CPCI specification. PXIe adds PCIe to the PXI specification, and its relationship with PXI and PCI is similar, encompassing various extended features required in the test and measurement field. PCIe can establish multiple channels simultaneously to improve data transmission rates and achieve serial bus connections. Each connection only carries data between the devices at both ends of the line. The data connection rate depends on the chassis, slots, and modules. All signal flows must enter and exit the root complex, and the actual rate depends on both the PCIe interface and the controller's processing capabilities.

[0089] Furthermore, to achieve integrated and standardized operation of all testing equipment, a standardized paradigm is provided, allowing staff to operate the equipment directly from the corresponding functional area without needing to analyze the current environment architecture. This functional area includes verification environment cabinets, verification environment product cabinets, and verification environment workbenches, with each piece of equipment categorized and configured.

[0090] like Figure 9 As shown, the verification environment cabinet is equipped with a programmable power supply, digital multimeter, oscilloscope, signal generator, disconnection box, VMC integrated test equipment - PXI chassis, PXI adapter, KVM monitor, VCM integrated test microservice computer, VMC integrated test client computer, MBT / GMP equipment and automatic dual V test computer;

[0091] like Figure 10 As shown, the verification environment cabinet includes a network switch, a reflective memory switch, development and integration testing equipment, a PXI chassis for bus data acquisition, and a bus repeater; as... Figure 11 As shown, the verification environment workbench is equipped with a bus data acquisition client computer, a bus data acquisition front-end computer, an MFD simulation device, a server, a disk array, and reserved equipment slots.

[0092] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this invention, and these all fall within the protection scope of this invention.

Claims

1. An aircraft management computer software verification environment system, used to coordinate multiple airborne products to conduct integrated experiments simultaneously and provide a software verification environment, characterized in that, This includes VMC integrated testing equipment, bus network node simulation equipment, bus data acquisition and analysis equipment, and development and integrated testing equipment, and constructs Ethernet, reflective memory network, and bus network for internal system use; among which, The VMC integrated test equipment includes a programmable power supply, a VMC integrated test microservice computer, a test subsystem PXI device, a disconnection box, a VMC integrated test client computer, an MFD simulation device, and an MBT / GMP device. The programmable power supply is electrically connected to each onboard product; the VMC integrated test microservice computer is electrically connected to the test subsystem PXI device and connected to both an Ethernet network and a reflective memory network; the test subsystem PXI device is also electrically connected to the disconnection box; the disconnection box is electrically connected to each onboard product; the VMC integrated test client computer is connected to the Ethernet network; the MFD simulation device is connected to the reflective memory network; and the MBT / GMP device is connected to the Ethernet network and communicates with each onboard product via a bus network. The bus network node simulation device includes a bus network node simulation client computer and a bus network node simulation PXI chassis; wherein, the bus network node simulation client computer is connected to Ethernet and a reflective memory network respectively, and the bus network node simulation PXI chassis communicates with each airborne finished product through the bus network and is connected to Ethernet and a reflective memory network respectively; The bus data acquisition and analysis equipment includes a disk array, a server, a bus data acquisition client computer, a bus data acquisition front-end computer, and a bus data acquisition front-end PXI chassis. The disk array, server, bus data acquisition client computer, bus data acquisition front-end computer, and bus data acquisition front-end PXI chassis are all connected to an Ethernet network. The bus data acquisition front-end PXI chassis is connected to a reflective memory network and communicates with each onboard product via the bus network. The development and integration testing equipment is configured via a VMC debugging computer and is electrically connected to each onboard product. Each onboard product also communicates with a bus repeater via the bus network. It also includes verification environment cabinets, verification environment finished product cabinets, and verification environment workbenches, with each piece of equipment categorized and organized; among them, The verification environment cabinet is equipped with a programmable power supply, digital multimeter, oscilloscope, signal generator, disconnection box, VMC integrated test equipment - PXI chassis, PXI adapter, KVM monitor, VCM integrated test microservice computer, VMC integrated test client computer, MBT / GMP equipment and automatic dual V test computer; The verification environment cabinet is equipped with network switches, reflective memory switches, development and integrated testing equipment, a bus data acquisition front-end PXI chassis, and bus repeaters; the verification environment workbench is equipped with bus data acquisition client computers, bus data acquisition front-end computers, MFD simulation equipment, servers, disk arrays, and reserved equipment slots. In the aircraft management computer software verification environment, the VMC integrated test equipment detects the low-frequency electrical signals of the airborne finished VMC, the bus network node simulation equipment and the bus data acquisition and analysis equipment complete the acquisition and analysis of bus data and low-frequency signals, and the development and integrated test equipment is responsible for the software debugging of the airborne finished product.

2. The aircraft management computer software verification environment system according to claim 1, characterized in that, The bus network is a 1394 bus network based on the 1394 protocol with added AS5643 protocol group enhancement, connecting various devices to realize device-to-device bus communication; the reflective memory network connects the reflective memory cards of various devices through a reflective memory switch, and realizes memory-to-memory communication between the connected devices. The Ethernet network connects the 10 Gigabit network cards of each device through a network switch, and enables device-to-device network communication between the connected devices.

3. The aircraft management computer software verification environment system according to claim 1, characterized in that, The equipment also includes testing instruments and equipment, such as a digital multimeter, an oscilloscope, and a signal generator. The disconnect box is electrically connected to the digital multimeter, oscilloscope, and signal generator, respectively.

4. The aircraft management computer software verification environment system according to claim 1, characterized in that, The VMC integrated test equipment includes a VMC integrated test equipment-PXI chassis, a cascade card, a first remote control card, a power SPST card group, a signal SPDT card group, and a single-line matrix card group; wherein, the first remote control card is electrically connected to the second remote control card of the VMC integrated test microservice computer, and the power SPST card group, the signal SPDT card group, and the single-line matrix card group are respectively electrically connected to the disconnect box.

5. The aircraft management computer software verification environment system according to claim 2, characterized in that, The bus network node emulation PXI chassis is equipped with a PXI host card, a first CPCI bus emulation card group, and a reflective memory card; wherein, the first CPCI bus emulation card group establishes bus communication connections with each airborne product through a 1394 bus network, and the bus network node emulation PXI chassis establishes memory communication connections with a reflective memory switch through the reflective memory card.

6. The aircraft management computer software verification environment system according to claim 2, characterized in that, The PXI chassis for bus data acquisition front-end is equipped with a third remote control card, a second CPCI bus emulation card group, a 10 Gigabit Ethernet card, and a reflective memory card. The third remote control card is electrically connected to a fourth remote control card of the bus data acquisition front-end computer. The second CPCI bus emulation card group establishes bus communication connections with each onboard product via a 1394 bus network. The PXI chassis for bus data acquisition front-end establishes a memory communication connection with a reflective memory switch via the reflective memory card and a network communication connection with a network switch via the 10 Gigabit Ethernet card.

7. The aircraft management computer software verification environment system according to claim 2, characterized in that, It is also equipped with a KVM switch and electrically connected to the MFD simulation equipment, the VMC integrated test client computer, the bus network node simulation client computer, and the MBT / GMP equipment respectively; wherein, the bus network node simulation client computer is also configured as an automatic dual-V test computer, and the MBT / GMP equipment is equipped with a PCI bus simulation card and establishes bus communication connections with each airborne finished product through the 1394 bus network.

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