A software and hardware cooperative memory access operation optimization method, device, equipment and medium

Abstract

The application discloses a software and hardware cooperative memory access operation optimization method and device, equipment and medium, and relates to the technical field of computers. The method comprises the following steps: traversing the operation type of a target memory reading operation corresponding to a current memory reading operation code in target code; if the operation type is a non-direct addressing mode, a cache query instruction is executed to replace the target memory reading operation; if the operation type is a direct addressing mode, a reuse distance corresponding to the current memory reading operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, a preset direct memory access instruction is executed to replace the target memory reading operation; if the reuse distance is not greater than the preset distance threshold, a target cache instruction is executed to replace the target memory reading operation; and code traversal is continued until all memory reading operation codes in the target code are traversed. Thus, the cache pollution can be reduced by combining the software and hardware memory access instruction optimization method.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for optimizing software and hardware collaborative memory access operations. Background Art

[0002] Currently, there are two main solutions to cache pollution: hardware optimization and software optimization. However, hardware optimization solutions require maintaining large prediction tables or cache block counters every time a memory access instruction is executed, resulting in significant latency and area overhead. Furthermore, due to a lack of comprehensive understanding of the program code structure and hardware resource limitations, hardware optimization solutions' replacement strategies can only be based on local analysis of a few recently executed instructions. Software-based methods, lacking detailed information about the runtime state of instructions, are less effective when faced with irregular indirect addressing memory access patterns and conditional memory access patterns caused by branch instructions. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for optimizing software and hardware collaborative memory access operations, which rationally combines software and hardware memory access instruction optimization methods. Compared with traditional hardware cache bypass solutions, the reuse distance indicator is used to determine whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment of these instructions during execution and the potential risk of contaminating the cache; compared with pure software solutions, for memory access modes that are not suitable for code analysis, the reuse count record module is queried and maintained during execution to determine whether cache bypass should be performed, and the judgment result is more accurate and efficient. The specific solution is as follows:

[0004] In a first aspect, the present application discloses a method for optimizing software and hardware collaborative memory access operations, comprising:

[0005] Traversing the current memory read operation code in the target code, and determining the operation type of the target memory read operation corresponding to the current memory read operation code;

[0006] If the operation type is an indirect addressing mode, replacing the target memory read operation by executing a cache query instruction;

[0007] If the operation type is a direct addressing mode, calculating a reuse distance corresponding to the current memory read operation code, and determining whether the reuse distance is greater than a preset distance threshold;

[0008] If the reuse distance is greater than the preset distance threshold, replacing the target memory read operation by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, replacing the target memory read operation by executing a target cache instruction;

[0009] Jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed.

[0010] Optionally, traversing the current memory read operation code in the target code and determining the operation type of the target memory read operation corresponding to the current memory read operation code includes:

[0011] The target code is sequentially traversed to take the memory read operation code that appears for the first time in the target code as the current memory read operation code, and the current memory operation code is analyzed to determine the operation type of the target memory read operation corresponding to the current memory operation code.

[0012] Optionally, if the operation type is an indirect addressing mode, executing a cache query instruction to replace the target memory read operation includes:

[0013] If the operation type is a non-direct addressing mode, executing a cache query instruction to query the number of hardware reuses, and determining whether to save the current array to be stored to a preset cache according to the number of hardware reuses;

[0014] If the hardware reuse count is greater than a preset hardware reuse count threshold, the array to be stored is directly processed; if the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to a preset cache.

[0015] Optionally, if the operation type is a direct addressing mode, calculating the reuse distance corresponding to the current memory read operation code includes:

[0016] If the operation type is direct addressing mode, the next memory read operation code in the target code is traversed, and the data access amount between the current memory read operation code and the next memory read operation code is used as the reuse distance corresponding to the current memory read operation code.

[0017] Optionally, if the reuse distance is greater than the preset distance threshold, executing a preset direct memory access instruction to replace the target memory read operation includes:

[0018] If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by a preset direct memory access instruction, and the array to be deleted in the preset cache is deleted, so that the array to be stored is directly stored in the preset cache through the direct memory access instruction.

[0019] Optionally, if the reuse distance is not greater than the preset distance threshold, executing a target cache instruction to replace the target memory read operation includes:

[0020] If the reuse distance is not greater than the preset distance threshold, a target cache instruction is generated, and the target memory read operation is replaced by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored and directly store the array to be stored in the preset cache.

[0021] Optionally, the step of jumping to the current memory read operation code in the traversal target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed includes:

[0022] Jumping to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and using the next memory read operation code as the current memory read operation code;

[0023] Determine whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, end the memory access operation optimization after the memory access operation corresponding to the current memory read operation code is completed.

[0024] In a second aspect, the present application discloses a software and hardware collaborative memory access operation optimization device, comprising:

[0025] A code traversal module is used to traverse the current memory read operation code in the target code and determine the operation type of the target memory read operation corresponding to the current memory read operation code;

[0026] A first instruction replacement module is configured to replace the target memory read operation by executing a cache query instruction if the operation type is an indirect addressing mode;

[0027] a reuse distance calculation module, configured to calculate a reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determine whether the reuse distance is greater than a preset distance threshold;

[0028] a second instruction replacement module, configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold;

[0029] a step jump module, configured to jump to a step of a current memory reading operation code in the target code to take a next memory reading operation code as the current memory reading operation code until all the memory reading operation codes in the target code are traversed.

[0030] In a third aspect, the present application discloses an electronic device, comprising:

[0031] a memory, configured to save a computer program;

[0032] a processor, configured to execute the computer program to implement the soft and hardware cooperative memory operation optimization method as described above.

[0033] In a fourth aspect, the present application discloses a computer readable storage medium, configured to save a computer program, wherein the computer program is executed by a processor to implement the soft and hardware cooperative memory operation optimization method as described above.

[0034] In the present application, the current memory read operation code in the target code can be traversed, and the operation type of the target memory read operation corresponding to the current memory read operation code can be determined; if the operation type is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction; if the operation type is a direct addressing mode, the reuse distance corresponding to the current memory read operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction; jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed. Thus, the method of the present application can traverse the memory read operation code in the target code. If the operation type of the current memory read operation code is a non-direct addressing mode, the cache query instruction is executed to replace the target memory read operation. If it is a direct addressing mode, its reuse distance is calculated, and then it is determined whether the reuse distance is greater than a preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If not, the target memory read operation is replaced by executing a target cache instruction. Then, the traversal is continued until all memory read operation codes in the target code are traversed. In this way, the method of the present application rationally combines software and hardware memory access instruction optimization methods. Compared with traditional hardware cache bypass solutions, for regular memory read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment during execution of these instructions and the potential risk of cache pollution. At the same time, compared with pure software solutions, for non-direct addressing modes that are not suitable for code analysis, the judgment result is more accurate and efficient by executing cache query instructions to determine whether cache bypass should be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 This is a flow chart of a method for optimizing software and hardware collaborative memory access operations disclosed in this application;

[0037] Figure 2 A software and hardware cooperative memory access operation optimization method processing timing diagram is disclosed in the present application;

[0038] Figure 3 A software and hardware cooperative memory access operation optimization component architecture diagram is disclosed in the present application;

[0039] Figure 4 A software and hardware cooperative memory access operation optimization device structure schematic diagram is disclosed in the present application;

[0040] Figure 5 A software and hardware cooperative memory access operation optimization device structure schematic diagram is disclosed in the present application; DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0042] In the prior art, there are mainly two types of solutions for cache pollution problems, namely hardware optimization and software optimization. However, the hardware optimization solution needs to maintain a large prediction table or cache block counter every time the memory access instruction is executed, resulting in large delay and area overhead. The software solution lacks specific state information of instructions at runtime, and the effect is not ideal when facing irregular indirect addressing memory access mode and conditional memory access mode caused by branch instructions.

[0043] In order to overcome the above technical problems, the present application discloses a software and hardware cooperative memory access operation optimization method, device, equipment and medium, which can reduce cache pollution by combining software and hardware memory access instruction optimization methods. For non-direct addressing mode that is not suitable for code analysis, it is determined whether cache bypass should be performed by executing cache query instructions.

[0044] Referring to Figure 1 The embodiments of the present application disclose a software and hardware cooperative memory access operation optimization method, which comprises:

[0045] Step S11, traverse the current memory read operation code in the target code, and determine the operation type of the target memory read operation corresponding to the current memory read operation code.

[0046] In the embodiments, the target code that needs to be optimized for memory access operation can be traversed, and then the memory read operation code in the target code is determined, and the operation type of the target memory read operation in the memory read operation code is determined. Specifically, as Figure 2As shown, it is necessary to traverse the target code sequentially and determine the memory read operation code that appears for the first time in the target code, and then use the memory read operation code that appears for the first time as the current memory read operation code, and then analyze the current memory read operation code to determine the operation type of the memory read operation corresponding to the current memory read operation code based on the analysis results. It should be noted that there may be two types of operation types of the memory read operation corresponding to the current memory read operation code, one is a direct addressing mode, and the other is an indirect addressing mode. In this way, the target code can be traversed and the operation type corresponding to the memory read operation code in the target code can be accurately determined, thereby improving the accuracy of the optimization of software and hardware collaborative memory access operations.

[0047] Step S12: If the operation type is a non-direct addressing mode, executing a cache query instruction to replace the target memory read operation.

[0048] In this embodiment, if the operation type corresponding to the memory read operation code is a non-direct addressing mode, it is necessary to replace the target memory read operation by executing a cache query instruction. Specifically, if the operation type of the memory read operation is a non-direct addressing mode, such as an indirect addressing mode, an unbalanced addressing mode, etc., then due to the lack of specific status information of the instruction at runtime, the effect is not good when facing irregular indirect addressing memory access modes and conditional memory access modes caused by branch instructions. Therefore, a cache query instruction can be used to execute the cache query instruction to query the number of hardware reuses, and determine whether to save the current array to be stored to the preset cache based on the number of hardware reuses. Specifically, the cache query instruction can be used to instruct the processor to query and maintain the hardware reuse count recording module during execution, and determine the hardware reuse count based on the query result. If the hardware reuse count is greater than the preset hardware reuse count threshold, the array to be stored is directly processed. If the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to the preset cache. In this way, compared with pure software solutions, for memory access patterns that are not suitable for code analysis, the judgment result of whether cache bypass should be performed is more accurate and efficient by querying and maintaining the reuse count record module during execution.

[0049] Step S13: If the operation type is the direct addressing mode, calculate the reuse distance corresponding to the current memory read operation code, and determine whether the reuse distance is greater than a preset distance threshold.

[0050] In this embodiment, if the operation type is direct addressing mode, it is necessary to calculate the reuse distance corresponding to the current memory read operation code. Specifically, the direct addressing mode includes a constant direct addressing mode and an incremental direct addressing mode, and the reuse distance refers to the number of different data elements accessed between two consecutive accesses to the same data element. Therefore, it is necessary to traverse the next memory read operation code in the target code, and use the data access amount between the current memory read operation code and the next memory read operation code as the reuse distance corresponding to the current memory read operation code. Specifically, in the calculation process of the reuse distance, it is necessary to search downward according to the order of code execution until the next memory read operation is found and the same address is accessed. At this time, the reuse distance is equal to the number of iterative loops between the two multiplied by the amount of data searched in each loop. It should be noted that due to the existence of pointers, it is necessary to perform alias analysis on the pointers during the search process to determine whether two different pointers point to the same place.

[0051] Step S14: If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction.

[0052] In this embodiment, if the reuse distance is greater than a preset distance threshold, it can be considered that the amount of data in the array to be stored is too large and exceeds the capacity of the preset cache. If an attempt is made to cache the array to be stored at this time, the cached array will be replaced before it is reused next time. Therefore, a preset direct memory access instruction can be used to replace the target memory read operation, and the array to be deleted with the least number of accesses and the earliest access in the preset cache can be deleted, so that the array to be stored can be directly stored in the preset cache using the direct memory access instruction. It should be noted that the distance threshold varies with the cache size in the processor.

[0053] In another scenario, if the reuse distance is not greater than the preset distance threshold, it can be assumed that the array to be stored currently being accessed and read will gain benefits in a short period of time after being placed in the preset cache. Therefore, a target cache instruction can be generated, and the target cache instruction can be used to replace the target memory read operation to skip the data volume determination of the array to be stored and directly store the array to be stored in the preset cache. In this way, for different reuse distance scenarios, corresponding implementation plans can be matched, and the reuse distance indicator can be used to determine whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment during the execution of these instructions and the potential risk of contaminating the cache.

[0054] Step S15, jump to the step of traversing the current memory read operation code in the target code, so as to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

[0055] In this embodiment, Figure 2 As shown, it is necessary to jump to the step of traversing the current memory read operation code in the target code, and then judge the next memory read operation code, and then use the next memory read operation code as the current memory read operation code. If the current memory read operation code is the last memory read operation code in the target code, then after the memory access operation corresponding to the current memory read operation code is completed, the memory access operation optimization is ended.

[0056] Thus, the method of the present application can traverse the memory read operation code in the target code. If the operation type of the current memory read operation code is a non-direct addressing mode, the cache query instruction is executed to replace the target memory read operation. If it is a direct addressing mode, its reuse distance is calculated, and then it is determined whether the reuse distance is greater than a preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If not, the target memory read operation is replaced by executing a target cache instruction. Then, the traversal is continued until all memory read operation codes in the target code are traversed. In this way, the method of the present application rationally combines software and hardware memory access instruction optimization methods. Compared with traditional hardware cache bypass solutions, for regular memory read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment during execution of these instructions and the potential risk of cache pollution. At the same time, compared with pure software solutions, for non-direct addressing modes that are not suitable for code analysis, the judgment result is more accurate and efficient by executing cache query instructions to determine whether cache bypass should be performed.

[0057] like Figure 3 The figure shows a software and hardware collaborative memory access instruction optimization component disclosed in this application, which includes two parts: software and hardware. Among them, the memory is used to store compiled and optimized binary instructions, such as cache query instructions, preset direct memory access instructions, and target cache instructions, and is also used to save the data required for program operation. Depending on the type of optimized memory access instruction, the memory will send the data to different places. If it is a preset direct memory access instruction, the memory unit directly sends the data to the operation unit; if it is a target cache instruction, the data is sent to the preset cache. If it is a cache query instruction, the reuse count recording module is used to query and determine the flow of data.

[0058] The reuse count recording module is located within the processor and uses multiple storage items to store the reuse status of different memory access operations. Each storage item has two parts. The first part stores the program counter of the instruction. In this application, the program counter is stored in 32-bit binary format. The same instruction in a loop may access memory multiple times during execution. The memory access address may be different each time, but the corresponding memory access mode is the same. The second part of each storage item stores the number of times the memory access instruction has been executed. The upper limit of this number needs to be set according to the specific program scale. Here, it can be set as a 32-bit binary number. When the reuse count recording module detects a memory read request, it searches the storage items for the program counter of the current read request. If the program counter is not found, a new storage item is created to store the program counter of the current read request and initialized to 0. The data from this memory access is also sent directly to the arithmetic unit. If the number of newly added storage items exceeds the resource limit, the storage item with the least access count and the earliest access count is deleted and a new storage item is added. If the storage item is found, the access count of the corresponding storage item for the instruction is increased by 1. The access count is then checked to see if it exceeds a threshold. If so, the data is cached; if less, it is sent directly to the arithmetic unit. If the access count exceeds the range of a 32-bit binary number, the access count remains at the maximum range.

[0059] The preset cache can store data during program execution and provide the data to the operation unit. The operation unit accepts operands from corresponding positions according to instruction requirements and performs corresponding operation types.

[0060] See also Figure 4 As shown, an embodiment of the present invention discloses a device for optimizing software and hardware collaborative memory access operations, comprising:

[0061] A code traversal module 11 is used to traverse the current memory read operation code in the target code and determine the operation type of the target memory read operation corresponding to the current memory read operation code;

[0062] A first instruction replacement module 12 is configured to replace the target memory read operation by executing a cache query instruction if the operation type is an indirect addressing mode;

[0063] a reuse distance calculation module 13 for calculating a reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determining whether the reuse distance is greater than a preset distance threshold;

[0064] a second instruction replacement module 14, configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold;

[0065] The step jump module 15 is used to jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

[0066] In this embodiment, the current memory read operation code in the target code can be traversed, and the operation type of the target memory read operation corresponding to the current memory read operation code can be determined; if the operation type is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction; if the operation type is a direct addressing mode, the reuse distance corresponding to the current memory read operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction; jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code, until all memory read operation codes in the target code are traversed. Thus, the method of the present application can traverse the memory read operation code in the target code. If the operation type of the current memory read operation code is a non-direct addressing mode, the cache query instruction is executed to replace the target memory read operation. If it is a direct addressing mode, its reuse distance is calculated, and then it is determined whether the reuse distance is greater than a preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If not, the target memory read operation is replaced by executing a target cache instruction. Then, the traversal is continued until all memory read operation codes in the target code are traversed. In this way, the method of the present application rationally combines software and hardware memory access instruction optimization methods. Compared with traditional hardware cache bypass solutions, for regular memory read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment during execution of these instructions and the potential risk of cache pollution. At the same time, compared with pure software solutions, for non-direct addressing modes that are not suitable for code analysis, the judgment result is more accurate and efficient by executing cache query instructions to determine whether cache bypass should be performed.

[0067] In some embodiments, the code traversal module 11 may specifically include:

[0068] A code traversal unit is used to sequentially traverse the target code to take the memory read operation code that appears for the first time in the target code as the current memory read operation code, and analyze the current memory operation code to determine the operation type of the target memory read operation corresponding to the current memory operation code.

[0069] In some embodiments, the first instruction replacement module 12 may specifically include:

[0070] a reuse count query unit, configured to execute a cache query instruction to query a hardware reuse count if the operation type is a non-direct addressing mode, and determine whether to save the current array to be stored to a preset cache according to the hardware reuse count;

[0071] The first cache unit is used to directly perform calculation processing on the array to be stored if the number of hardware reuse times is greater than a preset hardware reuse time threshold, and save the array to be stored to a preset cache if the number of hardware reuse times is not greater than the preset hardware reuse time threshold.

[0072] In some embodiments, the reuse distance calculation module 13 may specifically include:

[0073] A reuse distance calculation unit is used to traverse the next memory read operation code in the target code if the operation type is a direct addressing mode, and use the data access amount between the current memory read operation code and the next memory read operation code as the reuse distance corresponding to the current memory read operation code.

[0074] In some embodiments, the second instruction replacement module 14 may specifically include:

[0075] The second cache unit is used to replace the target memory read operation with a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and delete the array to be deleted in the preset cache, so as to directly store the array to be stored in the preset cache through the direct memory access instruction.

[0076] In some embodiments, the second instruction replacement module 14 may specifically include:

[0077] The third cache unit is used to generate a target cache instruction if the reuse distance is not greater than the preset distance threshold, and replace the target memory read operation by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored and directly store the array to be stored in the preset cache.

[0078] In some embodiments, the step jump module 15 may specifically include:

[0079] a step jump unit, configured to jump to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and use the next memory read operation code as the current memory read operation code;

[0080] A code judgment unit is used to judge whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, the memory access operation optimization is ended after the memory access operation corresponding to the current memory read operation code is completed.

[0081] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram should not be considered as any limitation to the scope of application of the present application.

[0082] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the software and hardware collaborative memory access operation optimization method disclosed in any of the aforementioned embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0083] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0084] In addition, the memory 22 as a carrier for resource storage can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0085] The operating system 221 is used to manage and control the hardware devices on the electronic device 20 and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of implementing the software and hardware coordinated memory access operation optimization method disclosed in any of the aforementioned embodiments and executed by the electronic device 20, the computer program 222 can further include a computer program capable of implementing other specific tasks.

[0086] Furthermore, this application discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned method for optimizing software and hardware coordinated memory access operations. The specific steps of this method can be found in the corresponding contents disclosed in the aforementioned embodiments and will not be further described here.

[0087] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0088] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0089] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0090] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0091] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for optimizing software and hardware collaborative memory access operations, characterized in that: include: Traversing the current memory read operation code in the target code, and determining the operation type of the target memory read operation corresponding to the current memory read operation code; If the operation type is an indirect addressing mode, replacing the target memory read operation by executing a cache query instruction; If the operation type is a direct addressing mode, calculating a reuse distance corresponding to the current memory read operation code, and determining whether the reuse distance is greater than a preset distance threshold; If the reuse distance is greater than the preset distance threshold, replacing the target memory read operation by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, replacing the target memory read operation by executing a target cache instruction; Jumping to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed; If the operation type is a non-direct addressing mode, executing a cache query instruction to replace the target memory read operation includes: If the operation type is a non-direct addressing mode, executing a cache query instruction to query the number of hardware reuses, and determining whether to save the current array to be stored to a preset cache according to the number of hardware reuses; If the hardware reuse count is greater than a preset hardware reuse count threshold, the array to be stored is directly processed; if the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to a preset cache.

2. The method for optimizing software and hardware collaborative memory access operations according to claim 1, wherein: The traversing the current memory read operation code in the target code and determining the operation type of the target memory read operation corresponding to the current memory read operation code includes: The target code is traversed sequentially to take the memory read operation code that appears for the first time in the target code as the current memory read operation code, and the current memory read operation code is analyzed to determine the operation type of the target memory read operation corresponding to the current memory read operation code.

3. The method for optimizing software and hardware collaborative memory access operations according to claim 1, wherein: If the operation type is a direct addressing mode, calculating the reuse distance corresponding to the current memory read operation code includes: If the operation type is direct addressing mode, the next memory read operation code in the target code is traversed, and the data access amount between the current memory read operation code and the next memory read operation code is used as the reuse distance corresponding to the current memory read operation code.

4. The method for optimizing software and hardware collaborative memory access operations according to claim 1, wherein: If the reuse distance is greater than the preset distance threshold, executing a preset direct memory access instruction to replace the target memory read operation includes: If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by a preset direct memory access instruction, and the array to be deleted in the preset cache is deleted, so that the array to be stored is directly stored in the preset cache through the preset direct memory access instruction.

5. The method for optimizing software and hardware collaborative memory access operations according to claim 4, wherein: If the reuse distance is not greater than the preset distance threshold, executing a target cache instruction to replace the target memory read operation includes: If the reuse distance is not greater than the preset distance threshold, a target cache instruction is generated, and the target memory read operation is replaced by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored and directly store the array to be stored in the preset cache.

6. The method for optimizing software and hardware collaborative memory access operations according to any one of claims 1 to 5, characterized in that: The step of jumping to the current memory read operation code in the traversal target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed includes: Jumping to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and using the next memory read operation code as the current memory read operation code; Determine whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, end the memory access operation optimization after the memory access operation corresponding to the current memory read operation code is completed.

7. A software and hardware collaborative memory access operation optimization device, characterized in that: include: A code traversal module is used to traverse the current memory read operation code in the target code and determine the operation type of the target memory read operation corresponding to the current memory read operation code; a first instruction replacement module, configured to replace the target memory read operation by executing a cache query instruction if the operation type is an indirect addressing mode; a reuse distance calculation module, configured to calculate a reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determine whether the reuse distance is greater than a preset distance threshold; a second instruction replacement module, configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold; a step jump module, configured to jump to the step of traversing the current memory read operation code in the target code, so as to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed; The first instruction replacement module includes: a reuse count query unit, configured to execute a cache query instruction to query a hardware reuse count if the operation type is a non-direct addressing mode, and determine whether to save the current array to be stored to a preset cache according to the hardware reuse count; The first cache unit is used to directly perform calculation processing on the array to be stored if the number of hardware reuse times is greater than a preset hardware reuse time threshold, and save the array to be stored to a preset cache if the number of hardware reuse times is not greater than the preset hardware reuse time threshold.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the method for optimizing software and hardware collaborative memory access operations as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that Used to store a computer program, wherein when the computer program is executed by a processor, the method for optimizing software and hardware collaborative memory access operations according to any one of claims 1 to 6 is implemented.

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