A One-Dimensional Gaussian Fitting IP Core Based on FPGA and Its Implementation Method

Abstract

The present invention discloses a one-dimensional Gaussian fitting IP core based on FPGA and its implementation method. The present invention relates to the field of network communication technology. The one-dimensional Gaussian fitting IP core based on FPGA of the present invention includes: a communication interface, an input conversion module, a filling buffer module, a fitting parameter solving module, and an output conversion module; the communication interface includes an AXI-Stream interface and an AXI-Lite interface; this IP soft core can be directly used in an FPGA or an embedded system containing an FPGA to meet the application requirements of high-speed and miniaturized computing devices, and can be directly embedded in the design, eliminating the need for designers to develop and design for one-dimensional Gaussian fitting, reducing the development cost and shortening the cycle.

Description

Technical Field

[0001] The present invention relates to the field of network communication technologies, and in particular, to a one-dimensional Gaussian fitting IP core based on FPGA and an implementation method thereof. Background Art

[0002] Currently, the development and implementation of one-dimensional Gaussian fitting algorithms are mostly carried out on microcontroller units (MCUs), digital signal processors (DSPs), and central processing units (CPUs). When processing one-dimensional Gaussian fitting algorithms, microcontrollers and digital signal processors often struggle to meet the requirements of high-speed data processing due to the limitations of their own architectures and resources, which greatly restricts the wide application and in-depth development of one-dimensional Gaussian fitting technology in fields with strict requirements for real-time performance and response speed. The central processing unit has powerful general computing capabilities and can use software algorithms to achieve accurate and fast modeling of one-dimensional Gaussian fitting. However, the CPU has inherent disadvantages in terms of miniaturization and it is difficult to integrate a CPU-based Gaussian fitting processing system into small devices or embedded systems with strict requirements for volume, power consumption, etc. Currently, there is no general one-dimensional Gaussian fitting intellectual property (IP) soft core, and technicians need to spend a lot of time designing algorithms according to specific hardware when using Gaussian fitting scenarios. Therefore, it is necessary to propose a one-dimensional Gaussian fitting IP core based on FPGA and an implementation method thereof to solve the above problems. Summary of the Invention

[0003] The present invention provides a one-dimensional Gaussian fitting IP core based on FPGA and an implementation method thereof to solve the problem that the CPU has inherent disadvantages in terms of miniaturization and it is difficult to integrate a CPU-based Gaussian fitting processing system into small devices or embedded systems with strict requirements for volume, power consumption, etc.

[0004] In a first aspect, the present invention provides a one-dimensional Gaussian fitting IP core based on FPGA, including: a communication interface, an input conversion module, a filling buffer module, a fitting parameter solving module, and an output conversion module; the communication interface includes an AXI-Stream interface and an AXI-Lite interface;

[0005] The AXI-Stream interface is used to receive data to be fitted;

[0006] The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling buffer module;

[0007] The filling cache module is used to fill the Vandermonde matrix A and matrix Y for fitting a quadratic polynomial using the least squares method according to the set fitting bits, and send the data to the fitting parameter solving module;

[0008] The fitting parameter solving module is used to receive the Vandermonde matrix A and matrix Y filled by the filling cache module, calculate the fitting line parameters using the least squares method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation;

[0009] The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module, and output the parameters after format conversion according to the set data format;

[0010] The AXI-Lite interface is used to output the data output by the output conversion module, and is also responsible for the communication interaction between the IP core and the processor.

[0011] Furthermore, the input format of the input conversion module is configured as a floating-point or fixed-point decimal format.

[0012] Furthermore, the input conversion module is used to convert the data to be calculated input through the AXI-Stream interface into floating-point numbers, obtaining the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the Cartesian coordinate system, where n = 0, 1,..., m - 1, and m is the fitting bit; and send the converted data to the filling cache module.

[0013] Furthermore, the fitting bit m is configured as any integer from 10 to 30, and the fitting bit determines the shape of the matrices participating in the calculation in the filling cache module and the fitting parameter solving module.

[0014] Furthermore, the filling cache module is used to fill the Vandermonde matrix A and matrix Y for fitting a quadratic polynomial using the least squares method according to the set fitting bit m, and send the data to the fitting parameter solving module;

[0015] The Vandermonde matrix A is:

[0016] ;

[0017] where x 0 , x 1 ,..., x m-1 are the X-axis coordinates x(n) of the data to be fitted. The matrix Y is:

[0018] ;

[0019] where y 0 , y 1,..., y m-1 is the Y-axis coordinate y(n) of the data to be fitted. Among them, ln , ln , ··· represents taking the logarithm of each item of the input y(n).

[0020] Furthermore, the fitting parameter solving module is used for:

[0021] Calculate the transpose matrix of the Vandermonde matrix passed in by the filling cache module ; ;

[0022] Use the least squares method to calculate the fitting line parameters , t = 0, 1, 2; calculate in parallel and , and After both calculations are completed, multiply to obtain (t), , where is the transpose matrix directly multiplies the matrix Y input by the filling cache module into the fitting parameter solving module; is to first multiply the transpose matrix by the Vandermonde matrix , and then judge whether the determinant value is 0. If the determinant value is 0, the exception flag bit is set to 1. If the determinant value is not 1, then take the inverse matrix of matrix and calculate ;

[0023] The fitting parameters are calculated in parallel through the following conversion formula:

[0024] ;

[0025] where , , correspond to the coefficients in the quadratic polynomial function fitted by the least squares method, is the mean value of the one-dimensional Gaussian fitting, is the standard deviation, and h is the peak height parameter;

[0026] Determine the output data. When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. When the determinant value is 0, the output one-dimensional Gaussian fitting parameter is replaced by three identical set numbers.

[0027] Further, the output format of the output conversion module is configured as a floating-point or fixed-point decimal format.

[0028] In a second aspect, the present invention provides an implementation method of the above-mentioned one-dimensional Gaussian fitting IP core based on FPGA, including:

[0029] The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak search module; the peak search module locates the maximum value of the data to be fitted, and takes a continuous segment of data with the maximum value as the middle position and the length consistent with the fitting bit number configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data into the one-dimensional Gaussian fitting IP core based on FPGA. The one-dimensional Gaussian fitting IP core based on FPGA uses the data for one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting , standard deviation , and peak height parameter h.

[0030] The present invention has the following beneficial effects: The one-dimensional Gaussian fitting IP core based on FPGA and its implementation method of the present invention can directly use this IP soft core in FPGA or an embedded system including FPGA to meet the application requirements of high-speed and miniaturized computing devices. It can be directly embedded in the design without the need for designers to develop and design for one-dimensional Gaussian fitting, reducing the development cost and shortening the cycle. The IP core of the present invention can be developed using the HLS tool, which can first convert C / C++ code into hardware description language code such as Verliog / VHDL, and then synthesize the converted hardware description language code into a specific circuit. All configuration information can be placed in the header file and configured and modified in the form of parameters, which is more convenient and fast. It supports the setting of the fitting bit number, input data format, and output data format of one-dimensional Gaussian fitting, and is flexible and convenient for specific application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is an architecture diagram of a one-dimensional Gaussian fitting IP core based on FPGA of the present invention.

[0033] Figure 2 It is a schematic diagram of an implementation method of a one-dimensional Gaussian fitting IP core based on FPGA of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention. The following will describe in detail the technical solutions provided by each embodiment of the present invention with reference to the drawings.

[0035] The present invention implements a one-dimensional Gaussian fitting algorithm on a Field-Programmable Gate Array (FPGA). By utilizing the editable and parallel characteristics of FPGA devices, high-speed one-dimensional Gaussian fitting calculations can be achieved. At the same time, a high-level synthesis (xilinx HLS) tool is used to generate an FPGA IP soft core. The IP soft core can be configured according to specific devices and can be integrated into various embedded systems to meet the requirement of miniaturization. In addition, it is designed as a general FPGA IP soft core, eliminating the need for designers to develop specifically for one-dimensional Gaussian fitting, thus saving project development time. The present invention aims to develop a one-dimensional Gaussian fitting IP core based on FPGA using the HLS tool, which can achieve high-speed calculation, miniaturized application, and ready-to-configure one-dimensional Gaussian fitting on the FPGA. At the same time, a method for implementing one-dimensional Gaussian fitting using this IP core is also provided.

[0036] Please refer to Figure 1 , a one-dimensional Gaussian fitting IP core based on FPGA provided by the present invention includes: a communication interface, an input conversion module, a fill cache module, a fitting parameter solving module, and an output conversion module; the communication interface includes an Advanced eXtensible Interface-Stream (AXI-Stream) interface and an Advanced eXtensible Interface Lite (AXI-Lite) interface.

[0037] One-dimensional Gaussian fitting calculations may face burst data transmission. A large amount of input data exceeds the processing capacity of the one-dimensional Gaussian fitting IP core. The input communication bus needs to have the ability to cache data and transmit at high speed. At the same time, since the data packet envelope to be calculated for one-dimensional Gaussian fitting satisfies the Gaussian bell-shaped characteristic, the input calculation data needs to be transmitted sequentially without the need to read through an address. The AXI-Stream interface adopts an advanced asynchronous First In First Out (FIFO) buffering mechanism, which can meet the requirements of the IP core for transmitting output data.

[0038] Among them, the AXI-Stream interface is used to receive the data to be fitted.

[0039] The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling cache module. Specifically, the input format of the input conversion module is configured as floating-point or fixed-point decimal format. For example, the input conversion module is used to convert the data to be calculated input by the AXI-Stream interface into floating-point numbers, obtaining the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the converted Cartesian coordinate system, where n = 0, 1,..., m - 1, and m is the number of fitting bits; and send the converted data to the filling cache module.

[0040] The filling cache module is used to fill the Vandermonde matrix A and matrix Y for fitting the quadratic polynomial using the least squares method according to the set number of fitting bits, and send the data to the fitting parameter solving module.

[0041] Specifically, the filling cache module fills the Vandermonde matrix A and matrix Y for fitting the quadratic polynomial using the least squares method according to the set number of fitting bits m, and sends the data to the fitting parameter solving module;

[0042] The Vandermonde matrix A is:

[0043] ;

[0044] In the formula, x 0 , x 1 ,..., x m-1 are the X-axis coordinates x(n) of the data to be fitted. The matrix Y is:

[0045] ;

[0046] In the formula, y 0 , y 1 ,..., y m-1 are the Y-axis coordinates y(n) of the data to be fitted. Among them, ln , ln , ··· means taking the logarithm of each item of the input y(n).

[0047] The fitting parameter solving module is used to receive the filled Vandermonde matrix A and matrix Y from the filling cache module, calculate the fitting line parameters using the least squares method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation. The number of fitting bits m is configured as any integer from 10 to 30, and the number of fitting bits determines the shape of the matrices participating in the calculation in the filling cache module and the fitting parameter solving module.

[0048] Specifically, the fitting parameter solving module is used for:

[0049] Calculating the transposed matrix of the Vandermonde matrix passed in by the filling cache module ; ;

[0050] Using the least squares method to calculate the fitting line parameters , t = 0, 1, 2; calculating in parallel and , and After both calculations are completed, multiply them to obtain (t); , where is the transposed matrix directly multiplies the matrix Y input to the fitting parameter solving module by the filling cache module; is to first multiply the transposed matrix by the Vandermonde matrix , and then judge whether the determinant value is 0. If the determinant value is 0, then the exception flag bit is set to 1. If the determinant value is not 1, then take the inverse matrix of the matrix and calculate ;

[0051] The fitting parameters are calculated in parallel through the following conversion formula:

[0052] ;

[0053] where , , corresponds to the coefficients in the quadratic polynomial function fitted by the least squares method, is the mean value of the one-dimensional Gaussian fitting, is the standard deviation, and h is the peak height parameter;

[0054] Determine the output data. When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. When the determinant value is 0, the output one-dimensional Gaussian fitting parameter is replaced with three identical set numbers.

[0055] The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module and output the confirmed parameters after format conversion according to the set data format. Specifically, the output format of the output conversion module is configured as floating-point or fixed-point decimal format.

[0056] AXI-Lite interface is used to output the data output by the output conversion module and is also responsible for the communication interaction between the IP core and the processor.

[0057] The one-dimensional Gaussian fitting IP core based on FPGA of the present invention is provided in the form of a soft core, and the soft core can be deployed on any FPGA platform, which is conducive to the rapid update and iteration of products.

[0058] The present invention also provides an implementation method for the above one-dimensional Gaussian fitting IP core based on FPGA, including:

[0059] The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak search module; the peak search module locates the maximum value of the data to be fitted, and takes a continuous segment of data with the maximum value as the middle position and the length consistent with the fitting bit number configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data into the one-dimensional Gaussian fitting IP core based on FPGA. The one-dimensional Gaussian fitting IP core based on FPGA uses the data for one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting , standard deviation , peak height parameter h.

[0060] Use case description: Use the one-dimensional Gaussian fitting IP core based on FPGA provided by the present invention to implement one-dimensional Gaussian fitting.

[0061] To better illustrate the technical solution of the present invention, the principle of the present invention is briefly deduced and described first.

[0062] The calculation formula for the quadratic polynomial of fitting m input data by the least squares method is:

[0063] ; (1)

[0064] (In formula (1): is the calculation result of the quadratic polynomial of fitting m input data by the least squares method; m is the fitting bit number, which can be configured as an integer between 10 and 30; the input data to be fitted is ([[]] , ), ([[]] , ), ···, ([[]] , ), The coordinates and coordinates are alternately input, and the parameters to be fitted are obtained. When t = 0, 1, 2, the quadratic polynomial can be fitted.

[0065] There are the following definitions:

[0066] ; (2)

[0067] ; (3)

[0068] ; (4)

[0069] Where matrix A is the Vandermonde matrix calculated from the x - coordinates of the input data to be fitted, matrix is the fitting parameter matrix, and Y is the matrix composed of the y - coordinates of the data to be fitted.

[0070] From equations (2), (3), and (4), the normal equations are derived as:

[0071] ; (5)

[0072] Solve for the parameter matrix from the normal equations. Multiply the left - hand side of equation (3) by matrix:

[0073] ; (6)

[0074] Where matrix is the transpose of matrix A. At this time, solving for the fitting parameter matrix in equation (1) is transformed into solving equation (6) :

[0075] ; (7)

[0076] The standard one - dimensional Gaussian bell function expression is:

[0077] ; (8)

[0078] Where x and y are the coordinate values of the X - axis and Y - axis in the Cartesian coordinate system respectively, μ is the mean of the one - dimensional Gaussian fitting, σ is the standard deviation of the one - dimensional Gaussian fitting, and h is the peak height parameter of the one - dimensional Gaussian fitting. Take the logarithm of both sides of equation (8):

[0079] ; (9)

[0080] Comparing equation (9) with equation (1), we can obtain:

[0081] ; (10)

[0082] From equation (11), the conversion formula between the one - dimensional Gaussian bell function parameters and the elements of the fitting parameter matrix can be obtained:

[0083] ; (11)

[0084] In summary, the method for calculating one-dimensional Gaussian fitting using the least squares method can be obtained as follows:

[0085] Input m coordinate data in the Cartesian coordinate system to be fitted ( , ), ( , ), ···, ( , ).

[0086] Fill matrix A according to equation (2), and fill matrix Y according to equation (4) after taking the logarithm of the input coordinates.

[0087] Calculate the fitting parameter matrix .

[0088] Calculate the mean value of the one-dimensional Gaussian fitting , the standard deviation of the one-dimensional Gaussian fitting, and the peak height parameter h of the one-dimensional Gaussian fitting.

[0089] To further improve the speed of the IP core fitting function, equation (7) is disassembled for parallel calculation and parts. After both parts are calculated, they are multiplied to obtain . The transpose matrix is directly multiplied by the filled matrix Y in the calculation part; the and are multiplied first in the calculation part, and then it is judged whether the determinant value of is 0. If the determinant value is 0, the exception flag bit is set to 1. If the determinant value is not 1, then is calculated, that is, the inverse matrix of the matrix is taken. The calculation of taking the inverse matrix in equation (7)

[0090] is reversible, otherwise the calculation result is not credible, and an exception flag bit needs to be set to indicate whether the calculation result is credible. When this flag bit is 1, the calculation result output by the IP core this time is a fixed exception value. If this flag bit is not 1, the calculation result output by the IP core this time is the calculated value.

[0091] Set the top-level configuration parameters and top-level input / output interfaces of the IP core. The configuration parameters include devices, clocks, etc., and the input / output interfaces include clocks, resets, interface registers, interface bit widths, etc.

[0092] Set the number of digits m for one-dimensional Gaussian fitting, the input format and output format. The setting of the number of digits for fitting is determined according to device resources and fitting accuracy, while the input and output formats are determined according to specific communication protocols.

[0093] Finally, it should be noted that the IP core of the present invention can use high-level synthesis, that is, the HLS tool, during development. It has the characteristics of fast, efficient, and flexible compared with traditional development using hardware description languages. For one-dimensional Gaussian fitting with different numbers of fitting digits, input formats, and output formats, only the design parameters need to be changed to achieve rapid configuration.

[0094] In summary, relying on the design characteristics of its own algorithm and combining the advantages of the HLS tool, the IP core of the present invention has extremely high applicability, flexibility, and configurability, and can meet the requirements of high-speed calculation of one-dimensional Gaussian fitting in FPGA and embedded systems.

[0095] The embodiments of the present invention described above do not constitute a limitation on the protection scope of the present invention.

Claims

1. A one-dimensional Gaussian fitting IP core based on FPGA, characterized in that: include: A communication interface, an input conversion module, a filling cache module, a fitting parameter solving module and an output conversion module; the communication interface includes an AXI-Stream interface and an AXI-Lite interface; The AXI-Stream interface is used to receive data to be fitted; The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling cache module; The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set number of fitting bits, and send the data to the fitting parameter solving module; The fitting parameter solving module is used to receive the Vandermonde matrix A and the matrix Y filled by the filling cache module, calculate the fitting straight line parameters using the least squares method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation is completed; The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module, convert the confirmed parameters into a format according to a set data format, and then output them; The AXI-Lite interface is used to output the data output by the output conversion module and is responsible for the communication interaction between the IP core and the processor.

2. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The input format of the input conversion module is configured as a floating point or fixed point decimal format.

3. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 2, characterized in that: The input conversion module is used to convert the data to be calculated input by the AXI-Stream interface into floating-point numbers, obtain the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the Cartesian coordinate system, n=0, 1, ..., m-1, m is the number of fitting bits; and send the converted data to the filling cache module.

4. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The number of fitting bits m is configured as any integer between 10 and 30, and the number of fitting bits determines the shapes of matrices involved in calculation in the filling cache module and the fitting parameter solving module.

5. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set fitting bit number m, and send the data to the fitting parameter solving module; The Vandermonde matrix A is: ; Where x0, x1, ..., x m-1 is the X-axis coordinate x(n) of the data to be fitted; The matrix Y is: ; Where y0, y1, ..., y m-1 is the Y-axis coordinate y(n) of the data to be fitted; where ln ,ln ,··· It means taking the logarithm of each term of the input y(n).

6. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The fitting parameter solving module is used for: Calculate the Vandermonde matrix passed to the fill cache module The transposed matrix of ; Calculate the parameters of the fitted line using the least squares method (t), t=0, 1, 2; parallel calculation and , and After all calculations are completed, multiply them to get (t); , where is the transposed matrix Directly multiply the matrix Y of the filling cache module input fitting parameter solution module; First, transpose the matrix Vandermonde matrix Multiply, then judge Whether the determinant value is 0, if If the determinant value is 0, the exception flag position is 1, such as If the determinant value is not 1, then Take the inverse matrix and calculate ; The fitting parameters are obtained by parallel calculation through the following conversion formula: ; In the formula, , , This corresponds to fitting the coefficients of a quadratic polynomial function using the least squares method. is the mean of the one-dimensional Gaussian fit, is the standard deviation of the one-dimensional Gaussian fit, and h is the peak height parameter of the one-dimensional Gaussian fit; To determine the output data, When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. The determinant value is 0, and the output one-dimensional Gaussian fitting parameters are replaced by three identical set numbers.

7. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The output format of the output conversion module is configured as a floating point or fixed point decimal format.

8. A method for implementing the one-dimensional Gaussian fitting IP core based on FPGA as claimed in any one of claims 1 to 7, characterized in that: include: The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak-finding module; the peak-finding module locates the maximum value of the data to be fitted, and takes a continuous data segment with the maximum value as the middle position and a length that is consistent with the number of fitting bits configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data to the one-dimensional Gaussian fitting IP core based on FPGA, and the one-dimensional Gaussian fitting IP core based on FPGA uses the data to perform one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting. , Standard Deviation , peak height parameter h.

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