Consistency directory access method, directory controller and computer equipment

Abstract

The embodiment of the invention provides a consistency directory access method, a directory controller and computer equipment, and the method comprises the steps: obtaining an access request which is used for accessing cache information of a target cache data block in a consistency directory; the consistency catalog comprises a coarse-grained catalog and a fine-grained catalog; judging whether the access request hits a directory cache or not, wherein the directory cache caches a part of items with a consistent directory; if the access request hits the directory cache, judging whether the access request causes the state change of the target cache data block in the consistent directory record or not; and if the access request does not cause the state change of the target cache data block recorded in the consistent directory, determining response information of the access request based on cache information of the target cache data block hit in the directory cache. According to the embodiment of the invention, the access overhead of the consistency directory can be reduced, and the performance of a computer system is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a method for accessing a consistent directory, a directory controller, and a computer device. Background Art

[0002] The cache consistency protocol is a mechanism used to maintain cache data consistency in a multi-processor system, and is crucial to the data accuracy and reliability of the multi-processor system. Specifically, a multi-processor system has multiple processor domains, and a processor domain is composed of multiple processor cores. Each processor domain has its own cache to accelerate data access by the processor cores in the processor domain; when processor cores in different processor domains access or modify the same data, the data copies in the cache may be inconsistent. At this time, the cache consistency protocol is used to ensure that the data copies in the cache remain consistent.

[0003] The consistency directory is an important component for implementing the cache consistency protocol. It records cache information such as the consistency status of the data copies owned by the cache. By accessing and updating the consistency directory, effective management of cache data consistency can be achieved, but frequent access to the consistency directory may result in large access overhead and affect the performance of the computer system. Therefore, how to provide a technical solution to reduce the access overhead of the consistency directory and improve the performance of the computer system has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] In view of this, embodiments of the present application provide a method for accessing a consistent directory, a directory controller, and a computer device to reduce the access overhead of the consistent directory and improve the performance of the computer system.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a method for accessing a consistent directory, including:

[0007] Obtaining an access request, the access request being used to access cache information of a target cache data block in a consistency directory; wherein the consistency directory includes a coarse-grained directory and a fine-grained directory, the coarse-grained directory includes a plurality of coarse-grained entries, one coarse-grained entry records cache information of a plurality of cache data blocks, and the fine-grained directory includes a plurality of fine-grained entries, one fine-grained entry records cache information of one cache data block;

[0008] Determining whether the access request hits a directory cache, the directory cache caching some entries of a consistent directory;

[0009] If the access request hits the directory cache, determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory;

[0010] If the access request does not result in a change in the state of the target cache data block recorded in the consistency directory, response information of the access request is determined based on cache information of the hit target cache data block in the directory cache.

[0011] In a second aspect, an embodiment of the present application provides a directory controller, including:

[0012] A consistency directory, wherein the consistency directory includes a coarse-grained directory and a fine-grained directory, wherein the coarse-grained directory includes a plurality of coarse-grained entries, wherein one coarse-grained entry records cache information of a plurality of cache data blocks, and the fine-grained directory includes a plurality of fine-grained entries, wherein one fine-grained entry records cache information of one cache data block;

[0013] A directory cache, wherein the directory cache caches some entries of a consistent directory;

[0014] A control circuit, configured to obtain an access request, wherein the access request is used to access cache information of a target cache data block in a consistency directory; determine whether the access request hits the directory cache; if the access request hits the directory cache, call optimization logic to determine whether the access request causes a state change of the target cache data block in the consistency directory record; if the judgment result of the optimization logic is that the access request does not cause a state change of the target cache data block in the consistency directory record, determine response information of the access request based on the cache information of the target cache data block that hits in the directory cache;

[0015] The optimization logic is used for the call of the controlled circuit to make optimization decisions, including determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory.

[0016] In a third aspect, an embodiment of the present application provides a computer device, comprising a directory controller as described in the second aspect above.

[0017] The access method of the consistency directory provided by the embodiment of the present application is based on the consistency directory used in combination with the coarse-grained directory and the fine-grained directory, and some entries of the consistency directory are cached through the directory cache; thus, for the access request obtained, the embodiment of the present application can first query the directory cache to determine whether the access request hits the directory cache; when the access request hits the directory cache, the embodiment of the present application further determines whether the access request will cause the target cache data block to change the state of the consistency directory record; for the access request that does not cause the record state change, the embodiment of the present application can directly determine the response information of the access request based on the entry hit in the directory cache to respond to the access request, without further accessing or updating the consistency directory, reducing the delay time for processing the access request, and improving the response speed and overall efficiency. That is to say, the embodiment of the present application caches some entries of the consistency directory through the directory cache, reducing the frequent access to the consistency directory; and when the access request hits the directory cache, introducing the judgment of whether the access request causes the state change of the consistency directory record, so as to directly respond to the access request based on the directory cache when the record state remains unchanged, avoiding unnecessary consistency directory access and state update operations, so the embodiment of the present application can effectively reduce the access overhead of the consistency directory and improve the response speed and overall performance of the computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 An architectural diagram of a computer system.

[0020] Figure 2A An example diagram of a fine-grained directory.

[0021] Figure 2B An example diagram of a coarse-grained directory.

[0022] Figure 3 An example flow chart for accessing and updating a consistency directory.

[0023] Figure 4 The following is an example diagram of the structure of an entry in a coarse-grained directory.

[0024] Figure 5 A block diagram of a computer system provided in accordance with an embodiment of the present application.

[0025] Figure 6 A flowchart of a method for accessing a consistency directory provided in an embodiment of the present application.

[0026] Figure 7 An example diagram of the state transition of the consistency protocol.

[0027] Fig. 8A This is an example diagram for the case where the state remains unchanged.

[0028] Figure 8B The following is an example diagram of a state change. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] To understand cache consistency and consistency directory, take a computer system with a multi-processor system as an example. Figure 1 The architecture diagram of a computer system is shown as an example. Figure 1 As shown, the computer system includes the following components.

[0031] Multiple processor domains 110, one processor domain may include multiple processor cores, which are regarded as a logical unit composed of multiple processor cores; wherein the processor core is the computing core of the processor domain, responsible for executing instructions and processing data, such as a CPU (Central Processing Unit) core.

[0032] The cache 120 of each processor domain is an intermediate layer between the processor domain and the memory, and is used to accelerate data access of the processor cores in the processor domain. For any processor domain, from the perspective of the cache hierarchy, the cache of the processor domain is divided into private cache and shared cache. Among them, the private cache is an independent cache of each processor core in the processor domain, belonging to a single processor core in the processor domain, such as L1 cache, L2 cache, etc.; the shared cache is a cache shared by multiple processor cores in the processor domain, belonging to the processor domain, and used for multiple processor cores in the processor domain to share data, such as LLC (Last Level Cache).

[0033] Multiple consistency master nodes 130, which are core components for implementing cache consistency protocols and are responsible for managing cache data consistency across processor domains; for example, when a processor core of one processor domain needs to access data in the cache of another processor domain, the consistency master node can coordinate data access to ensure that the latest state of the data is correctly obtained;

[0034] A computer system may deploy multiple consistency master nodes. Specifically, multiple processor domains and multiple processor cores within a processor domain may initiate a large number of data access requests. A single consistency master node may not be able to efficiently manage cache data consistency for all data access requests. Therefore, multiple consistency master nodes may be deployed in a computer system to share data access requests, such as assigning requests from different address ranges or processor domains to different consistency master nodes for cache data consistency management. Of course, deploying multiple consistency master nodes is only an optional method, and a computer system may also support deploying a single consistency master node.

[0035] The consistency master node is a hardware or logic component that coordinates cache data consistency operations in a multi-processor system (i.e., a multi-processor domain system) or a multi-core system. Its form and implementation may vary based on the different computer system architectures. For example, based on consistency protocols such as the MESI (Modified Exclusive Shared Invalid) protocol, the bus controller can serve as a consistency master node.

[0036] Multiple consistency directories 140, the consistency directories are used to record cache information of data, including but not limited to: owner information of data (such as the processor core and / or processor domain where the cache storing the data is located, that is, the cache location of the data), consistency status of data, etc.; the consistency directory works in coordination with the consistency master node, so that the consistency master node obtains cache information such as owner information and consistency status of data by querying the consistency directory;

[0037] Specifically, for intra-domain data access, if the data accessed by a processor core only exists in the cache of the processor domain where it is located, the data can be directly read or written, that is, the data only exists in the cache of the current processor domain and does not exist in the cache of multiple processor domains. At this time, the processor core can directly perform read and write operations; for cross-domain data access, when the data that the processor core of a processor domain needs to access is not in the cache of the current processor domain, but in another processor domain, it is necessary to query the consistency directory through the consistency master node to obtain the owner information and consistency status information of the data, so that the consistency master node transfers the data from the target processor domain (that is, the processor domain where the cache storing the data is located) to the requesting processor domain (that is, the processor domain where the processor core requesting to access the data is located) through the bus: Then, the consistency master node updates the cache information of the relevant data in the consistency directory to ensure the consistency of subsequent accesses;

[0038] In an optional implementation, the computer system may deploy multiple consistency directories to manage data cache information in a distributed manner, thereby reducing single-point access bottlenecks and supporting larger-scale multi-processor systems; of course, deploying multiple consistency directories is only an optional method, and the computer system can also support the deployment of a single consistency directory.

[0039] Furthermore, there is a collaborative relationship between the consistency master node and the consistency directory. For example, there is a one-to-one correspondence between the consistency master node and the consistency directory, that is, each consistency master node corresponds specifically to a consistency directory, and is responsible for querying and updating the cache information of the data recorded in the corresponding consistency directory; for another example, a consistency master node can correspond to multiple consistency directories, so that the consistency master node is responsible for distributing queries to its corresponding multiple consistency directories; for another example, multiple consistency master nodes share multiple consistency directories, allowing the consistency master node to query any consistency directory as needed.

[0040] Further, combined with Figure 1 As shown, the computer system also includes: a bus 150 and multiple system memories 160; wherein the bus connects all processor domains, consistency master nodes and consistency directories, and serves as the main channel for data transmission. Cross-domain data transmission and consistency maintenance operations are transmitted through the bus; the system memory is the final storage location of the data. When the data does not hit the cache of the processor domain or the data cannot be found in other processor domains, the system memory is accessed through the consistency master node and the bus to achieve data access. The system memory is, for example, the memory set in the computer system.

[0041] The consistency directory is a component that records cache information of data. The consistency directory and the cache can be associated through addresses (such as cache addresses) to form a logical mapping, thereby allowing the computer system to quickly query and maintain the cache information of data through the consistency directory through the logical mapping. Specifically, the entries of the consistency directory are the basic units for recording the cache information of data. Each entry contains information associated with the cache data. Therefore, through the entries of the consistency directory, the consistency directory can track the status of the cache data and maintain consistency. In other words, an entry is a recording unit in the consistency directory, which is used to store the cache information of data, including but not limited to:

[0042] The consistency state of the data, for example, Modified, Exclusive, Shared, Invalid, etc.

[0043] The owner information of the data, that is, the cache location of the data, indicating the processor core and processor domain where the cache storing the data is located;

[0044] A tag that identifies the data associated with the entry.

[0045] Furthermore, a cache data block (such as a cache line) is the basic storage unit of the cache, which is used to store a small segment of continuous data. The size of each cache data block can be set, such as 64 bytes, 128 bytes, etc.; based on the number of cache data blocks corresponding to an entry in the consistency directory, that is, the number of cache data blocks corresponding to the cache information recorded by an entry, the consistency directory can be divided into fine-grained directories and coarse-grained directories.

[0046] A fine-grained directory means that one entry in the consistency directory records the cache information of a cache data block, that is, one entry in the fine-grained directory corresponds to one cache data block. It should be noted that although each entry in the fine-grained directory corresponds to one cache data block, the number of entries in the fine-grained directory is not necessarily exactly equal to the number of cache data blocks in the computer system, that is, the number of entries in the fine-grained directory and the number of cache data blocks in the computer system are not necessarily in a one-to-one relationship; the number of entries in the fine-grained directory depends on the proportional relationship between the fine-grained directory and the cache data blocks to be implemented, and can be designed according to the cache management method and consistency mechanism.

[0047] For ease of understanding, Figure 2A An example diagram of a fine-grained directory is shown exemplarily. For the sake of illustration, taking 8 cache data blocks (such as 8 cache lines) as an example, the cache numbers 0 to 7 on the left side of the figure represent the 8 cache data blocks (such as 8 cache lines) in the cache. Each cache data block stores data of a set size such as 64 bytes, 128 bytes, etc. loaded from the memory, and each cache data block has associated cache information managed by the consistency protocol; the fine-grained directory on the right side of the figure is used to record cache information of each cache data block (for example, each cache line) in the cache, such as owner information, consistency status, etc., and one entry in the fine-grained directory corresponds to one cache data block (for example, one entry corresponds to one cache line), that is, one entry in the consistency directory is used to record cache information of one cache data block.

[0048] It can be seen that in the fine-grained directory, each entry manages the cache information of a cache data block separately, and can accurately manage the cache information of the cache data block; however, as the cache capacity of the computer system increases, the number of cache data blocks increases accordingly, which requires the capacity requirements of the fine-grained directory to increase accordingly (for example, according to the proportional relationship between the fine-grained directory and the cache data block, the entries of the fine-grained directory are increased accordingly). At this time, the fine-grained directory requires a large number of entries to meet the increase in the number of cache data blocks, resulting in the continuous increase in the area of ​​the fine-grained directory, so that accessing the fine-grained directory requires a large amount of access overhead. It should be noted that the consistency directory will occupy physical area on integrated circuits such as chips. The continuous increase in the number of entries will cause the area occupied by the consistency directory to continue to increase, and even increase to a level that is difficult to tolerate in the design (for example, it may occupy too many silicon chip resources, resulting in inability to manufacture), and greatly consume the overhead required to access the fine-grained directory.

[0049] Based on this, coarse-grained directories were proposed to optimize the storage and access of consistent directories; a coarse-grained directory refers to a cache information that records multiple cache data blocks in one entry. Compared with a fine-grained directory, the number of entries in a coarse-grained directory is less than that of a fine-grained directory, but the specific number of entries in a coarse-grained directory depends on the specific granularity of the coarse-grained directory (the number of specific cache data blocks corresponding to one entry) and the ratio between the coarse-grained directory and the cache data blocks that need to be implemented. Therefore, the number of entries in a coarse-grained directory is not necessarily less than the number of cache data blocks in a computer system.

[0050] For ease of understanding, Figure 2B An example diagram of a coarse-grained directory is shown as an example. For the sake of illustration, 32 cache data blocks (such as 32 cache lines) are taken as an example. The cache numbers 0 to 31 on the left side of the figure represent 32 cache data blocks (such as 32 cache lines) in the cache. Each cache data block stores data of a set size such as 64 bytes or 128 bytes loaded from the memory, and each cache data block has associated cache information managed by the consistency protocol. In the coarse-grained directory on the right side of the figure, one entry corresponds to multiple cache data blocks, that is, one entry in the coarse-grained directory records the cache information of multiple cache data blocks. For the sake of illustration, Figure 2B Take an example in which an entry in the coarse-grained directory corresponds to 16 cache data blocks, and cache data blocks 0 to 15 are mapped to an entry in the coarse-grained directory, which is used to record the cache information of cache data blocks 0 to 15, and cache data blocks 16 to 31 are mapped to another entry in the coarse-grained directory, which is used to record the cache information of cache data blocks 16 to 31.

[0051] Specifically, data has temporal and spatial properties, that is, the state of data tends to remain consistent in a short period of time. For example, in a short period of time, the same piece of data is either frequently read and written or not accessed, and consecutive memory addresses have similar states because programs tend to access memory sequentially. Based on the temporal and spatial properties of data, the coarse-grained directory can merge the cache information of multiple cache data blocks at consecutive addresses (e.g., multiple cache lines at consecutive addresses) into the same entry of the coarse-grained directory to reduce the number of entries in the coarse-grained directory, improve query efficiency, and thus reduce access overhead. In other words, one entry in the coarse-grained directory can correspond to multiple cache data blocks at consecutive addresses, such as Figure 2B One entry in corresponds to 16 cache data blocks at consecutive addresses, and is used to record cache information of the 16 cache data blocks at consecutive addresses, wherein the cache data blocks at consecutive addresses can be regarded as multiple cache data blocks within an address range, such as multiple cache lines within an address range.

[0052] It can be seen that the design of coarse-grained directories can solve the bottleneck problems of fine-grained directories in terms of capacity and access performance, and is an important optimization method in consistency management.

[0053] Compared with fine-grained directories, coarse-grained directories can reduce the number of entries, but they still face the problem of high access overhead. Specifically, no matter whether a coarse-grained directory or a fine-grained directory is used, the consistency directory needs to be accessed and updated for each access request to ensure consistency, which brings large delays and power consumption; that is, when an access request reaches the consistency master node, the consistency master node needs to access and update the consistency directory through the directory controller of the consistency directory (the consistency directory is not limited to coarse-grained directories, fine-grained directories, or a combination of coarse-grained directories and fine-grained directories), which causes unnecessary power consumption and delays, resulting in large access overhead, and affecting the response processing speed of the computer system.

[0054] For ease of understanding, let's take the example of a consistency directory that combines a coarse-grained directory and a fine-grained directory. That is, the consistency directory is a coarse-grained and fine-grained consistency directory. Figure 3 An exemplary flowchart of accessing and updating a consistent directory is shown, which may be executed by a directory controller of a consistent directory. The directory controller of the consistent directory may communicate with a consistent master node and be instructed by the consistent master node to control and manage the consistent directory. Figure 3 As shown, the process of accessing and updating the consistency directory may include the following steps.

[0055] Step S310: Get access request.

[0056] An access request refers to a data access request issued by a processor core, which involves querying, updating, or accessing a consistency directory when reading or writing data. Access requests include, but are not limited to: read requests (for reading cached data) and write requests (for updating data or status in the cache). Furthermore, access requests can also be status query requests (for checking the consistency status of data), status update requests (for updating the consistency status of data), etc.

[0057] For example, the content carried in the access request may include but is not limited to:

[0058] A request address, such as an address of a target cache data block, the request address is used to locate the target cache data block (the target cache data block is such as a target cache line); for a consistency directory, the target cache data block (such as a target cache line) is the cache data block whose cache information the access request needs to access; for a data read and write operation, the target cache data block is the cache data block whose data the access request needs to read and write;

[0059] Request type, indicating the operation type of the access request, such as read, write, invalidate, etc.

[0060] The access request may reach the consistency master node and be passed to the directory controller corresponding to the consistency directory cooperating with the consistency master node so that the directory controller can access and update the consistency directory.

[0061] Step S311: Access the coarse-grained directory and the fine-grained directory.

[0062] After obtaining the access request, the coarse-grained directory and the fine-grained directory can be accessed at the same time, and the information in the coarse-grained directory and the fine-grained directory can be read to confirm whether the access request is hit. At this time, the following situations exist:

[0063] The access request hits the coarse-grained directory;

[0064] Access requests hit fine-grained directories;

[0065] The access request misses neither the coarse-grained directory nor the fine-grained directory.

[0066] The above situation will be described in detail below.

[0067] Step S312: determine whether the access request hits the coarse-grained directory. If so, execute step S313; if not, execute step S316.

[0068] In an optional implementation, an embodiment of the present application can determine whether the cache information of the target cache data block corresponding to the access request has been recorded in the coarse-grained directory; for example, the directory controller can determine whether the corresponding entry in the coarse-grained directory can be located based on the label and index of the request address of the access request, and determine whether the target cache data block is valid in the entry.

[0069] For ease of understanding, Figure 4 The following is an exemplary diagram showing the structure of an entry of a coarse-grained directory. The cache information recorded in the entry of the coarse-grained directory may include:

[0070] Tag, used to identify multiple cache data blocks corresponding to the entry. The tag can be the bits remaining after removing the block offset and directory index from the address of the cache data block. The address of the cache data block (such as the cache address) is composed of the tag, index and block offset. The tag is a part of the cache address and is used to identify the cache data block. The index is used to specify the cache set or area of ​​the address mapping. The block offset is used to identify the specific data location of the cache data block. Multiple cache data blocks corresponding to an entry in the coarse-grained directory can have the same tag.

[0071] Current state (State), which records the current consistency state of multiple cache data blocks corresponding to the entry (consistency state is referred to as state for short). For example, in consistency protocols such as MESI, the state may be modified (M), shared (S), exclusive (E), invalid (I), etc. Multiple cache data blocks corresponding to an entry in a coarse-grained directory can have the same current state;

[0072] Owner information (Owner), i.e., the cache locations of multiple cache data blocks corresponding to the entry, indicating the processor core and processor domain holding the cache data blocks; multiple cache data blocks corresponding to an entry in the coarse-grained directory can have the same owner information;

[0073] Valid cache identifier: the valid cache identifier can indicate a valid cache data block among the multiple cache data blocks corresponding to the entry. For example, taking an entry in the coarse-grained directory corresponding to 16 cache data blocks as an example, the valid cache identifier can indicate the cache data block that currently stores cache information among the 16 cache data blocks corresponding to the entry, i.e., the valid cache data block; that is, which one or several cache data blocks among the 16 cache data blocks with consecutive addresses the entry currently stores cache information of; the valid cache identifier can be obtained by mapping the lower 4 bits (block offset) of the address of the cache data block;

[0074] For example, the valid cache identifier may be a bitmap, including a plurality of bits, each bit representing a cache data block among a plurality of cache data blocks corresponding to the entry, and being mapped to a block offset of the cache data block; if the value of a bit in the valid cache identifier is a valid value (such as 1), it indicates that the cache data block corresponding to the bit is a valid cache data block, that is, the entry currently stores cache information of the cache data block corresponding to the bit; if the value of a bit in the valid cache identifier is an invalid value (such as 0), it indicates that the cache data block corresponding to the bit is an invalid cache data block, that is, the entry currently does not store cache information of the cache data block corresponding to the bit; wherein, the valid cache identifier based on the bitmap may also be referred to as a valid cache bit;

[0075] Specifically, the valid cache bit represents which one or several cache data blocks of the 16 cache data blocks at consecutive addresses have their cache information currently stored in the entry, and the serial number of the bit corresponding to the valid cache bit of the cache data block can be mapped according to the lower 4 bits of the address of the cache data block (ie, the block offset). For example, taking the order of bits in binary from right to left as an example, that is, the lowest bit is on the rightmost side and the highest bit is on the leftmost side, if the valid cache bits of the entry are {0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0}, it means that the entry corresponds to 16 cache data blocks, of which the 10th bit is 1 (in order from right to left), then the 10th cache data block corresponding to the entry is a valid cache data block, that is, the entry currently stores cache information of the 10th cache data block, wherein the 10th bit is 1, which means that the lower 4 bits of the address of the 10th cache data block corresponding to the entry are 10 (block offset is 10), for example, in order from right to left, the bit number corresponds to the block offset of the cache data block; further, if the remaining bits of the valid cache bits (except the 10th bit) are 0, it means that the corresponding cache data block is invalid.

[0076] It can be seen that, taking an entry of a coarse-grained directory corresponding to 16 cache data blocks as an example, an entry of the coarse-grained directory can store up to 16 cache information of consecutive cache data blocks with the same tag, the same state, and the same owner, that is, the cache information of the 16 cache data blocks stored in an entry can have the same tag, state, and owner, and the addresses of the 16 cache data blocks are continuous, so that in an example, the cache information of the 16 cache data blocks stored in an entry can be composed of the same tag, the same state, the same owner, and different bits in the valid cache bit, so as to store as much information as possible with as few bits as possible, wherein different bits in the valid cache bit correspond to different cache data blocks of consecutive addresses, and the value of the bit indicates whether the corresponding cache data block is valid, and multiple bits in the valid cache bit can represent multiple cache data blocks of consecutive addresses, and the entries in the coarse-grained directory are identified by the same tag. Of course, the cache information of multiple cache data blocks corresponding to an entry can also be composed of different tags, different states, different owners, and different bits in the valid cache bit, which can be determined based on actual conditions, and the embodiments of the present application are not limited.

[0077] Further, as an example, assume that the address of a cache data block has a tag a, an index 0, a block offset 10, and the value of the lower 4 bits of the address of the cache data block corresponding to the block offset 10 is 4'd10 (4'd10 is a 4-bit binary value, corresponding to 10 in decimal), then the cache information of the cache data block can be recorded in the entry with index 0 and tag a in the coarse-grained directory, and the 10th bit in the effective cache bit of the entry corresponds to the cache data block; thus, when an access request corresponding to the address of the above cache data block arrives, the directory controller can search for the entry in the coarse-grained directory according to the index 0 and tag a of the request address of the access request (wherein the index of the entry is used to identify the cache set or area where the cache data block corresponding to the entry is located), and then when the entry with index 0 and tag a is found, based on the block offset of the request address being 10 (for example, the value of the lower 4 bits is 4'd10), check the value of the 10th bit in the effective cache bit of the entry, and if the value of the 10th bit is 1, it is determined that the access request hits in the coarse-grained directory.

[0078] That is to say, by comparing the index, tag matching and valid cache bits of the entries in the coarse-grained directory, it is possible to determine whether the access request hits the coarse-grained directory; for example, if the index and tag of the entry exist in the coarse-grained directory, and match the index and tag of the request address of the access request, the valid cache bits of the entry are further checked to determine whether the lower four bits of the request address of the access request are valid in the bits mapped to the valid cache bits (for example, whether they are 1). If valid, the access request hits the entry in the coarse-grained directory.

[0079] It is worth noting that, unlike the coarse-grained directory, the fine-grained directory does not need to set the valid cache bit information for entries because one entry corresponds to one cache data block (the valid cache bit is used to indicate the valid cache data block that currently stores the cache information when the entry corresponds to multiple cache data blocks). Therefore, the hit judgment of the fine-grained directory can be performed based on the matching of the index and label of the entry. If the index and label of the entry match the index and label of the access request, the access request hits the fine-grained directory.

[0080] Step S313: determine whether the new cache information of the target cache data block corresponding to the access request is suitable for storage in the coarse-grained directory. If so, execute step S314; if not, execute step S315.

[0081] The target cache data block corresponding to the access request has new cache information (such as new status, new owner, and other new cache information). The new cache information needs to be added or updated to the consistency directory. At this time, it is necessary to determine whether the new cache information is suitable for storage in the coarse-grained directory.

[0082] In an optional implementation, the embodiment of the present application can determine whether it is appropriate to store the new cache information in the coarse-grained directory according to the set coarse-grained directory write rules. If the new cache information meets the coarse-grained directory write rules, the new cache information can be stored in the coarse-grained directory; the set coarse-grained directory write rules can be set according to the status corresponding to the new cache information, the predefined write logic of the coarse-grained directory, etc.

[0083] For example, an entry of a coarse-grained directory can cover multiple consecutive addresses. At the same time, based on the implementation of the coarse-grained directory, the coarse-grained directory can have a corresponding recorded state type, that is, there is a corresponding relationship between the coarse-grained directory and the recorded state; for example, the coarse-grained directory can record the cache information of a cache data block in a private state (that is, there is a corresponding relationship between the coarse-grained directory and the private state), and the cache data block in the private state may involve an exclusive address range, which is suitable for coarse-grained management; for example, the fine-grained directory can record the cache information of a cache data block in a shared state (that is, there is a corresponding relationship between the fine-grained directory and the shared state), and the cache data blocks in the shared state are distributed in multiple caches, which is suitable for fine-grained management;

[0084] Thus, when determining whether the new cache information is suitable for storage in the coarse-grained directory, the embodiment of the present application can determine whether the state of the new cache information is the state corresponding to the coarse-grained directory, for example, whether the state of the new cache information is the private state corresponding to the coarse-grained directory; if so, it is determined that the new cache information is suitable for storage in the coarse-grained directory; if not, it is determined that the new cache information is not suitable for storage in the coarse-grained directory;

[0085] That is, whether the new cache information is suitable for being stored in the coarse-grained directory is determined by the correspondence between the state and the coarse-grained directory. It should be noted that the directories in different implementations correspond to different states, and the above are only examples.

[0086] In other possible implementation examples, based on the fact that an entry in a coarse-grained directory can cover multiple consecutive addresses, the embodiments of the present application can determine whether the address of the cache data block recorded in the entry of the coarse-grained directory is continuous with the address of the new cache information; if so, the new cache information can be stored in the coarse-grained directory; if not, the new cache information can be written into the fine-grained directory first.

[0087] Furthermore, if, during the processing of a subsequent access request, it is found that the fine-grained directory has multiple entries with consecutive addresses, the multiple entries with consecutive addresses in the fine-grained directory can be merged and stored in the coarse-grained directory. In other words, when the new cache information is not suitable for being stored in the coarse-grained directory, the new cache information can be first stored in the fine-grained directory, and the multiple entries with consecutive addresses found in the fine-grained directory can be merged into the coarse-grained directory.

[0088] It should be noted that if the address of the new cache information is the first address of a certain continuous address segment, it cannot form a continuous address with the records of the existing entries in the coarse-grained directory. At this time, the new cache information can be temporarily written into the fine-grained directory, and then migrated from the fine-grained directory to the coarse-grained directory after multiple entries of the continuous address range are formed later; or, in other possible implementations, a new entry is initialized directly in the coarse-grained directory, such as initializing a new entry of the continuous address range based on the address of the new cache information being the first address of the continuous address range, and writing the new cache information into the entry initialized in the coarse-grained directory. For the cache information of the first address of the continuous address range, the directory where the cache information is stored can be determined based on the specific implementation method of the directory.

[0089] It can be seen that if the new cache information adapts to the coarse-grained management method and meets the coarse-grained directory writing rules, it is suitable to be stored in the coarse-grained directory. At this time, only the coarse-grained directory needs to be updated, such as updating the new cache information of the target cache data block in the entry of the coarse-grained directory; since the coarse-grained directory can already meet the needs of the new cache information, there is no need to further update the fine-grained directory.

[0090] If the new cache information is not suitable for storage in the coarse-grained directory, both the coarse-grained directory and the fine-grained directory need to be updated simultaneously. That is, since the access request hits the coarse-grained directory, and the new cache information is not suitable for continued storage in the coarse-grained directory, the new cache information of the target cache data block needs to be transferred to the fine-grained directory. At the same time, the coarse-grained directory also needs to reflect this directory change, so both the coarse-grained directory and the fine-grained directory need to be updated simultaneously.

[0091] Step S314: Update the coarse-grained directory.

[0092] Step S315: Update the coarse-grained directory and the fine-grained directory.

[0093] A single entry may be used when updating a fine-grained directory to record the new cache information of the target cache data block.

[0094] Step S316: determine whether the access request hits the fine-grained directory. If so, execute step S317; if not, execute step S319.

[0095] Each entry in the fine-grained directory corresponds to the cache information of a cache data block, and no valid cache flag is set, so that the index and label of the entry in the fine-grained directory can be matched through the index and label of the request address of the access request to determine whether the access request has a matching entry in the fine-grained directory.

[0096] Step S317: determine whether the new cache information of the target cache data block corresponding to the access request is suitable for storage in the fine-grained directory. If so, execute step S318; if not, execute step S315.

[0097] If the access request hits the fine-grained directory, it is necessary to determine whether the new cache information of the target cache data block is suitable for continuing to be stored in the fine-grained directory, such as determining whether the state of the new cache information is the state corresponding to the fine-grained directory, such as determining whether the address of the new cache information is continuous with the address of the cache information recorded in the fine-grained directory; if the state of the new cache information is the state corresponding to the fine-grained directory (for example, the state of the new cache information is the shared state corresponding to the fine-grained directory), or the address of the new cache information and the address of the recorded cache information involve a non-continuous address range, etc., then the new cache information of the target cache data block is suitable for continuing to be stored in the fine-grained directory, and the entry of the fine-grained directory can be directly updated; otherwise, it is necessary to update the new cache information of the target cache data block in the coarse-grained directory, and update the fine-grained directory to reflect this directory change.

[0098] That is, if the new cache information is not suitable for continued storage in the fine-grained directory, the coarse-grained directory and the fine-grained directory need to be updated at the same time. That is, since the access request hits the fine-grained directory, and the new cache information is not suitable for continued storage in the fine-grained directory, the new cache information of the target cache data block needs to be transferred to the coarse-grained directory, and the fine-grained directory also needs to reflect this directory change, so the coarse-grained directory and the fine-grained directory need to be accessed and updated at the same time. When updating the coarse-grained directory, the coarse-grained directory can use one entry to record the cache information of multiple cache data blocks, including the new cache information of the target cache data block.

[0099] Step S318: Update the fine-grained directory.

[0100] Step S319: determine whether the new cache information of the target cache data block corresponding to the access request is suitable for storage in the fine-grained directory. If so, execute step S318; if not, execute step S314.

[0101] When an access request misses both the coarse-grained directory and the fine-grained directory, it means that there is no relevant entry for the target cache data block in the consistency directory, that is, the consistency directory does not have cache information such as the status and owner of the target cache data block. At this time, it can be determined whether it is appropriate to store the new cache information in the fine-grained directory. If it is appropriate to store the new cache information in the fine-grained directory, the fine-grained directory is updated to store the new cache information in the fine-grained directory. Otherwise, the coarse-grained directory is updated to store the new cache information in the coarse-grained directory.

[0102] It should be noted that although both step S317 and step S319 determine whether the new cache information is suitable for storage in the fine-grained directory, the preconditions are not consistent and the corresponding subsequent processing is also different; that is, step S317 is entered when the access request hits the fine-grained directory, and when the new cache information is not suitable for storage in the fine-grained directory, both the coarse-grained directory and the fine-grained directory are updated at the same time; while step S319 is entered when the access request does not hit both the coarse-grained directory and the fine-grained directory, and either the fine-grained directory or the coarse-grained directory is updated.

[0103] It can be seen that when the new cache information of the target cache data block cannot adapt to the storage of the hit directory, the new cache information needs to be stored in another directory. At this time, the coarse-grained directory and the fine-grained directory need to be updated at the same time to ensure cache consistency and synchronous management of data. In other words, no matter whether the access request hits the coarse-grained directory or the fine-grained directory, as long as the new cache information is not suitable for continuing to be stored in the hit directory, the new cache information needs to be transferred to another directory. At this time, both the coarse-grained directory and the fine-grained directory need to be updated at the same time. Through the above description, it can be understood that processing an access request requires accessing the consistency directory twice, that is, when determining whether the access request hits, it is necessary to first access the consistency directory once to read the directory information. When updating the new cache information, it is necessary to write the new cache information into the consistency directory, involving a second access to the consistency directory. The above process undoubtedly increases the access overhead of the consistency directory.

[0104] The embodiments of the present application consider further optimizing the access scheme of the consistency directory. In the case of a consistency directory that is a combination of a coarse-grained directory and a fine-grained directory, by caching some entries of the consistency directory, including but not limited to caching some entries of the coarse-grained directory, or caching some entries of the fine-grained directory, or caching some entries of the coarse-grained directory and some entries of the fine-grained directory, when processing access requests of certain access types (for example, when processing access requests that do not result in state changes), access to the consistency directory can be skipped, thereby accelerating the processing of access requests and reducing the access overhead of the consistency directory.

[0105] For example, taking the example of caching some entries of a coarse-grained directory, the embodiment of the present application can cache some of the coarse-grained entries that have been accessed (the entries of the coarse-grained directory are referred to as coarse-grained entries for short). For example, if a previous access request has queried a coarse-grained entry, the coarse-grained entry can be cached so that it can be used quickly in the future. Furthermore, if the next access request is to operate on a coarse-grained entry that has been previously accessed and does not change the state, then there is no need to query the entire consistency directory again, but to directly obtain the required cache information from the cached coarse-grained entry, thereby reducing the number of accesses to the consistency directory, saving power consumption for directory access and improving processing speed, thereby reducing the access overhead of the consistency directory.

[0106] Based on the above ideas, as an optional implementation, Figure 5 An optional block diagram of a computer system provided in an embodiment of the present application is shown by way of example. Figure 1 and Figure 5 As shown, the computer system provided in the embodiment of the present application is provided with: a directory controller 500, which is a hardware module in the computer system, implemented as a hardware component in a multi-processor system or a multi-core processor system, and is used to manage cache consistency; for example, the directory controller manages the data consistency of the cache in the computer system through a consistency directory based on the instruction of the consistency master node. In the embodiment of the present application, the directory controller efficiently responds to and processes access requests through directory caching and optimization mechanisms.

[0107] like Figure 5 As shown, the directory controller 500 includes the following components.

[0108] The consistency directory 140, in the embodiment of the present application, is a hybrid directory of a coarse-grained directory and a fine-grained directory, that is, the consistency directory 140 includes a coarse-grained directory 510 and a fine-grained directory 520; wherein the coarse-grained directory 510 includes a plurality of coarse-grained entries, and one coarse-grained entry records cache information of a plurality of cache data blocks; the fine-grained directory 520 includes a plurality of fine-grained entries, and one fine-grained entry records cache information of one cache data block. For ease of explanation, the entries in the fine-grained directory are referred to as fine-grained entries;

[0109] As an optional implementation, when a coarse-grained directory and a fine-grained directory are used in combination, the cache information of each cache data block can only exist in the coarse-grained directory or the fine-grained directory, that is, the cache information of a cache data block will not exist in both the coarse-grained directory and the fine-grained directory. In other words, the coarse-grained directory and the fine-grained directory are mutually exclusive; this is to achieve a balance between storage efficiency (corresponding to the coarse-grained directory) and accuracy (corresponding to the fine-grained directory). For example, if the addresses of some cache data blocks are continuous (that is, the spatial locality is high), using a coarse-grained directory can effectively compress the storage requirements. If the addresses of the cache data blocks are not continuous, using a fine-grained directory can ensure precise management, while also avoiding redundant storage of cache information in a consistency directory.

[0110] Directory cache 530, stores some entries in the consistency directory, and is used to quickly respond to some access requests to reduce the access to the consistency directory; that is, the directory cache is a hardware module dedicated to caching some entries in the consistency directory, for example, the directory cache can store the coarse-grained entries and / or fine-grained entries that have been recently accessed, so that when a new access request hits the directory cache and does not change the state (that is, the consistency state is not changed), the directory controller can respond directly without accessing the consistency directory; in an optional implementation, from the perspective of hardware design, the directory cache can be implemented as a small, high-speed storage unit built using hardware registers, such as a small register file;

[0111] As an optional implementation, the directory cache is not limited to caching partial entries of the coarse-grained directory, but can also cache partial entries of the fine-grained directory as required, or cache partial entries of both the coarse-grained directory and the fine-grained directory at the same time;

[0112] For example, if a directory cache is used to store some coarse-grained entries (i.e., some entries of the cached coarse-grained directory), it can be applicable to access requests with high spatial locality (e.g., continuous memory address access), such as access scenarios of large-scale sequential data access, so that continuous addresses can be covered by one cached entry; for example, if a directory cache is used to store some fine-grained entries (i.e., some entries of the cached fine-grained directory), it can be applicable to access requests with high randomness (e.g., scattered and discontinuous memory access), such as access scenarios where the addresses frequently accessed by the program are scattered and discontinuous, thereby providing precise state management; for example, if a directory cache is used to store some coarse-grained entries and some fine-grained entries at the same time, it can take into account both accuracy and storage efficiency and adapt to diverse access scenarios, such as mixed access scenarios, which have both continuous memory address access and scattered random address access.

[0113] The control circuit 540 is implemented as a logic control unit in the directory controller, responsible for coordinating the access and operation of the consistency directory, for example, the control circuit schedules and manages the directory access process to ensure that the access request is processed correctly;

[0114] The optimization logic 550, a logic part for controlling directory access efficiency set in an embodiment of the present application, is used to analyze the access type of the access request and the current state of the corresponding target cache data block, and make optimization decisions; thereby, through the effect of the optimization logic, it is possible to reduce access to the consistency directory, reduce power consumption and improve performance.

[0115] In an optional implementation, the control circuit 540 can be regarded as the master control unit of the directory controller 500, which is responsible for the scheduling of the overall directory access process, including request routing, state synchronization, directory update and other operations; the optimization logic 550 can be regarded as the decision unit of the directory controller 500, which is used to analyze the access type and state of the access request and provide optimization decisions for the control circuit. For example, when the access request hits the directory cache, the control circuit can call the optimization logic for decision analysis. If the optimization logic determines that the access to the consistent directory can be skipped, the control circuit can directly respond to the access request based on the directory cache, otherwise, it is necessary to respond to the access request based on the consistent directory.

[0116] In a further optional implementation, the optimization logic can be used as a submodule of the control circuit, that is, the optimization logic is nested in the control circuit and is regarded as a part of the control circuit; in further other optional implementations, the optimization logic can be implemented as an independent module, that is, the optimization logic and the control circuit can be designed separately, for example, the optimization logic is designed as an independent hardware module, and interacts with the control circuit through a signal interface. Of course, whether the optimization logic is nested in the control circuit can be determined according to actual needs, and the embodiments of the present application are not limited. The specific design depends on system performance requirements and modular requirements.

[0117] It can be understood that based on the distributed design of deploying multiple consistency directories in the computer system, the embodiment of the present application can also deploy multiple directory controllers, for example, a consistent directory that is a mixture of a coarse-grained directory and a fine-grained directory corresponds to one directory controller; of course, deploying multiple directory controllers is only an optional method, and the computer system can also support the deployment of a single directory controller.

[0118] Based on the directory controller set in the embodiment of the present application, the embodiment of the present application can reduce the access to the consistency directory when the state of the target cache data block in the consistency directory record is stable based on the state transition rules in the consistency protocol (such as MESI) and combined with the control circuit, optimization logic and directory cache architecture. As an optional implementation, Figure 6 An optional flow chart of a method for accessing a consistent directory provided in an embodiment of the present application is exemplarily shown. The method flow can be executed by a directory controller, and specifically can be executed by a control circuit and an optimization logic in the directory controller. Figure 6 The method flow may include the following steps.

[0119] Step S610: The control circuit obtains an access request.

[0120] The relevant contents of the access request are as described above and can be cross-referenced and will not be expanded here.

[0121] In an embodiment of the present application, an access request may reach a consistency master node and be passed to a directory controller corresponding to a consistency directory cooperating with the consistency master node, thereby being acquired by a control circuit in the directory controller.

[0122] Step S611, the control circuit queries the directory cache to determine whether the access request hits the directory cache, if not, execute step S612, if yes, execute step S613.

[0123] After receiving an access request, the control circuit first queries the directory cache to check whether the access request hits the directory cache; for example, after receiving an access request, the control circuit can query the directory cache based on the request address of the access request to determine whether there is an entry in some of the entries cached in the directory cache that matches the request address.

[0124] In an optional implementation, the directory cache can cache some coarse-grained entries and / or some fine-grained entries. Therefore, the embodiment of the present application can combine the granularity characteristics of the entries cached by the directory cache and the format of the request address to perform hit judgment. The principle is similar to Figure 3 The principles of determining whether an access request hits a coarse-grained directory and whether it hits a fine-grained directory as shown in the process are similar.

[0125] That is, when the directory cache caches some coarse-grained entries, it can be regarded as a subdirectory of the coarse-grained directory. The principle of judging whether the access request hits the directory cache is the same as Figure 3 The principle of judging whether an access request hits a coarse-grained directory is similar to that shown in the flow, and can be used as a reference. When the directory cache caches some fine-grained entries, it can be regarded as a subdirectory of the fine-grained directory. The principle of judging whether an access request hits the directory cache is similar to that of Figure 3 The principle of judging whether an access request hits a fine-grained directory is similar to that shown in the process, and can be used as a reference. When the directory cache caches some fine-grained entries and some coarse-grained entries at the same time, it can be regarded as a mixed sub-directory that mixes fine-grained directories and coarse-grained directories. The principle of judging whether an access request hits a directory cache is similar to that of Figure 3 The principles of determining whether an access request hits a coarse-grained directory and whether it hits a fine-grained directory as shown in the process are similar and can be referenced to each other.

[0126] For example, when the directory cache caches some coarse-grained entries, the embodiments of the present application can confirm whether the access request hits the directory cache through index, tag matching, and block validity judgment, that is, the embodiments of the present application can check whether the index and tag of the coarse-grained entries cached by the directory cache match the index and tag of the request address of the access request, and whether the valid cache identifier (for example, valid cache bit) of the coarse-grained entries cached by the directory cache and the bits corresponding to the block offset of the request address are valid values, so as to determine whether the access request hits the directory cache; thus, the index and tag cached by the directory cache match the index and tag of the request address of the access request, and the coarse-grained entries whose bits corresponding to the valid cache identifier and the block offset of the request address are valid values ​​are the coarse-grained entries that the access request hits in the directory cache.

[0127] For example, when the directory cache caches some fine-grained entries, an embodiment of the present application can check whether the tags and indexes of the fine-grained entries cached by the directory cache match the tags and indexes of the request address of the access request to determine whether the access request hits the directory cache; thus, the fine-grained entries whose tags and indexes cached by the directory cache match the tags and indexes of the request address of the access request are the fine-grained entries that the access request hits in the directory cache.

[0128] For example, when the directory cache caches some coarse-grained entries and some fine-grained entries at the same time, an embodiment of the present application can determine whether there are coarse-grained entries in the directory cache that are hit by the access request (the relevant process can be referred to the previous text and will not be expanded here), and determine whether there are fine-grained entries in the directory cache that are hit by the access request (the relevant process can be referred to the previous text and will not be expanded here).

[0129] Step S612: The control circuit accesses the coarse-grained directory and the fine-grained directory.

[0130] If the access request does not hit the directory cache, the control circuit needs to access the coarse-grained directory and the fine-grained directory to respond to the access request. At this time, the process can be connected to Figure 3 The process shown in FIG. 1 is to process the content of the content in the directory cache. That is, when the directory cache is set to cache some entries of the consistency directory (the consistency directory uses a mixture of coarse-grained directory and fine-grained directory), if the access request does not hit in the directory cache, the content of the content in the directory cache can be processed by Figure 3 The process shown accesses and updates the consistency directory.

[0131] Step S613: The control circuit calls the optimization logic.

[0132] Step S614, the optimization logic determines whether the access request causes a change in the state of the target cache data block recorded in the consistency directory. If not, execute step S615; if so, execute step S617.

[0133] If the access request hits the directory cache, the control circuit can use the optimization logic to make an optimization decision for directory access; at this time, the control circuit can call the optimization logic, pass the request information corresponding to the access request (such as request type, initiator information, etc.), and the current state and owner information of the target cache data block corresponding to the entry hit in the directory cache to the optimization logic, and the optimization logic will make the optimization decision. Thus, the optimization logic determines whether the access request causes the state of the target cache data block in the consistency directory record to change, so as to decide the subsequent operation of the control circuit; for example, if the access request hits the directory cache and the state of the consistency directory record remains unchanged, it means that the access request does not need to update the cache information in the consistency directory, and the control circuit can directly return the response data of the access request based on the target cache without further accessing the consistency directory; if the access request hits the directory cache and the state of the consistency directory record changes, it means that the access request needs to update the cache information in the consistency directory, and the control circuit needs to further access the consistency directory.

[0134] As an optional implementation, the optimization logic can determine the access type of the access request based on the request type, initiator information, and owner information of the target cache data block; and then, using the access type of the access request and the current state of the target cache data block, determine whether the access request causes the state of the target cache data block in the consistency directory record to change. For example, based on the state transition rules (such as state transition diagrams) of consistency protocols such as MESI, it is determined whether the access type of the access request causes the state of the target cache data block in the consistency directory record to change. For ease of understanding, Figure 7 An example diagram showing the state transition of the consistency protocol is shown as follows: Figure 7 As shown, a consistency protocol such as MESI can have four states:

[0135] M (Modified) state, that is, the modified state. From the data state of the cache data block, the modified state means that the data of the cache data block has been modified and only exists in the current cache. At this time, the data in the memory is invalid;

[0136] E (Exclusive) state, that is, exclusive state. From the data state of the cache data block, the exclusive state means that the data of the cache data block is exclusive to the current cache and has not been modified. At this time, the data in the memory is valid;

[0137] S (Shared) state, that is, shared state. From the data state of the cache data block, the shared state means that the data of the cache data block is shared and exists in multiple caches. At this time, the data in the memory is valid;

[0138] The I (Invalid) state, i.e. the invalid state, indicates that the data of the cached data block is invalid and there is no valid data in the current cache.

[0139] Combination Figure 7 As shown, the transition of the cache data block between different states may be triggered by different access types of access requests. Specifically, the access types of access requests may include:

[0140] local read: indicates that the processor core performs a local read operation on the data of the cache data block, for example, the processor core performs a data read operation on the cache of its own processor domain;

[0141] local write: indicates that the processor core performs a local write operation on the data in the cache data block, for example, the processor core performs a data write operation on the cache of its own processor domain;

[0142] remote read: indicates that the processor core performs a remote read operation on the data of the cache data block, for example, the processor core performs a data read operation on the cache of a processor domain other than its own;

[0143] Remote write means that the processor core performs a remote write operation on the data of the cache data block, for example, the processor core performs a data write operation on the cache of a processor domain other than its own.

[0144] The above access types can be factors that trigger the state transition of the consistency protocol. That is, the access type of the access request (such as local read, local write, remote read, remote write, etc.) and the current state of the target cache data block (such as M state, E state, S state, I state, etc.) determine whether the access request causes a state change.

[0145] In an optional implementation, the access type of an access request can be determined based on the request type (e.g., read, write) of the access request, initiator information, and owner information of the target cache data block; wherein, the request type and initiator information of the access request are carried by the access request, and the owner information of the target cache data block is recorded by the consistency directory (when hitting the directory cache, there is a corresponding record for the entry hit in the directory cache); if the initiator information and the owner information of the target data block are compared and are located in the same processor domain, the access type is deemed to be local access, and then based on the request type (e.g., read, write) of the access request, local read and local write are distinguished; if the initiator information and the owner information of the target data block are not located in the same processor domain, the access type is deemed to be remote access, and then based on the request type (e.g., read, write) of the access request, remote read and remote write are distinguished.

[0146] In a further optional implementation, under a consistency protocol such as MESI, determining that the access request does not cause a change in the state of the target cache data block recorded in the consistency directory (i.e., the state does not change) may include at least one of the following:

[0147] When the current state of the target cache data block is E state (i.e., exclusive state), the access type of local read does not change the state. In other words, the data of the cache data block is in exclusive state and is not accessed by other processor cores. Local read does not need to communicate with other caches or access memory. Therefore, it does not need to modify data and will not affect other caches. Therefore, the state remains unchanged and is still in E state.

[0148] When the current state of the target cache data block is M state (modified state), the access type of local read or local write does not change the state. That is, the data of the cache data block is in modified state and only exists in the current cache. Local read does not affect the consistency of the data, and does not need to notify other processor cores or update the memory. The state remains in M ​​state. Local write does not affect other caches either, because the data is not in other caches. At this time, the data in the memory is invalid, and the state remains unchanged, which is still M state.

[0149] When the current state of the target cache data block is S state (i.e. shared state), the access types of local read and remote read do not change the state, that is, the data is in a shared state, and local read reading shared data will not change the consistency of the data, that is, the data is in the current cache and may also be in other caches, but the local read operation does not need to notify other processor cores, and the state remains unchanged and remains in the S state; remote read will not change the consistency of the data either. When other processor cores access the shared data, the data remains in a shared state, and there is no need to update the memory, so the state remains unchanged and remains in the S state.

[0150] For ease of understanding, Fig. 8A An example diagram showing a situation where the state remains unchanged is exemplified and can be used for reference.

[0151] In a further optional implementation, under a consistency protocol such as MESI, determining whether an access request causes a state change of a target cache data block recorded in a consistency directory (i.e., a state change) may include at least one of the following:

[0152] When the current state of the target cache data block is E state (i.e., exclusive state), the access type of remote read or remote write changes state; that is, the target cache data block is in exclusive state, but remote read needs to share the data of the target cache data block from the current cache to the processor cores of other processor domains, so the target cache data block needs to be marked as S state, at which time the exclusive state is broken and the state becomes shared state; remote write will invalidate the current cache, so that the target cache data block can no longer maintain exclusive rights, and the state becomes I state, and the data of the target cache data block is taken over by the memory or other cache;

[0153] When the current state of the target cache data block is M state, the access type of remote read or remote write changes state; that is, the target cache data block is in the modified state, but remote read requires the current cache to share data, so the current cache needs to write the data of the target cache data block back to the memory to maintain consistency, so the state is changed to S state; while remote write requires the current cache to invalidate the data of the target cache data block, so the current cache needs to write the modified data of the target cache data block back to the memory or hand it over to the remote processor core, at which time the current cache loses control of the data of the target cache data block and the state is changed to I state;

[0154] When the current state of the target cache data block is S state, the access type of local write or remote write changes state; that is, the target cache data block is in shared state, but local write requires exclusive permission, so the current cache must notify other shared data caches to invalidate the target cache data block, and the data in the memory is also invalidated, then the S state is broken and the state changes to M state; remote write requires the current cache to be invalidated, that is, the current cache needs to give up data control of the target cache data block, so that the memory or remote cache can take over the data of the target cache data block, at this time the S state is broken and the state changes to I state;

[0155] When the state of the target cache data block is I state, the access type of local read or local write changes state; that is, the target cache data block is in invalid state, local read needs to load the data of the target cache data block from the main memory or other cache, if the data of the target cache data block is not shared by other caches, the state changes to E state, if the data of the target cache data block is shared by other caches, the state changes to S state; and local write needs to load the data of the target cache data block and mark the target cache data block as M state.

[0156] For ease of understanding, Figure 8B The example diagram showing the state change is exemplified and can be used for reference.

[0157] That is to say, if the access request does not involve memory update or interaction with other caches and is only completed within the current cache, such as local read, local write and other access requests in exclusive or modified state, the state of the target cache data block remains unchanged; if the access request involves memory synchronization or interaction with other caches, the state of the target cache data block needs to be changed.

[0158] The above uses MESI and other consistency protocols to illustrate the access type of the access request and the current state of the target cache data block, resulting in scenarios where the state changes and does not change; different consistency protocols may define different states and state transition rules, so the embodiments of the present application can be based on specific consistency protocols and specific state transition rules (such as state jump diagrams) to adapt to the definition of state changes and scenarios where the state does not change, and is not limited to the examples of the above-mentioned MESI and other consistency protocols.

[0159] For example, other consistency protocols include but are not limited to MOESI (Modified Owned Exclusive Shared Invalid), MESIF (Modified Exclusive Shared Invalid Forward), etc., where the O (Owned) state indicates that the data has been modified and is shared, and the cache data block is responsible for writing the data back to the main memory. The F (Forward) state indicates that the cache data block is a forwarder of shared data, which is used to reduce conflicts when multiple caches respond to read requests at the same time.

[0160] It should be noted that the above is an example of a one-to-one correspondence between the status of the consistency directory record and the status of the consistency protocol. Based on different implementations of the consistency directory, the status recorded in the consistency directory may not correspond one-to-one to the status in the consistency protocol. Specifically, based on the implementation of the consistency directory, the status recorded in the consistency directory and the status of the consistency protocol may have the following relationship:

[0161] The state of the consistency directory record corresponds one-to-one with the state of the consistency protocol;

[0162] The states recorded in the consistency directory do not correspond one-to-one to the states of the consistency protocol. For example, at least two states in the consistency protocol correspond to a merged state recorded in the consistency directory. For example, the M (Modified) state and E (Exclusive) state of the consistency protocol are merged into a private state in the consistency directory to reduce the types of states and reduce management complexity.

[0163] Therefore, if the current state of the target cache data block in the consistency protocol is changed, but the current state and the changed state belong to the merged state recorded in the consistency directory, then the state of the target cache data block in the consistency directory record may remain unchanged and remain in the merged state; for example, the current state of the target cache data block changes from the M state of the consistency protocol to the E state, but they both belong to the private state in the consistency directory (the merged state corresponding to the M state and the E state), so the state of the target cache data block in the consistency directory record is still the private state, and the state of the target cache data block in the consistency directory record is deemed to have not changed.

[0164] Based on this, whether the status of the target cache data block recorded in the consistency directory has changed can be divided into:

[0165] Whether the current state of the target cache data block is maintained, for example, whether the state of the target cache data block in the consistency protocol remains unchanged;

[0166] Whether the current state and the changed state of the target cache data block belong to the merged state recorded in the consistency directory.

[0167] Among them, the current state of the target cache data block is maintained, or the current state and the changed state belong to the merged state of the consistency directory record, which is regarded as the state of the target cache data block in the consistency directory record unchanged. At this time, the access request does not cause the state of the target cache data block in the consistency directory record to change.

[0168] Step S615: The optimization logic decision uses the cache information of the target cache data block in the directory cache to respond to the access request.

[0169] Step S616: The control circuit determines response information based on the cache information of the target cache data block hit in the directory cache.

[0170] If the optimized logic analyzes that the access request does not result in a state change, the decision control circuit can use the cache information of the target cache data block that hits in the directory cache to respond to the access request; thereby the control circuit can determine the response information of the access request based on the cache information of the target cache data block in the directory cache (such as cache information such as status), and output the response information; at this time, the control circuit does not need to access the consistency directory or modify the directory entry, which can reduce directory access, improve processing speed, and reduce power consumption.

[0171] Step S617, optimizing the logic decision control circuit to access the consistency directory.

[0172] Step S618: The control circuit accesses the consistency directory and updates the consistency directory and the directory cache, or updates the directory cache.

[0173] The optimized logic analyzes that the access request will cause a state change, and can decide that the control circuit needs to access the consistency directory. At the same time, the control circuit can update the consistency directory and the directory cache, or temporarily update the directory cache. As an optional implementation, when the access request causes the state of the target cache data block to change, the control circuit can update the consistency directory, and the directory cache also needs to be updated to ensure the consistency between the directory cache and the consistency directory. In other words, the directory cache is a copy of some entries in the consistency directory. When the access request hits the directory cache but causes a state change, if the consistency directory is updated, the directory cache needs to be updated synchronously to avoid inconsistency.

[0174] In other possible implementations, the embodiments of the present application may also support temporary updates to the directory cache, such as temporary updates to the directory cache under specific circumstances. At this time, the update of the directory cache can be performed independently of the consistency directory, so that the directory cache can be directly updated without updating the consistency directory at the same time, so as to speed up access and avoid frequent updates to the consistency directory. However, the temporary update of the directory cache is only a temporary inconsistency between the consistency directory and the directory cache. The temporary update of the directory cache ultimately needs to be applied to the consistency directory to ensure the ultimate consistency between the consistency directory and the directory cache. In other words, if the consistency directory is updated, the directory cache must be updated to ensure the consistency of the two; updating the directory cache alone is only a temporary operation, and the temporary update of the directory cache ultimately needs to be applied to the consistency directory to ensure the consistency of the two.

[0175] In an optional implementation, when an access request hits the directory cache but causes a state change, in order to reduce the impact of access delay, the control circuit can access the coarse-grained directory and the fine-grained directory at the same time to avoid delay accumulation. That is to say, accessing the coarse-grained directory first and then accessing the fine-grained directory as needed may cause delay accumulation, so the coarse-grained directory and the fine-grained directory can be accessed at the same time; for example, if it is found that the fine-grained directory needs to be accessed after accessing the coarse-grained directory, the total delay is the access time of the coarse-grained directory plus the access time of the fine-grained directory, that is, serial access (first access the coarse-grained directory, and then access the fine-grained directory as needed) will cause delay accumulation, while accessing the coarse-grained directory and the fine-grained directory at the same time, that is, accessing the coarse-grained directory and the fine-grained directory in parallel, the total delay is the longer access time of the coarse-grained directory and the fine-grained directory, which can reduce some delays.

[0176] In other optional implementations, when an access request hits the directory cache but causes a state change, the control circuit can determine the directory to access based on the state of the target cache data block change, the correspondence between the coarse-grained directory and the recorded state (e.g., the private state corresponding to the coarse-grained directory), and the correspondence between the fine-grained directory and the recorded state (e.g., the shared state corresponding to the fine-grained directory). For example, if the state of the target cache data block change corresponds to the coarse-grained directory, such as the state of the target cache data block change is a private state, the coarse-grained directory is accessed; if the state of the target cache data block change corresponds to the fine-grained directory, such as the state of the target cache data block change is a shared state, the fine-grained directory is accessed.

[0177] In an optional implementation, taking the directory cache storing some coarse-grained entries as an example, when an access request hits the directory cache but causes a state change, the consistency directory accessed by the control circuit can be a fine-grained directory; that is, if the directory cache caches some coarse-grained entries, and the access request hits the directory cache, but the optimization logic decision changes the state, then the fine-grained directory can be further accessed, and if the new cache information needs to be stored in the fine-grained directory, the fine-grained directory, coarse-grained directory, and directory cache also need to be updated.

[0178] In a further optional implementation, the embodiment of the present application may further access the fine-grained directory when the access request hits the directory cache but causes a state change, and determine whether the new cache information of the target cache data block is suitable for storage in the coarse-grained directory;

[0179] If it is suitable to be stored in the coarse-grained directory, some coarse-grained entries are cached based on the directory cache, and the cache information of the target cache data block belongs to the cache information that has been recently accessed. Therefore, the directory cache can be directly updated, and the directory cache caches the new cache information of the target cache data block, such as adjusting the state of the target cache data block in the directory cache to a new state. This situation can be regarded as a temporary update of the directory cache, that is, the cache information of the target cache data block cached by the directory cache is temporarily updated. At the same time, the temporary update of the target cache must eventually be synchronously applied to the coarse-grained directory, such as applying the temporary update of the target cache to the coarse-grained directory at an appropriate synchronization time;

[0180] If it is not suitable to be stored in the coarse-grained directory, the cache information of the target cache data block needs to be stored in the fine-grained directory. The embodiment of the present application can update the fine-grained directory, the coarse-grained directory, and the directory cache; specifically, the coarse-grained directory and the fine-grained directory are updated, and the cache information of the target cache data block is migrated from the coarse-grained directory to the fine-grained directory to update the new cache information of the target cache data block in the fine-grained directory; at the same time, based on the directory cache storing some coarse-grained entries and the access request hits the directory cache, the cache information based on the target cache data block is migrated from the coarse-grained directory to the fine-grained directory, and the directory cache needs to be updated synchronously; for example, the cache information of the target cache data block in the directory cache can be deleted (the corresponding directory cache only caches some coarse-grained entries), or the cache information of the updated target cache data block in the fine-grained directory is synchronized to the directory cache (at this time the directory cache can cache some coarse-grained entries and fine-grained entries in a mixed manner).

[0181] In a further optional implementation, an embodiment of the present application supports replacement of entries cached in a directory cache, including but not limited to replacement of some coarse-grained entries and / or some fine-grained entries in the cache; optionally, the replacement strategy of the directory cache includes but is not limited to: LRU (Least Recently Used), LFU (Least Frequently Used), Random Replacement, ARC (AdaptiveReplacement Cache), etc.; wherein, LRU eliminates entries that have not been accessed in the recent period of time, and marks the entries that hit the directory cache as recently used each time the directory cache is accessed; LFU eliminates the entries with the least number of accesses, and increases the number of accesses to the entries that hit the directory cache each time the directory cache is accessed; RandomReplacement allows random selection of entries in the directory cache for replacement; ARC combines LRU and LFU to dynamically adjust the replacement strategy based on the request pattern.

[0182] The solution provided in the embodiment of the present application can reduce the access to coarse-grained directories and fine-grained directories and significantly optimize the directory access performance through the coordination of directory caching and optimization logic. For example, taking the directory cache storing some coarse-grained entries as an example, condition 1 is defined as the access request hits the directory cache, and the optimization logic determines that the access request will not cause a state change, and condition 2 is defined as the access request hits the directory cache, but the optimization logic determines that the access request will cause a state change; thus, under condition 1, since the directory cache has stored some coarse-grained entries and the state remains unchanged, there is no need to access the coarse-grained directory and the fine-grained directory, so the access request can be directly processed by the directory cache, avoiding two directory accesses, that is, saving two accesses to the coarse-grained directory and the fine-grained directory, which are a read access (access for hit judgment) and a write access (update access) to the coarse-grained directory and the fine-grained directory respectively; under condition 2, since the directory cache hits but the state changes, it can save a read access to the coarse-grained directory and the fine-grained directory originally required for the hit judgment, and at the same time, it depends on whether the new cache information is suitable for storage in the coarse-grained directory to determine the directory involved in the write access (update access).

[0183] It can be seen that the embodiments of the present application can intelligently optimize the access path of the directory, reduce the number of unnecessary directory accesses, improve performance, reduce power consumption, and reduce the access overhead of directory access through the cooperation of directory caching and optimization logic.

[0184] Based on the consistent directory access method provided in the embodiment of the present application, the embodiment of the present application can configure the functions of the components in the directory controller accordingly. The functions of the components in the directory controller described below can be referenced to the above description.

[0185] Combination Figure 5 As shown, the directory controller provided in the embodiment of the present application includes:

[0186] A consistency directory, wherein the consistency directory includes a coarse-grained directory and a fine-grained directory, wherein the coarse-grained directory includes a plurality of coarse-grained entries, wherein one coarse-grained entry records cache information of a plurality of cache data blocks, and the fine-grained directory includes a plurality of fine-grained entries, wherein one fine-grained entry records cache information of one cache data block;

[0187] A directory cache, wherein the directory cache caches some entries of a consistent directory;

[0188] A control circuit, configured to obtain an access request, wherein the access request is used to access cache information of a target cache data block in a consistency directory; determine whether the access request hits the directory cache; if the access request hits the directory cache, call optimization logic to determine whether the access request causes a state change of the target cache data block in the consistency directory record; if the judgment result of the optimization logic is that the access request does not cause a state change of the target cache data block in the consistency directory record, determine response information of the access request based on the cache information of the target cache data block that hits in the directory cache;

[0189] The optimization logic is used for the call of the controlled circuit to make optimization decisions, including determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory.

[0190] The specific functions, extended functions, and additional functions of the above-mentioned components of the directory controller can be referred to the description of the corresponding parts in the previous text, which will not be expanded here.

[0191] Furthermore, an embodiment of the present application also provides a computer device, such as a terminal device or a server device, including the directory controller provided by the above-mentioned embodiment of the present application.

[0192] Further, combined with Figure 1 and Figure 5 As shown, the computer device may also include:

[0193] Multiple processor domains, a processor domain may include multiple processor cores;

[0194] Cache for each processor domain;

[0195] Multiple consistent master nodes;

[0196] bus;

[0197] and system memory.

[0198] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0199] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for accessing a consistent directory, characterized in that: include: Obtaining an access request, the access request being used to access cache information of a target cache data block in a consistency directory; wherein the consistency directory includes a coarse-grained directory and a fine-grained directory, the coarse-grained directory includes a plurality of coarse-grained entries, one coarse-grained entry records cache information of a plurality of cache data blocks, and the fine-grained directory includes a plurality of fine-grained entries, one fine-grained entry records cache information of one cache data block; Determining whether the access request hits a directory cache, the directory cache caching some entries of a consistent directory; If the access request hits the directory cache, determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory; If the access request does not result in a change in the state of the target cache data block recorded in the consistency directory, response information of the access request is determined based on cache information of the hit target cache data block in the directory cache.

2. The method according to claim 1, characterized in that: The determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory includes: Using the access type of the access request and the current state of the target cache data block, it is determined whether the access request causes a change in the state of the target cache data block recorded in the consistency directory.

3. The method according to claim 2, characterized in that The step of using the access type of the access request and the current state of the target cache data block to determine whether the access request causes a change in the state of the target cache data block recorded in the consistency directory includes: Based on the state transition rule, using the access type of the access request and the current state of the target cache data block, determining whether the current state of the target cache data block is maintained, or whether the current state and the changed state belong to a merged state of the consistency directory record; The states recorded in the consistency directory correspond one-to-one to the states of the consistency protocol, or at least two states in the consistency protocol correspond to a merged state recorded in the consistency directory.

4. The method according to claim 3, characterized in that The state of the consistency directory record corresponds to the state of the consistency protocol one by one; the state transition rule based on the access type of the access request and the current state of the target cache data block is used to determine whether the current state of the target cache data block is maintained, including: The situation of determining whether the current state of the target cache data block is maintained includes at least one of the following: The current state of the target cache data block is an exclusive state, and the access type of the access request is a local read; The current state of the target cache data block is a modification state, and the access type of the access request is a local read or a local write; The current state of the target cache data block is a shared state, and the access type of the access request is a local read or a remote read.

5. The method according to claim 3, characterized in that: The state of the consistency directory record corresponds to the state of the consistency protocol one by one; the state transition rule based on the access type of the access request and the current state of the target cache data block is used to determine whether the current state of the target cache data block is maintained, including: The situation where it is determined that the current state of the target cache data block is not maintained includes at least one of the following: The current state of the target cache data block is an exclusive state, and the access type of the access request is remote read or remote write; The current state of the target cache data block is a modification state, and the access type of the access request is remote read or remote write; The current state of the target cache data block is a shared state, and the access type of the access request is a local write or a remote write; The current state of the target cache data block is an invalid state, and the access type of the access request is local read or local write.

6. The method according to claim 1, characterized in that The cache information recorded by the coarse-grained entry includes: A tag, used to identify multiple cache data blocks corresponding to the coarse-grained entry; Current state, used to indicate the current state of multiple cache data blocks corresponding to the coarse-grained entry; Owner information, used to indicate owners of multiple cache data blocks corresponding to the coarse-grained entries; And, a valid cache identifier is used to indicate a valid cache data block among multiple cache data blocks corresponding to the coarse-grained entry, and the valid cache data block is a cache data block that currently stores cache information in the coarse-grained entry.

7. The method according to claim 6, characterized in that The partial entries of the consistency directory cached by the directory cache include: partial coarse-grained entries; Determining whether the access request hits the directory cache includes: Check whether the index and tag of the coarse-grained entry cached by the directory cache matches the index and tag of the request address of the access request, and whether the bit corresponding to the block offset of the valid cache identifier and the request address is a valid value, where the tag of the request address is the remaining address portion after removing the block offset and index of the request address; Among them, the index and tag of the coarse-grained entry match the index and tag of the request address of the access request, and the coarse-grained entry whose bits corresponding to the block offset of the valid cache identifier and the request address are valid values ​​is the coarse-grained entry that the access request hits in the directory cache.

8. The method according to claim 7, characterized in that The valid cache identifier includes multiple bits, each bit represents a cache data block among multiple cache data blocks corresponding to the coarse-grained entry, and is mapped to the block offset of the cache data block; if the value of a bit in the valid cache identifier is a valid value, the cache data block corresponding to the bit is a valid cache data block; if the value of a bit in the valid cache identifier is an invalid value, the cache data block corresponding to the bit is an invalid cache data block.

9. The method according to claim 1, characterized in that: The partial entries of the consistency directory cached by the directory cache include: partial fine-grained entries; Determining whether the access request hits the directory cache includes: Check whether the label and index of the fine-grained entry cached by the directory cache matches the label and index of the request address of the access request; Among them, the fine-grained entry whose tag and index both match the tag and index of the request address of the access request is the fine-grained entry hit by the access request in the directory cache.

10. The method according to claim 1, characterized in that The partial entries of the consistency directory cached by the directory cache include: partial coarse-grained entries and partial fine-grained entries.

11. The method according to claim 1, characterized in that: Also includes: If the access request causes the state of the target cache data block recorded in the consistency directory to change, the consistency directory is accessed, and the consistency directory and the directory cache are updated, or the directory cache is updated.

12. The method according to claim 11, characterized in that If the access request causes the state of the target cache data block recorded in the consistency directory to change, accessing the consistency directory includes: If the access request causes the state of the target cache data block recorded in the consistency directory to change, the coarse-grained directory and the fine-grained directory are accessed, or the directory to be accessed is determined based on the state of the target cache data block change, the correspondence between the coarse-grained directory and the recorded state, and the correspondence between the fine-grained directory and the recorded state.

13. The method according to claim 11, characterized in that The directory cache caches some coarse-grained entries; if the access request causes the state of the target cache data block recorded in the consistency directory to change, then access the consistency directory and update the consistency directory and the directory cache, or update the directory cache includes: If the access request causes a change in the state of the target cache data block recorded in the consistency directory, access the fine-grained directory and determine whether the new cache information of the target cache data block is suitable for storage in the coarse-grained directory; If so, update the directory cache; If not, update the coarse-grained directory and the fine-grained directory, migrate the cache information of the target cache data block from the coarse-grained directory to the fine-grained directory, update the new cache information of the target cache data block in the fine-grained directory, and, based on the cache information of the target cache data block being migrated from the coarse-grained directory to the fine-grained directory, synchronously update the directory cache.

14. The method according to claim 1, characterized in that Also includes: If the access request misses the directory cache, the coarse-grained directory and the fine-grained directory are accessed.

15. A directory controller, characterized in that: include: A consistency directory, wherein the consistency directory includes a coarse-grained directory and a fine-grained directory, wherein the coarse-grained directory includes a plurality of coarse-grained entries, wherein one coarse-grained entry records cache information of a plurality of cache data blocks, and the fine-grained directory includes a plurality of fine-grained entries, wherein one fine-grained entry records cache information of one cache data block; A directory cache, wherein the directory cache caches some entries of a consistent directory; A control circuit, used to obtain an access request, wherein the access request is used to access cache information of a target cache data block in a consistency directory; Determining whether the access request hits the directory cache; If the access request hits the directory cache, calling the optimization logic to determine whether the access request causes a change in the state of the target cache data block in the consistency directory record; If the optimization logic determines that the access request does not cause a change in the state of the target cache data block recorded in the consistency directory, then based on cache information of the target cache data block hit in the directory cache, determining response information of the access request; The optimization logic is used for making optimization decisions based on the call of the controlled circuit, including determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory.

16. The directory controller according to claim 15, characterized in that: The optimization logic for determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory includes: Using the access type of the access request and the current state of the target cache data block, it is determined whether the access request causes a change in the state of the target cache data block recorded in the consistency directory.

17. The directory controller according to claim 16, characterized in that: The optimization logic, for determining whether the access request causes a change in the state of the target cache data block recorded in the consistency directory by using the access type of the access request and the current state of the target cache data block, includes: Based on the state transition rule, using the access type of the access request and the current state of the target cache data block, determining whether the current state of the target cache data block is maintained, or whether the current state and the changed state belong to a merged state of the consistency directory record; The states recorded in the consistency directory correspond one-to-one to the states of the consistency protocol, or at least two states in the consistency protocol correspond to a merged state recorded in the consistency directory.

18. The directory controller according to claim 17, characterized in that: The state of the consistency directory record corresponds to the state of the consistency protocol one by one; the optimization logic is used to determine whether the current state of the target cache data block is maintained based on the state transition rule using the access type of the access request and the current state of the target cache data block: The situation of determining whether the current state of the target cache data block is maintained includes at least one of the following: The current state of the target cache data block is an exclusive state, and the access type of the access request is a local read; The current state of the target cache data block is a modification state, and the access type of the access request is a local read or a local write; The current state of the target cache data block is a shared state, and the access type of the access request is a local read or a remote read.

19. The directory controller according to claim 17, characterized in that: The state of the consistency directory record corresponds to the state of the consistency protocol one by one; the optimization logic is used to determine whether the current state of the target cache data block is maintained based on the state transition rule using the access type of the access request and the current state of the target cache data block: The situation where it is determined that the current state of the target cache data block is not maintained includes at least one of the following: The current state of the target cache data block is an exclusive state, and the access type of the access request is remote read or remote write; The current state of the target cache data block is a modification state, and the access type of the access request is remote read or remote write; The current state of the target cache data block is a shared state, and the access type of the access request is a local write or a remote write; The current state of the target cache data block is an invalid state, and the access type of the access request is local read or local write.

20. The directory controller according to claim 15, characterized in that: The cache information recorded by the coarse-grained entry includes: A tag, used to identify multiple cache data blocks corresponding to the coarse-grained entry; Current state, used to indicate the current state of multiple cache data blocks corresponding to the coarse-grained entry; Owner information, used to indicate owners of multiple cache data blocks corresponding to the coarse-grained entries; And, a valid cache identifier is used to indicate a valid cache data block among multiple cache data blocks corresponding to the coarse-grained entry, and the valid cache data block is a cache data block that currently stores cache information in the coarse-grained entry.

21. The directory controller according to claim 20, characterized in that: The partial entries of the consistency directory cached by the directory cache include: partial coarse-grained entries; the control circuit for determining whether the access request hits the directory cache includes: Check whether the index and tag of the coarse-grained entry cached by the directory cache matches the index and tag of the request address of the access request, and whether the bit corresponding to the block offset of the valid cache identifier and the request address is a valid value, where the tag of the request address is the remaining address portion after removing the block offset and index of the request address; Among them, the index and tag of the coarse-grained entry match the index and tag of the request address of the access request, and the bits corresponding to the block offset of the valid cache identifier and the request address are coarse-grained entries with valid values, which are the coarse-grained entries that the access request hits in the directory cache.

22. The directory controller according to claim 21, characterized in that The valid cache identifier includes multiple bits, each bit represents a cache data block among multiple cache data blocks corresponding to the coarse-grained entry, and is mapped to the block offset of the cache data block; if the value of a bit in the valid cache identifier is a valid value, the cache data block corresponding to the bit is a valid cache data block; if the value of a bit in the valid cache identifier is an invalid value, the cache data block corresponding to the bit is an invalid cache data block.

23. The directory controller according to claim 15, characterized in that: The partial entries of the consistency directory cached by the directory cache include: partial fine-grained entries; The control circuit, for determining whether the access request hits the directory cache, comprises: Check whether the label and index of the fine-grained entry cached by the directory cache matches the label and index of the request address of the access request; Among them, the fine-grained entry whose tag and index both match the tag and index of the request address of the access request is the fine-grained entry hit by the access request in the directory cache.

24. The directory controller according to claim 15, characterized in that: The partial entries of the consistency directory cached by the directory cache include: partial coarse-grained entries and partial fine-grained entries.

25. The directory controller according to claim 15, characterized in that: The control circuit is further configured to access the consistency directory and update the consistency directory and the directory cache, or update the directory cache, if the optimization logic determines that the access request causes a change in the state of the target cache data block recorded in the consistency directory.

26. The directory controller according to claim 25, characterized in that The control circuit is configured to, if the optimization logic determines that the access request causes a change in the state of the target cache data block recorded in the consistency directory, access the consistency directory, including: If the access request causes the state of the target cache data block recorded in the consistency directory to change, the coarse-grained directory and the fine-grained directory are accessed, or the directory to be accessed is determined based on the state of the target cache data block change, the correspondence between the coarse-grained directory and the recorded state, and the correspondence between the fine-grained directory and the recorded state.

27. The directory controller according to claim 25, characterized in that: The directory cache caches some coarse-grained entries; the control circuit is used to access the consistency directory and update the consistency directory and the directory cache if the optimization logic determines that the access request causes the state of the target cache data block recorded in the consistency directory to change, or updating the directory cache includes: If the access request causes a change in the state of the target cache data block recorded in the consistency directory, access the fine-grained directory and determine whether the new cache information of the target cache data block is suitable for storage in the coarse-grained directory; If so, update the directory cache; If not, update the coarse-grained directory and the fine-grained directory, migrate the cache information of the target cache data block from the coarse-grained directory to the fine-grained directory, update the new cache information of the target cache data block in the fine-grained directory, and, based on the cache information of the target cache data block being migrated from the coarse-grained directory to the fine-grained directory, synchronously update the directory cache.

28. The directory controller according to claim 15, characterized in that: The control circuit is further configured to access the coarse-grained directory and the fine-grained directory if the access request does not hit the directory cache.

29. A computer device, characterized in that: Comprising a directory controller as described in any one of claims 15-28.

30. The computer device according to claim 29, characterized in that Also includes: Multiple processor domains, a processor domain may include multiple processor cores; Cache for each processor domain; Multiple consistent master nodes; bus, and system memory.

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