Improved ABSPD clock recovery method under single baud rate sampling

Abstract

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed optical signal processing, and more specifically, to an improved ABSPD clock recovery method under single baud rate sampling. Background Art

[0002] In order to meet the growing demand for data traffic, it will become a future trend to apply coherent technology to short-distance optical interconnection applications to support large-capacity data transmission. However, due to the high complexity of the digital signal processing (DSP) algorithm of traditional coherent optical communication systems, it cannot be directly applied to short-distance data center optical interconnection application scenarios. Therefore, it is necessary to simplify the traditional coherent optical communication algorithms. In the DSP algorithms of traditional coherent systems, the commonly used clock recovery algorithms usually have a large dependence on the oversampling rate of the receiver. The classic time domain Gardner algorithm, Lee algorithm, and frequency domain Godard algorithm all require twice oversampling, resulting in a high computational complexity of the algorithm.

[0003] In order to reduce the complexity of the clock recovery algorithm, the improved Lee algorithm in the time domain and the improved Godard algorithm in the frequency domain have been proposed to enable them to work under non-integer oversampling conditions, thereby reducing the computational complexity of the clock recovery loop. However, these algorithms still require a certain oversampling rate. In order to further reduce the computational complexity of the algorithm, it is necessary to explore clock recovery algorithms suitable for single baud rate sampling. The Mueller & Müller (MM) algorithm is a single baud rate clock recovery algorithm commonly used in intensity modulation direct detection systems. However, the algorithm is very sensitive to frequency deviation, phase noise and dispersion damage in coherent systems, and various damages need to be compensated in the loop, thereby increasing the complexity and delay of the entire clock recovery loop. Therefore, the MM algorithm is not suitable for coherent systems. In addition, a clock recovery algorithm called ABSPD (absolute phase detector) has been proposed for use in coherent optical communication systems and can work under single baud rate sampling. However, this ABSPD algorithm involves too many multiplication operations in the process of calculating the timing error, resulting in a high computational complexity, which affects the implementation of the scheme in the actual system. Summary of the invention

[0004] The purpose of the present invention is to overcome the disadvantage that the prior art ABSPD algorithm involves too many multiplication operations in the process of calculating the timing error, thereby resulting in a high computational complexity. An improved ABSPD clock recovery method under single baud rate sampling is provided to avoid the use of complex multiplication operations in the timing error calculation process, thereby realizing ABSPD clock recovery under single baud rate sampling without multiplication operations, and significantly reducing the complexity of the entire clock recovery loop.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] An improved ABSPD clock recovery method under single baud rate sampling is provided, which realizes the clock synchronization of the signal of the transmitting and receiving end through a fully digital clock recovery loop, wherein the fully digital clock recovery loop comprises an interpolation filter, a timing error detector, a loop filter and a digitally controlled oscillator; when calculating the timing error e, the timing error detector uses symbol judgment and shift operation to replace the numerical multiplication operation; after the timing error e is calculated by the timing error detector, the timing error e is input into the loop filter for noise filtering to obtain a control word W; then the control word W is used to control the digitally controlled oscillator, and the fractional interval μ is calculated by the output NCO of the digitally controlled oscillator and the control word W. k ; Use the signed integer mark m k and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter to calculate the data with correct timing.

[0007] The improved ABSPD clock recovery method under single baud rate sampling of the present invention replaces the multiplication operation involving specific numerical values ​​in the traditional ABSPD algorithm with sign judgment and shift operations, thereby avoiding the use of complex multiplication operations in the timing error calculation process, realizing ABSPD clock recovery under single baud rate sampling without multiplication operations, and significantly reducing the complexity of the entire clock recovery loop.

[0008] Preferably, the timing error detector calculates the timing error e in the following manner:

[0009]

[0010] In the formula, x I and x Q are the real and imaginary parts of the received signal x, respectively. N is the length of a data block required for calculating the timing error each time. k represents the pointer of the data in the data block. n represents the time. sign(·) represents the sign operation. |·| represents the absolute value operation.

[0011] Preferably, for formula (1):

[0012] Involving |sign(x I (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q (k-1))| can be realized by shift operation. From formula (1), we can see that sign(xI (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q The value of (k-1))| can only be 0 or 2. Since the multiplication by 2 operation can be realized by a shift operation, the improved ABSPD clock recovery method of the present invention does not need to use a complex multiplication operation.

[0013] Preferably, the timing error detector operates at single baud rate sampling.

[0014] Preferably, the timing error e is input into a loop filter for noise filtering to obtain a control word W, which is calculated by the following formula:

[0015]

[0016] In the formula, LF p and LF I They represent the outputs of the proportional part and the integral part in the loop filter respectively, and k1 and k2 represent the error control coefficients of the proportional part and the integral part respectively.

[0017] Preferably, the control word W is used to control the digital controlled oscillator, and the control process includes:

[0018] NCO(n)=[NCO(n-1)-W(n-1)]mod1(3)

[0019] Where NCO represents the output of the numerically controlled oscillator, and mod represents the modulo operation.

[0020] Preferably, the fractional interval μ is calculated by the output NCO of the numerically controlled oscillator and the control word W. k , calculated using the following formula:

[0021]

[0022] Preferably, m is labeled with a signed integer k and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter to calculate the data with correct timing, which is calculated by the following formula:

[0023]

[0024] Where, T s and T i represent the actual sampling period and the optimal sampling period after clock recovery respectively, and y is the symbol after clock recovery.

[0025] The present invention also provides an optical communication method. In the digital signal processing at the transmitting end, a pseudo-random bit sequence is first mapped into a 16QAM symbol to generate two 50Gbuad 16QAM signals, and a root raised cosine filter with a roll-off factor of 0 is used to perform Nyquist shaping on the QAM symbol, and finally the signal is resampled; in the digital signal processing at the receiving end, dispersion compensation is performed on the received signal, and then the clock recovery method described above is used to perform clock recovery at a single baud rate; after clock recovery, equalization is performed using an equalizer working at a single baud rate, and finally the bit error rate is calculated.

[0026] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-described method when executing the computer program.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The improved ABSPD clock recovery method under single baud rate sampling of the present invention can realize clock recovery under single baud rate sampling in a coherent optical communication system, and the present invention avoids a large number of multiplication operations when calculating the timing error in the clock recovery loop by replacing the numerical multiplication operation in the traditional ABSPD clock recovery algorithm with symbol judgment and shift operations, thereby significantly reducing the computational complexity of the clock recovery loop while ensuring that the algorithm can work under single baud rate sampling. In addition, based on the realization of single baud rate sampling clock recovery based on the proposed scheme, the subsequent equalizer can be further simplified from a two-times oversampling equalizer architecture to a single-times sampling equalizer architecture, thereby significantly reducing the DSP complexity of the receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the fully digital clock recovery loop structure.

[0030] Figure 2 The figure is a schematic diagram showing the principle of the improved ABSPD clock recovery method of the present invention.

[0031] Figure 3 This is a diagram of a simulation system device of Embodiment 2.

[0032] Figure 4 This is a schematic diagram of the S curve of the traditional ABSPD algorithm.

[0033] Figure 5 It is a schematic diagram of the S curve of the improved ABSPD clock recovery method of the present invention.

[0034] Figure 6 Schematic diagram of the performance of different ABSPD algorithms when there is a 10ppm sampling frequency deviation.

[0035] Figure 7 Schematic diagram of the performance of different ABSPD algorithms when there is a 30ppm sampling frequency deviation.

[0036] Figure 8 Schematic diagram of the performance of different ABSPD algorithms when there is a 40ppm sampling frequency deviation. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with specific implementation methods. The accompanying drawings are only used for exemplary descriptions and are only schematic diagrams, not actual drawings, and cannot be understood as limiting this patent; in order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0038] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0039] Embodiment 1

[0040] This embodiment is a first embodiment of an improved ABSPD clock recovery method under single baud rate sampling, which realizes the clock synchronization of the transmitting and receiving end signals through a fully digital clock recovery loop. Figure 1 The structure of this all-digital clock recovery loop is given. Figure 1 It can be seen that the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter and a digitally controlled oscillator; the timing error detector operates at a single baud rate sampling, and when calculating the timing error e, a sign judgment and a shift operation are used to replace a numerical multiplication operation; Figure 2 The principle block diagram of the present invention is given; the timing error e is calculated by the timing error detector, and its calculation principle is as follows:

[0041]

[0042] In the formula, x I and x Qare the real and imaginary parts of the received signal x, respectively. N is the length of a data block required for calculating the timing error each time. k represents the pointer of the data in the data block. n represents the time. sign(·) represents the sign operation. |·| represents the absolute value operation.

[0043] From formula (1), we can see that |sign(x I (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q The value of (k-1))| can only be 0 or 2. Since the multiplication by 2 operation can be realized by a shift operation, the improved ABSPD clock recovery method of the present invention does not need to use a complex multiplication operation.

[0044] After the timing error e is calculated, the timing error e is input into the loop filter for noise filtering to obtain the control word W. The process can be described as:

[0045]

[0046] In the formula, LF p and LF I They represent the outputs of the proportional part and the integral part in the loop filter respectively, and k1 and k2 represent the error control coefficients of the proportional part and the integral part respectively.

[0047] Then use the control word W to control the digital controlled oscillator, and the control process is:

[0048] NCO(n)=[NCO(n-1)-W(n-1)]mod1(3)

[0049] Where NCO represents the output of the numerically controlled oscillator, and mod represents the modulo operation.

[0050] Next, the fractional interval μ is calculated from the output NCO of the numerically controlled oscillator and the control word W. k :

[0051]

[0052] Finally, use the integer notation m k and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter to calculate the data with correct timing. The process is expressed as:

[0053]

[0054] Where, T s and T irepresent the actual sampling period and the optimal sampling period after clock recovery respectively, and y is the symbol after clock recovery.

[0055] The improved ABSPD clock recovery method under single baud rate sampling of the present invention replaces the multiplication operation involving specific numerical values ​​in the traditional ABSPD algorithm with sign judgment and shift operations, thereby avoiding the use of complex multiplication operations in the timing error calculation process, realizing ABSPD clock recovery under single baud rate sampling without multiplication operations, and significantly reducing the complexity of the entire clock recovery loop.

[0056] Compared with commonly used clock recovery algorithms such as the classic time domain Gardner algorithm, Lee algorithm and frequency domain Godard algorithm, the present invention can effectively reduce the system oversampling rate required for clock recovery at the receiving end, and realize clock recovery at a low complexity single baud rate. In addition, compared with the traditional single baud rate ABSPD algorithm suitable for coherent systems, the present invention adopts symbol judgment and shift operations to replace the numerical multiplication operations in the traditional ABSPD algorithm, thereby avoiding a large number of multiplication operations when calculating the timing error, thereby significantly reducing the computational complexity of the clock recovery algorithm.

[0057] Embodiment 2

[0058] This embodiment is based on the clock recovery method proposed in the first embodiment, and the method is analyzed and verified through simulation.

[0059] The effectiveness of the present invention is verified in a homologous coherent system. Figure 3 The simulation system device diagram of the present invention is given. The optical carrier at the transmitting end is generated by a laser with a line width of 100kHz and an output power of 16dBm. The carrier is divided into two branches by a coupler, the upper branch is used for signal modulation, and the lower branch is used as a local oscillator light source (LO). In the signal modulation part, the optical carrier used for signal modulation is divided into two orthogonal polarized lights, X polarization and Y polarization, by a polarization beam splitter (PBS), and respectively input into two IQ modulators (IQM) for signal modulation. The two 50Gbaud single-carrier 16QAM signals generated offline at the transmitting end are respectively loaded into two IQMs to realize electro-optical conversion. The signals output by the two modulators are coupled by a polarization beam combiner (PBC) and then input into 80 kilometers of optical fiber for transmission. The optical signal-to-noise ratio (OSNR) module is used in the simulation to adjust the OSNR of the system. After the LO is transmitted to the receiving end through the same length of optical fiber, the sum signal is divided into two orthogonal polarization states by a PBS, and then input into two 90° optical mixers and detected by four pairs of photodetectors (PD). The detected data is processed in the DSP at the receiving end. The sampling rate used by the system is 80GSa / s.

[0060] (1) Transmitter DSP

[0061] In the transmitter DSP, the pseudo-random bit sequence is first mapped into 16QAM symbols to generate two 50Gbuad 16QAM signals, and the QAM symbols are Nyquist-shaped using a root raised cosine filter with a roll-off factor of 0, and finally the signal is resampled.

[0062] (2) DSP at the receiving end

[0063] In the receiving end DSP, dispersion compensation is first performed on the received signal, and then clock recovery is performed at a single baud rate using the improved ABSPD clock recovery method proposed in Example 1. After clock recovery, equalization is performed using an equalizer working at a single baud rate, and finally the bit error rate is calculated.

[0064] Result analysis:

[0065] based on Figure 3 The simulation device is used to first compare the S curve of the traditional ABSPD algorithm and the S curve of the improved ABSPD algorithm proposed in the present invention. The results are as follows: Figure 4 and Figure 5 As shown in Figure 2. According to the S curve, the jitter size of the two algorithms at the zero point can be obtained, and Figure 4 and Figure 5 As shown in the figure, the jitter of the traditional ABSPD algorithm and the improved ABSPD algorithm are -40.9dB and -41.3dB respectively, that is, the two algorithms show similar jitter performance.

[0066] Figure 6 The bit error rate performance comparison between the proposed improved ABSPD clock recovery method and the traditional ABSPD method is given when the system sampling phase deviation and sampling frequency deviation are 5ps and 10ppm respectively, and is also compared with the case where there is no timing error. It can be seen from the figure that when there is a sampling phase deviation of 5ps and a sampling frequency deviation of 10ppm, the method of the present invention can obtain almost the same performance as the traditional ABSPD algorithm, and compared with the case where there is no timing error, it has almost no optical signal-to-noise ratio loss at the hard decision threshold.

[0067] Figure 7The bit error rate curves of the method of the present invention and the traditional ABSPD algorithm are given when the system sampling phase deviation and sampling frequency deviation are 5ps and 30ppm respectively, and are also compared with the case where there is no timing error. It can be seen from the figure that when there is a sampling phase deviation of 5ps and a sampling frequency deviation of 30ppm, the method of the present invention can obtain almost the same performance as the traditional ABSPD algorithm, and compared with the case where there is no timing error, the two algorithms only have an optical signal-to-noise ratio loss of about 0.3dB at the hard decision threshold.

[0068] Figure 8 The bit error rate performance comparison between the method of the present invention and the traditional ABSPD algorithm is given when the system sampling phase deviation and sampling frequency deviation are 5ps and 40ppm respectively, and compared with the case where there is no timing error. Similarly, when there is a sampling phase deviation of 5ps and a sampling frequency deviation of 40ppm, the bit error rate curves of the method of the present invention and the traditional ABSPD algorithm are almost overlapped. Compared with the case where there is no timing error, the two algorithms have an optical signal-to-noise ratio loss of about 0.5dB at the hard decision threshold.

[0069] Embodiment 3

[0070] This embodiment provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described in Embodiment 1 when executing the computer program.

[0071] In the specific contents of the above-mentioned specific implementation methods, the various technical features can be combined in any non-contradictory manner. In order to make the description concise, not all possible combinations of the above-mentioned technical features are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. An improved ABSPD clock recovery method under single baud rate sampling, characterized in that: A clock synchronization of the transmitting and receiving end signals is achieved by a fully digital clock recovery loop, wherein the fully digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter and a digitally controlled oscillator; The timing error detector uses sign determination and shift operations to replace numerical multiplication operations when calculating the timing error e; After the timing error e is calculated by the timing error detector, the timing error e is input into the loop filter for noise filtering to obtain the control word W; then the control word W is used to control the numerically controlled oscillator, and the fractional interval μ is calculated by the output NCO of the numerically controlled oscillator and the control word W. k ; Use the signed integer m k and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter to calculate the data with correct timing.

2. The improved ABSPD clock recovery method under single baud rate sampling according to claim 1, characterized in that: The timing error detector calculates the timing error e in the following manner: In the formula, x I and x Q are the real and imaginary parts of the received signal x, respectively. N is the length of a data block required for calculating the timing error each time. k represents the pointer to the data in the data block. n represents the time. sign(·) represents the sign operation. |·| represents the absolute value operation.

3. The improved ABSPD clock recovery method under single baud rate sampling according to claim 2, characterized in that: In formula (1): |sign(x I (k))+sign(x I (k-1))| and |sign(x Q (k))+sign(x Q The multiplication operation of (k-1))| is implemented using a shift operation.

4. The improved ABSPD clock recovery method under single baud rate sampling according to claim 2, characterized in that: The timing error detector operates at single baud rate sampling.

5. The improved ABSPD clock recovery method under single baud rate sampling according to claim 2, characterized in that: The timing error e is input into the loop filter for noise filtering to obtain the control word W, which is calculated by the following formula: In the formula, LF p and LF I They represent the outputs of the proportional part and the integral part in the loop filter respectively, and k1 and k2 represent the error control coefficients of the proportional part and the integral part respectively.

6. The improved ABSPD clock recovery method under single baud rate sampling according to claim 5, characterized in that: The control word W is used to control the digital controlled oscillator. The control process includes: NCO(n)=[NCO(n-1)-W(n-1)]mod1(3) Where NCO represents the output of the numerically controlled oscillator, and mod represents the modulo operation.

7. The improved ABSPD clock recovery method under single baud rate sampling according to claim 6, characterized in that: The fractional interval μ is calculated from the output NCO of the numerically controlled oscillator and the control word W. k , calculated using the following formula:

8. The improved ABSPD clock recovery method under single baud rate sampling according to claim 7, characterized in that: Use the signed integer notation m k and the calculated fractional interval μ k The received signal is interpolated in the interpolation filter to calculate the data with correct timing, which is calculated by the following formula: Where, T s and T i represent the actual sampling period and the optimal sampling period after clock recovery respectively, and y is the symbol after clock recovery.

9. An optical communication method, characterized in that: In the digital signal processing at the transmitting end, the pseudo-random bit sequence is first mapped into a 16QAM symbol to generate two 50Gbuad 16QAM signals, and the QAM symbol is Nyquist shaped using a root raised cosine filter with a roll-off factor of 0, and finally the signal is resampled; in the digital signal processing at the receiving end, the received signal is dispersion compensated, and then the clock recovery method described in any one of claims 1 to 8 is used to perform clock recovery at a single baud rate; After clock recovery, an equalizer operating at single baud rate is used for equalization, and finally the bit error rate is calculated.

10. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, and the processor implements the steps of the method described in any one of claims 1 to 8 when executing the computer program.

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