Frequency locking loop and control method thereof

Abstract

The embodiment of the invention discloses a frequency locking loop and a control method thereof, and the frequency locking loop comprises a numerical control oscillator which is configured to generate a corresponding target frequency signal based on a target control signal, and control a loop control switch to execute a corresponding action based on the frequency signal; the high-frequency counter is configured to count the numerical control oscillator to obtain an actual count value; an ideal count value unit configured to generate an ideal count value within a preset time window; the frequency identification unit is configured to judge whether the difference value between the actual count value and the ideal count value meets a preset difference value threshold value or not; and the frequency regulation control unit is configured to generate a target control signal based on a preset difference threshold value if the judgment result is satisfied, so as to control the numerical control oscillator to generate a target frequency signal. According to the frequency locking method and device, the technical problems that in the prior art, power consumption is large and the locking speed is low when frequency locking is carried out are solved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of frequency control, and in particular to a frequency locked loop and a control method thereof. Background Art

[0002] In low-power transmitters, the power consumption of the local oscillator generation circuit is dominant. To reduce power consumption, the local oscillator generation circuit can adopt an intermittent working mode. When the frequency locking loop is closed, the frequency of the digital controlled oscillator is locked; when the frequency locking loop is disconnected, the digital controlled oscillator is in a free oscillation state.

[0003] In the prior art, there are usually two methods for frequency locking: (1) an analog frequency locked loop based on a charge pump. In this method, the locking speed is proportional to the charge pump current, resulting in high power consumption; (2) a synchronously locked digital frequency locked loop. In this method, the locking of each bit of the frequency control word requires the same counting time to ensure frequency accuracy, and the locking speed is relatively slow. Summary of the invention

[0004] The embodiment of the present invention provides a frequency locked loop and a control method thereof, which solves the technical problems of high power consumption and slow locking speed in the prior art for locking the frequency.

[0005] An embodiment of the present invention provides a frequency locked loop, the frequency locked loop comprising:

[0006] a digitally controlled oscillator configured to generate a corresponding target frequency signal based on a target control signal, and to control a loop control switch to perform a corresponding action based on the frequency signal;

[0007] A high frequency counter configured to count the digital controlled oscillator to obtain an actual count value;

[0008] an ideal count value unit, configured to generate an ideal count value within a preset time window;

[0009] a frequency identification unit, configured to determine whether a difference between the actual count value and the ideal count value satisfies a preset difference threshold;

[0010] The frequency adjustment control unit is configured to generate the target control signal based on the difference if the judgment result is satisfied, so as to control the digital controlled oscillator to generate the target frequency signal.

[0011] Further, the frequency identification unit includes a frequency identifier and an error identifier;

[0012] The frequency discriminator is configured to obtain the actual count value and the ideal count value and calculate a difference between the actual count value and the ideal count value;

[0013] The error identifier is configured to determine whether the difference calculated by the frequency identifier satisfies the preset difference threshold.

[0014] Furthermore, the frequency locked loop further comprises a reference counting unit;

[0015] The reference counting unit is configured to generate the preset time window based on a reference clock.

[0016] Further, the reference counting unit includes a reference clock and a reference counter;

[0017] The reference clock is configured to input a clock of a set frequency to the reference counter;

[0018] The reference counter is configured to generate the preset time window based on a clock input of the reference clock.

[0019] Furthermore, the frequency locked loop also includes a counting threshold unit;

[0020] The counting threshold unit is configured to generate a counting duration for the numerically controlled oscillator and send the counting duration to the reference counter.

[0021] Further, the frequency locked loop also includes the loop control switch;

[0022] The loop control switch is configured to be turned on under the control of an enable control signal and to perform a corresponding action based on the frequency signal sent by the digitally controlled oscillator.

[0023] Furthermore, the frequency locked loop further includes a finite state machine;

[0024] The finite state machine is configured to control a current state of the loop control switch.

[0025] An embodiment of the present invention further provides a method for controlling a frequency locked loop, the method comprising:

[0026] The high frequency counter counts the numerically controlled oscillator to obtain the actual count value;

[0027] The ideal count value unit generates an ideal count value within a preset time window;

[0028] The frequency identification unit receives the actual count value and the ideal count value, and determines whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold;

[0029] If the judgment result of the frequency identification unit is satisfied, the frequency adjustment control unit generates a target control signal based on the difference;

[0030] The digital controlled oscillator generates a corresponding target frequency signal based on the target control signal, and controls a loop control switch to perform a corresponding action based on the target frequency signal.

[0031] Further, the frequency identification unit receives the actual count value and the ideal count value, and determines whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold, including:

[0032] The frequency identification unit receives the actual count value and the ideal count value, and subtracts the actual count value from the ideal count value and takes an absolute value to obtain a difference between the actual count value and the ideal count value;

[0033] It is determined whether the obtained difference satisfies a preset difference threshold.

[0034] Furthermore, the control method further includes:

[0035] If the determination result of the frequency identification unit is not satisfied, the actual count value and the ideal count value are received, and the action of determining whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold is continued.

[0036] The embodiment of the present invention discloses a frequency locked loop and a control method thereof, wherein the frequency locked loop comprises: a digitally controlled oscillator, configured to generate a corresponding target frequency signal based on a target control signal, and to control a loop control switch to perform a corresponding action based on a frequency signal; a high frequency counter, configured to count the digitally controlled oscillator to obtain an actual count value; an ideal count value unit, configured to generate an ideal count value within a preset time window; a frequency identification unit, configured to determine whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold; and a frequency adjustment control unit, configured to generate a target control signal based on a preset difference threshold if the judgment result is satisfied, so as to control the digitally controlled oscillator to generate a target frequency signal. The present application generates a target control signal according to the error of the current count value, realizes the control of the output frequency of the digitally controlled oscillator, and solves the technical problems of high power consumption and slow locking speed in the prior art of frequency locking by intermittent frequency locking of the digitally controlled oscillator, realizes a technical effect of greatly reducing average power consumption and improving locking speed while ensuring frequency accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a structural diagram of a frequency locked loop provided by an embodiment of the present invention;

[0038] Figure 2 is a structural diagram of another frequency locked loop provided by an embodiment of the present invention;

[0039] Figure 3 is a calibration timing diagram of a frequency locked loop provided by an embodiment of the present invention;

[0040] Figure 4 The present invention provides a flow chart of a method for controlling a frequency locked loop. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish different objects, rather than to limit a specific order. The following embodiments of the present invention can be implemented separately, or in combination with each other, and the embodiments of the present invention do not impose specific limitations on this.

[0043] Figure 1 It is a structural diagram of a frequency locked loop provided by an embodiment of the present invention.

[0044] like Figure 1 As shown, the frequency locked loop specifically includes:

[0045] The digital controlled oscillator 10 is configured to generate a corresponding target frequency signal based on the target control signal, and control the loop control switch 80 to perform a corresponding action based on the target frequency signal;

[0046] The high frequency counter 20 is configured to count the numerically controlled oscillator 10 to obtain an actual count value;

[0047] An ideal count value unit 30, configured to generate an ideal count value within a preset time window;

[0048] The frequency identification unit 40 is configured to determine whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold;

[0049] The frequency adjustment control unit 50 is configured to generate a target control signal based on the difference if the judgment result is satisfied, so as to control the digital controlled oscillator to generate a target frequency signal.

[0050] Specifically, the target frequency signal output by the digitally controlled oscillator 10 (Digitally Controlled Oscillator DCO) is regulated by a set of binary frequency control words. In the embodiment of the present invention, the frequency locked loop calibrates each bit of the frequency control word to make it output the expected frequency. The high frequency counter 20 (HF counter) generates an actual count value by counting the digitally controlled oscillator 10, and its operating frequency is in the GHz range. The ideal count value generated by the ideal count value unit 30 (Ideal Counting Value) is the ideal count value of the target locked frequency output by the desired digitally controlled oscillator 10 for a fixed time window, wherein the fixed time window is the above-mentioned preset time window, which is usually determined based on the output value of the reference clock.

[0051] The frequency identification unit 40 is used to obtain the actual count value and the ideal count value, calculate the difference between the two, and then determine whether the difference between the actual count value and the ideal count value meets the preset difference threshold; wherein the preset difference threshold is determined based on the frequency accuracy of the desired output of the numerically controlled oscillator 10. The frequency adjustment control unit 50 (TuningController) is used to receive the judgment result of the frequency identification unit 40, and when the judgment result is satisfied, generate a calibrated frequency control word based on the difference between the actual count value and the ideal count value, that is, the above-mentioned target control signal, to control the numerically controlled oscillator 10 to output the target frequency signal, and finally use the target frequency signal to control the loop control switch 80 to perform the corresponding action.

[0052] In an embodiment of the present invention, a frequency locking loop based on a counter capable of making a pre-determination is adopted to determine the initial calibration position according to the error value of the current counting frequency, thereby reducing unnecessary high-order control word calibration; it can both ensure frequency accuracy and save frequency locking time; by using it to intermittently lock the frequency of the numerically controlled oscillator, the average power consumption can be greatly reduced.

[0053] Figure 2 It is a structural diagram of another frequency locked loop provided by an embodiment of the present invention.

[0054] Alternatively, if Figure 2 As shown, the frequency identification unit 40 includes a frequency identifier 41 and an error identifier 42; the frequency identifier 41 is configured to obtain an actual count value and an ideal count value, and calculate the difference between the two; the error identifier 42 is configured to determine whether the difference calculated by the frequency identifier 41 meets a preset difference threshold.

[0055] Specifically, the frequency detector 41 is used to calculate the difference between the actual count value and the ideal count value, and to obtain the absolute value of the difference. The error detector 42 defines the loop behavior according to the difference between the two count values, that is, when the frequency error (i.e., the difference between the two count values) is less than the preset difference threshold, the loop is locked; when the frequency error is greater than the preset difference threshold, the calibration continues.

[0056] Alternatively, if Figure 2 As shown, the frequency locked loop further includes a reference counting unit 60; the reference counting unit 60 is configured to generate a preset time window based on a reference clock.

[0057] Alternatively, see Figure 2 The reference counting unit 60 includes a reference clock 61 and a reference counter 62; the reference clock 61 is configured to input a clock of a set frequency to the reference counter; the reference counter 62 is configured to generate a preset time window based on the clock input of the reference clock.

[0058] Specifically, the reference clock 61 (Reference Clock) is used to generate a clock input for the reference counter 62, and its frequency is usually in the MHz range. The reference counter 62 (Reference) counts based on the reference clock 61 and generates a fixed time window, namely the above-mentioned preset time window.

[0059] Alternatively, if Figure 2 As shown, the frequency locked loop further includes a counting threshold unit 70;

[0060] The counting threshold unit 70 is configured to generate a counting duration for the numerically controlled oscillator 10 and send the counting duration to the reference counter 62 .

[0061] Specifically, the counting threshold unit 70 (Counting Threshold) is used to indicate the threshold of the reference counter, which is used to characterize the counting duration of the digital controlled oscillator 10 .

[0062] Alternatively, if Figure 2 As shown, the frequency locked loop further includes a loop control switch 80;

[0063] The loop control switch 80 is configured to be turned on under the control of the enable control signal and to perform corresponding actions based on the frequency signal sent by the digitally controlled oscillator 10 .

[0064] Specifically, the loop control switch 80 (Loop switch) can control the on and off of the entire frequency locked loop. When it is off, the digital controlled oscillator 10 is in a free oscillation state; when it is closed, the loop is in a calibration state.

[0065] Alternatively, if Figure 2 As shown, the frequency locked loop further includes a finite state machine 90;

[0066] Finite state machine 90 is configured to control the current state of loop control switch 80 .

[0067] Specifically, the finite state machine 90 (Finite State Machine, FSM) is configured to control the current state of the loop control switch 80 based on the output of the error discriminator 42. The current state of the loop control switch 80 generally includes four states, namely, an enable state, a single-bit calibration state, a multi-bit calibration state, and a calibration completion state, which are represented by codes 00, 01, 10, and 11. In the calibration process, the first counting result is used to determine the initial calibration position, and the subsequent counting results are used for the calibration of each bit of the frequency control word.

[0068] The finite state machine 90 is further configured to open the control loop and reset the high frequency counter 20 and the counting threshold unit 70 when the frequency is locked.

[0069] Figure 3 This is a calibration timing diagram of a frequency locked loop provided by an embodiment of the present invention.

[0070] See also Figure 3 , Figure 3 This shows the timing diagram of reference clock (Reference Clock), enable signal (Enable), numerically controlled oscillator enable (Osc start), calibration decision counting window (Cal decision counting window), calibration decision calculation (Cal decision calculation), calibration decision completion (Cal decision done), bit-by-bit calibration counting window (Bit<N>Calibration counting window), bit-by-bit calibration calculation (Bit<N>Calibration calculation) and bit-by-bit loop calibration completion (Bit<N>Loop Calibration done).

[0071] Among them, t1 represents the initialization stage, that is, it corresponds to the enable state 00 of the finite state machine 90; it represents the initialization of the internal parameters of the digital loop and the start-up of the digital control oscillator 10. t2 represents the judgment stage, that is, it corresponds to the single-bit calibration state 01 of the finite state machine 90; it represents that the initial calibration position is determined according to the first count difference, and unnecessary high-bit calibration can be skipped. t3 represents the calibration stage, that is, it corresponds to the multi-bit calibration state 10 of the finite state machine 90; it represents that the frequency control word is calibrated from high to low according to the subsequent count difference.

[0072] Figure 4 The present invention provides a flow chart of a method for controlling a frequency locked loop.

[0073] like Figure 4 As shown, the control method of the frequency locked loop specifically includes the following steps:

[0074] S401, a high frequency counter counts the numerically controlled oscillator to obtain an actual count value;

[0075] S402, the ideal count value unit generates an ideal count value within a preset time window;

[0076] S403, the frequency identification unit receives the actual count value and the ideal count value, and determines whether the difference between the actual count value and the ideal count value meets a preset difference threshold;

[0077] S404, if the judgment result of the frequency identification unit is satisfied, the frequency adjustment control unit generates a target control signal based on the difference;

[0078] S405, the digitally controlled oscillator generates a corresponding target frequency signal based on the target control signal, and controls the loop control switch to perform a corresponding action based on the target frequency signal.

[0079] Optionally, S403 specifically includes:

[0080] The frequency identification unit receives the actual count value and the ideal count value, and subtracts the actual count value from the ideal count value and takes the absolute value to obtain the difference between the actual count value and the ideal count value;

[0081] It is determined whether the obtained difference satisfies a preset difference threshold.

[0082] Optionally, the control method further includes:

[0083] If the determination result of the frequency identification unit is not satisfied, the operation of receiving the actual count value and the ideal count value and determining whether the difference between the actual count value and the ideal count value satisfies the preset difference threshold is continued.

[0084] In the embodiment of the present invention, the reference counter counts the reference clock to obtain a preset time window. The output of the numerically controlled oscillator generates an actual count value through statistics of the high-frequency counter, which is compared with the ideal count value (generated by the ideal counting unit) of the target locking frequency within the preset time window. The first comparison result is used to determine the initial calibration position, and the subsequent calibration results are used to calibrate the frequency control word bit by bit from high to low. When the frequency error (i.e., the difference between the actual count value and the ideal count value) is less than the preset difference threshold, the frequency locking is completed, the frequency locking loop is disconnected, and the numerically controlled oscillator 10 enters a free oscillation state; when the frequency error is greater than the preset difference threshold, the frequency locking loop continues to be calibrated.

[0085] The control method of the frequency locked loop provided in the embodiment of the present invention has the same technical features as the frequency locked loop provided in the above embodiment, and therefore can also solve the same technical problems and achieve the same technical effects.

[0086] In the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0087] Finally, it should be noted that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A frequency locked loop, characterized in that: The frequency locked loop comprises: a digitally controlled oscillator configured to generate a corresponding target frequency signal based on a target control signal, and to control a loop control switch to perform a corresponding action based on the target frequency signal; A high frequency counter configured to count the digital controlled oscillator to obtain an actual count value; an ideal count value unit, configured to generate an ideal count value within a preset time window; a frequency identification unit, configured to determine whether a difference between the actual count value and the ideal count value satisfies a preset difference threshold; The frequency adjustment control unit is configured to generate the target control signal based on the difference if the judgment result is satisfied, so as to control the digital controlled oscillator to generate the target frequency signal.

2. The frequency locked loop according to claim 1, characterized in that: The frequency identification unit includes a frequency identifier and an error identifier; The frequency discriminator is configured to obtain the actual count value and the ideal count value and calculate a difference between the actual count value and the ideal count value; The error identifier is configured to determine whether the difference calculated by the frequency identifier satisfies the preset difference threshold.

3. The frequency locked loop according to claim 1, characterized in that: The frequency locked loop also includes a reference counting unit; The reference counting unit is configured to generate the preset time window based on a reference clock.

4. The frequency locked loop according to claim 3, characterized in that: The reference counting unit includes a reference clock and a reference counter; The reference clock is configured to input a clock of a set frequency to the reference counter; The reference counter is configured to generate the preset time window based on a clock input of the reference clock.

5. The frequency locked loop according to claim 4, characterized in that: The frequency locked loop also includes a counting threshold unit; The counting threshold unit is configured to generate a counting duration for the numerically controlled oscillator and send the counting duration to the reference counter.

6. The frequency locked loop according to claim 1, characterized in that: The frequency locked loop also includes the loop control switch; The loop control switch is configured to be turned on under the control of an enable control signal and to perform a corresponding action based on the frequency signal sent by the digitally controlled oscillator.

7. The frequency locked loop according to claim 6, characterized in that: The frequency locked loop also includes a finite state machine; The finite state machine is configured to control a current state of the loop control switch.

8. A method for controlling a frequency locked loop, characterized in that: The control method comprises: The high frequency counter counts the numerically controlled oscillator to obtain the actual count value; The ideal count value unit generates an ideal count value within a preset time window; The frequency identification unit receives the actual count value and the ideal count value, and determines whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold; If the judgment result of the frequency identification unit is satisfied, the frequency adjustment control unit generates a target control signal based on the difference; The digital controlled oscillator generates a corresponding target frequency signal based on the target control signal, and controls a loop control switch to perform a corresponding action based on the target frequency signal.

9. The method for controlling a frequency locked loop according to claim 8, characterized in that: The frequency identification unit receives the actual count value and the ideal count value, and determines whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold, including: The frequency identification unit receives the actual count value and the ideal count value, and subtracts the actual count value from the ideal count value and takes an absolute value to obtain a difference between the actual count value and the ideal count value; It is determined whether the obtained difference satisfies a preset difference threshold.

10. The method for controlling a frequency locked loop according to claim 8, characterized in that: The control method further comprises: If the determination result of the frequency identification unit is not satisfied, the actual count value and the ideal count value are received, and the action of determining whether the difference between the actual count value and the ideal count value satisfies a preset difference threshold is continued.

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