Memory chip, logic chip, chip stacking structure and memory

Abstract

The invention provides a memory chip, a logic chip, a chip stacking structure and a memory. The memory chip comprises m channels, and the m channels are sequentially arranged in the first direction and are symmetrical about the axis of the chip; each channel is provided with a channel signal region, each channel signal region is divided into 2 * 2 through hole regions which are distributed in an array, the areas of the m channel signal regions are the same, and the distribution positions of the conductive through hole groups in the m channel signal regions are the same.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory chip, a logic chip, a chip stacking structure and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked using bonding processes (e.g., hybrid bonding, bump bonding, wire bonding) to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affects the quality of signal transmission. Summary of the invention

[0003] The present disclosure provides a memory chip, a logic chip, a chip stacking structure and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory chip, the memory chip comprising m channels, the m channels being arranged in sequence along a first direction, the memory chip having a chip axis extending in a second direction and passing through the center of the memory chip, the m channels being symmetrical about the chip axis; each of the channels comprising a first memory array region, a channel signal region, and a second memory array region distributed in sequence along the second direction, and the center of each of the channel signal regions coincides with the center of the corresponding channel, and m is a positive integer; the first direction is perpendicular to the second direction; each of the channel signal regions has a first axis and a second axis, the first axis extending in the first direction or the second direction, the second axis and the first axis being perpendicular to each other and intersecting at the center of the corresponding channel signal region; each of the channel signal regions is divided into 2×2 through-hole regions distributed in an array, the first through-hole region and the second through-hole region being arranged along the first axis of the corresponding channel signal region. The third through-hole area and the fourth through-hole area are symmetrical along the first axis of the channel signal area to which they belong, and the first through-hole area and the fourth through-hole area are symmetrical along the second axis of the channel signal area to which they belong; each of the through-hole areas includes n conductive through-hole groups, and the n conductive through-hole groups penetrate the substrate of the memory chip in a direction perpendicular to the active surface of the memory chip, where n is a natural number; the areas of the m channel signal areas are the same, and the distribution positions of the conductive through-hole groups in the m channel signal areas are the same; in the same channel signal area, the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong, the n conductive through-hole groups in the third through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong, and the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong.

[0006] In some embodiments, each of the conductive through-hole groups has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group; in the case where each of the conductive through-hole groups includes a first conductive through-hole, a second conductive through-hole, a third conductive through-hole and a fourth conductive through-hole distributed in a 2×2 array, the first conductive through-hole and the second conductive through-hole are symmetrical about the third axis of the conductive through-hole group, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the third axis of the conductive through-hole group, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the fourth axis of the conductive through-hole group; In each of the channel signal regions, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n first conductive vias in the first via region and the n fourth conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong; the n second conductive vias in the first via region and the n first conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong The n fourth conductive vias in the third through-hole area and the n third conductive vias in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive vias in the first through-hole area and the n third conductive vias in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong; the n third conductive vias in the first through-hole area and the n fourth conductive vias in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong; the n first conductive vias in the third through-hole area and the n second conductive vias in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong Axis symmetry; the n third conductive vias in the first via area and the n second conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n third conductive vias in the second via area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive vias in the third via area and the n first conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n first conductive vias in the fourth via area are symmetrical about the second axis of the channel signal area to which they belong.

[0007] In some embodiments, the memory chip further includes (4×m×n) first driving circuits; (4×m×n) first driving circuits are coupled one-to-one with (4×m×n) first conductive vias, and the first driving circuits are coupled with the portion of the first conductive vias located on the active surface; the first driving circuit is used to send the signal transmitted by the correspondingly connected first conductive vias to the internal circuit of the memory chip; or, to send the signal generated by the internal circuit of the memory chip to the correspondingly connected first conductive vias.

[0008] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal region to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal.

[0009] In some embodiments, the conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process; different conductive vias in the same memory chip are electrically isolated.

[0010] In a second aspect, an embodiment of the present disclosure provides a logic chip, the logic chip comprising m channel signal areas, the m channel signal areas are arranged in sequence along a first direction, the logic chip has a chip axis extending along a second direction and passing through the center of the logic chip, and the m channel signal areas are symmetrical about the chip axis; m is a positive integer; each of the channel signal areas has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the channel signal area to which they belong; each of the channel signal areas is divided into 2×2 through-hole areas distributed in an array, the first through-hole area and the second through-hole area are symmetrical along the first axis of the channel signal area to which they belong, the third through-hole area and the fourth through-hole area are symmetrical along the first axis of the channel signal area to which they belong, The hole area is symmetrical along the second axis of the channel signal area to which it belongs; the second direction is perpendicular to the first direction; each of the through-hole areas includes n conductive through-hole groups, and the n conductive through-hole groups penetrate the substrate of the logic chip along a direction perpendicular to the active surface of the logic chip, and n is a natural number; the areas of the m channel signal areas are the same, and the distribution positions of the conductive through-hole groups in the m channel signal areas are the same; in the same channel signal area, the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong, the n conductive through-hole groups in the third through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong, and the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong.

[0011] In some embodiments, each of the conductive through-hole groups has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group; in the case where each of the conductive through-hole groups includes the first conductive through-hole, the second conductive through-hole, the third conductive through-hole and the fourth conductive through-hole distributed in a 2×2 array, the first conductive through-hole and the second conductive through-hole are symmetrical about the third axis of the conductive through-hole group, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the third axis of the conductive through-hole group, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the fourth axis of the conductive through-hole group; in each of the conductive through-hole groups In the channel signal region, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n first conductive vias in the first via region and the n fourth conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong; the n second conductive vias in the first via region and the n first conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong The n fourth conductive through-holes in the third through-hole area and the n third conductive through-holes in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive through-holes in the first through-hole area and the n third conductive through-holes in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong; the n third conductive through-holes in the first through-hole area and the n fourth conductive through-holes in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong; the n first conductive through-holes in the third through-hole area and the n second conductive through-holes in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong Symmetrical; the n third conductive vias in the first via area and the n second conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n third conductive vias in the second via area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive vias in the third via area and the n first conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n first conductive vias in the fourth via area are symmetrical about the second axis of the channel signal area to which they belong.

[0012] In some embodiments, the logic chip also includes (16×m×n) second driving circuits, and the (16×m×n) second driving circuits are coupled one-to-one with the (16×m×n) conductive vias, and the second driving circuits are coupled to the portion of the conductive vias located on the active surface; the second driving circuit is used to send the signal transmitted by the corresponding conductive via to the internal circuit of the logic chip; or, to send the signal generated by the internal circuit of the logic chip to the corresponding conductive via.

[0013] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal; the conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same logic chip are electrically isolated from each other.

[0014] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising the logic chip as described in the second aspect and at least one stacking unit, the logic chip and the at least one stacking unit are stacked in sequence along a third direction, each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, the third direction is perpendicular to an active surface of each of the memory chips, the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all the memory chips as described in the first aspect;

[0015] The logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner;

[0016] The first memory chip and the second memory chip are stacked in a face-to-face manner;

[0017] The second memory chip and the third memory chip are stacked in a back-to-back manner;

[0018] The third memory chip and the fourth memory chip are stacked in a face-to-face manner.

[0019] In some embodiments, the logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; when the logic chip and the first memory chip are stacked back to back, and the first axes of the logic chip and each of the memory chips extend along the first direction, the mi-th channel signal area in the logic chip is aligned with the channel signal area in the i+1-th channel in the first memory chip, the channel signal area in the i+1-th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the mi-th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0020] In some embodiments, the logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; when the logic chip and the first memory chip are stacked back to back and the second axis of the logic chip and each of the memory chips extends along the first direction, the i+1th channel signal area in the logic chip is aligned with the channel signal area in the i+1th channel in the first memory chip, the channel signal area in the mith channel in the second memory chip, the channel signal area in the mith channel in the third memory chip, and the channel signal area in the i+1th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0021] In some embodiments, the channel signal area in each of the channels is divided into 2×2 through-hole areas distributed in an array; only for the multiple channel signal areas aligned along the third direction: the fourth through-hole area belonging to the logic chip, the first through-hole area belonging to the first memory chip, the second through-hole area belonging to the second memory chip, the third through-hole area belonging to the third memory chip, and the fourth through-hole area belonging to the fourth memory chip are aligned along the third direction; the third through-hole area belonging to the logic chip, the second through-hole area belonging to the first memory chip, the first through-hole area belonging to the second memory chip, and the fourth through-hole area belonging to the third memory chip are aligned along the third direction. The fourth through-hole area and the third through-hole area belonging to the fourth storage chip are aligned along a third direction; the second through-hole area belonging to the logic chip, the third through-hole area belonging to the first storage chip, the fourth through-hole area belonging to the second storage chip, the first through-hole area belonging to the third storage chip, and the second through-hole area belonging to the fourth storage chip are aligned along the third direction; the first through-hole area belonging to the logic chip, the fourth through-hole area belonging to the first storage chip, the third through-hole area belonging to the second storage chip, the second through-hole area belonging to the third storage chip, and the first through-hole area belonging to the fourth storage chip are aligned along the third direction.

[0022] In some embodiments, each of the through-hole areas includes n conductive through-hole groups with the same distribution position, each conductive through-hole group has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group to which it belongs; in the case where each of the conductive through-hole groups includes 2×2 first conductive through-holes, second conductive through-holes, third conductive through-holes and fourth conductive through-holes distributed in a 2×2 array, the first conductive through-hole and the second conductive through-hole are symmetrical about the third axis of the conductive through-hole group to which they belong, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the third axis of the conductive through-hole group to which they belong, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the fourth axis of the conductive through-hole group to which they belong; only for the multiple through-hole areas aligned along the third direction: the fourth conductive through-hole belonging to the logic chip, the first conductive through-hole belonging to the first memory chip, the second conductive through-hole belonging to the second memory chip, the third conductive through-hole belonging to the third memory chip, the fourth conductive through-hole belonging to the fourth memory chip The fourth conductive through-hole of the storage chip is aligned along a third direction; the third conductive through-hole belonging to the logic chip, the second conductive through-hole belonging to the first storage chip, the first conductive through-hole belonging to the second storage chip, the fourth conductive through-hole belonging to the third storage chip, and the third conductive through-hole belonging to the fourth storage chip are aligned along the third direction; the second conductive through-hole belonging to the logic chip, the third conductive through-hole belonging to the first storage chip, the fourth conductive through-hole belonging to the second storage chip, the first conductive through-hole belonging to the third storage chip, and the second conductive through-hole belonging to the fourth storage chip are aligned along the third direction; the first conductive through-hole belonging to the logic chip, the fourth conductive through-hole belonging to the first storage chip, the third conductive through-hole belonging to the second storage chip, the second conductive through-hole belonging to the third storage chip, and the first conductive through-hole belonging to the fourth storage chip are aligned along the third direction; wherein, a plurality of conductive through-holes aligned along the third direction are coupled to form a conductive channel.

[0023] In some embodiments, the logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; when the logic chip and the first memory chip are stacked back to back and the first axis of the logic chip and each of the memory chips extends along the first direction, the i+1th channel signal area in the logic chip is aligned with the channel signal area in the i+1th channel in the first memory chip, the channel signal area in the i+1th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the mi-th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0024] In some embodiments, the logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; when the logic chip and the first memory chip are stacked back to back and the second axis of the logic chip and each of the memory chips extends along the first direction, the mi-th channel signal area in the logic chip is aligned with the channel signal area in the i+1-th channel in the first memory chip, the channel signal area in the mi-th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the i+1-th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0025] In some embodiments, only for the multiple channel signal areas aligned along the third direction: the second through-hole area belonging to the logic chip, the first through-hole area belonging to the first memory chip, the second through-hole area belonging to the second memory chip, the third through-hole area belonging to the third memory chip, and the fourth through-hole area belonging to the fourth memory chip are aligned along the third direction; the first through-hole area belonging to the logic chip, the second through-hole area belonging to the first memory chip, the first through-hole area belonging to the second memory chip, the fourth through-hole area belonging to the third memory chip, and the fourth through-hole area belonging to the fourth memory chip are aligned along the third direction. The third through hole area of ​​the logic chip is aligned along the third direction; the fourth through hole area belonging to the logic chip, the third through hole area belonging to the first memory chip, the fourth through hole area belonging to the second memory chip, the first through hole area belonging to the third memory chip, and the second through hole area belonging to the fourth memory chip are aligned along the third direction; the third through hole area belonging to the logic chip, the fourth through hole area belonging to the first memory chip, the third through hole area belonging to the second memory chip, the second through hole area belonging to the third memory chip, and the first through hole area belonging to the fourth memory chip are aligned along the third direction.

[0026] In some embodiments, each of the through-hole areas includes n conductive through-hole groups with the same distribution position, each conductive through-hole group has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group to which it belongs; in the case where each of the conductive through-hole groups includes 2×2 first conductive through-holes, second conductive through-holes, third conductive through-holes and fourth conductive through-holes distributed in a 2×2 array, the first conductive through-hole and the second conductive through-hole are symmetrical about the third axis of the conductive through-hole group to which they belong, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the third axis of the conductive through-hole group to which they belong, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the fourth axis of the conductive through-hole group to which they belong; for the plurality of through-hole areas aligned along the third direction: the second conductive through-hole belonging to the logic chip, the first conductive through-hole belonging to the first memory chip, the second conductive through-hole belonging to the second memory chip, the third conductive through-hole belonging to the third memory chip, the fourth conductive through-hole belonging to the fourth memory chip The fourth conductive through-hole of the storage chip is aligned along the third direction; the first conductive through-hole belonging to the logic chip, the second conductive through-hole belonging to the first storage chip, the first conductive through-hole belonging to the second storage chip, the fourth conductive through-hole belonging to the third storage chip, and the third conductive through-hole belonging to the fourth storage chip are aligned along the third direction; the fourth conductive through-hole belonging to the logic chip, the third conductive through-hole belonging to the first storage chip, the fourth conductive through-hole belonging to the second storage chip, the first conductive through-hole belonging to the third storage chip, and the second conductive through-hole belonging to the fourth storage chip are aligned along the third direction; the third conductive through-hole belonging to the logic chip, the fourth conductive through-hole belonging to the first storage chip, the third conductive through-hole belonging to the second storage chip, the second conductive through-hole belonging to the third storage chip, and the first conductive through-hole belonging to the fourth storage chip are aligned along the third direction; wherein, a plurality of conductive through-holes aligned along the third direction are coupled to form a conductive channel.

[0027] In some embodiments, for two chips connected face to face, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected face to back, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a conductive bump bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected face to back, the conductive vias aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected face to back, the conductive vias aligned along the third direction in the two chips are electrically connected through a conductive bump bonding process.

[0028] In a fourth aspect, an embodiment of the present disclosure provides a memory, which includes the chip stacking structure as described in the third aspect.

[0029] The embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure and a memory, which not only reduce the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection configuration of a through hole, and also reduces parasitic resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a chip;

[0031] Figure 2A A schematic diagram of signal transmission of a chip stacking structure;

[0032] Figure 2B A schematic diagram of signal transmission of a chip stacking structure;

[0033] Figure 3 A schematic diagram of the structure of a memory chip provided by an embodiment of the present disclosure;

[0034] Figure 4 A schematic diagram of a local structure of a memory chip provided in an embodiment of the present disclosure Figure 1 ;

[0035] Figure 5 A second schematic diagram of a partial structure of a memory chip provided in an embodiment of the present disclosure;

[0036] Figure 6 A schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure;

[0037] Fig. 7A A schematic diagram of a local structure of a logic chip provided in an embodiment of the present disclosure Figure 1 ;

[0038] Figure 7B A second schematic diagram of a partial structure of a logic chip provided in an embodiment of the present disclosure;

[0039] Figure 8 A schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure;

[0040] Fig. 9A A specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0041] Fig. 9B A second specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure;

[0042] Fig. 10A A specific schematic diagram of another chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0043] Fig. 10B A second specific schematic diagram of another chip stacking structure provided by an embodiment of the present disclosure;

[0044] Fig.11A A specific schematic diagram of another chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0045] Fig. 11B A second specific schematic diagram of another chip stacking structure provided in an embodiment of the present disclosure;

[0046] Fig. 12A A specific schematic diagram of another chip stacking structure provided in the embodiment of the present disclosure Figure 1 ;

[0047] Fig. 12B A second specific schematic diagram of another chip stacking structure provided by an embodiment of the present disclosure;

[0048] Fig.13 A schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0049] Fig.14 A second schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure;

[0050] Fig.15 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0052] Dynamic Random Access Memory (DRAM);

[0053] Synchronous Dynamic Random Access Memory (SDRAM);

[0054] Double Data Rate SDRAM (DDR);

[0055] Low Power DDR (LPDDR).

[0056] Before introducing the embodiments of the present disclosure, three directions that may be used to describe the three-dimensional structure of the plane involved in the following embodiments are defined first. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0057] See also Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, a direction intersecting (e.g., perpendicular) the top surface and the bottom surface of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two directions perpendicular to each other are defined, namely, a first direction and a second direction, and the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0058] See also Figure 1 The semiconductor chip includes a substrate, one side of which is used to make devices (such as transistors, capacitors, etc.) and forms an active surface (the side of the substrate opposite to the active surface is a non-active surface, i.e. Figure 1 There are multiple metal layers between the substrate and the top surface, such as M1, M2, M3... Figure 1 Also shown are two types of conductive vias (eg, through silicon vias), both used to achieve signal connections between different stacked chips.

[0059] like Figure 1 As shown, for the type 1 conductive via, it penetrates the bottom surface and the top surface along the third direction, and the conductive via is connected to the internal circuit of the chip through the metal layer.

[0060] like Figure 1 As shown, for the conductive via of type 2, it only penetrates the substrate along the third direction (through the active surface and the bottom surface), and needs to cooperate with the contact structure that penetrates the top surface along the third direction to realize signal transmission; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1 The contact structure in is connected to M4, M4 is connected to M1 via M3 and M2 in sequence, and M1 is connected to the conductive through hole; or, Figure 1 The conductive vias in the chip are connected to the internal circuits via M1-M4 ( Figure 1 The output signal processed by the chip internal circuit is then output to the corresponding contact structure through the metal layers M1-M4. Figure 1 The contact structure in can also be connected to the internal circuit of the chip via M1-M4 ( Figure 1 The output signal processed by the chip internal circuit is then output to the corresponding conductive via via M1-M4. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0061] Meanwhile, the types of conductive vias are not limited to the above two types, which are only examples. In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0062] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0063] In one embodiment, a memory chip and a logic chip are provided, each of which includes a plurality of conductive vias penetrating the chip along a third direction, the conductive vias being used to achieve signal transmission between different chips, and all the conductive vias can be located at any position. In particular, every four conductive vias can be functionally regarded as a conductive via group, but the positions of the four conductive vias are not limited.

[0064] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device, and the conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Figure 2A , which shows a schematic diagram of signal transmission of a chip stacking structure. Figure 2A As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2A Only four conductive through holes D0 to D3 are shown for each memory chip, and these four conductive through holes D0 to D3 belong to the same conductive through hole group. At this time, the conductive through holes D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive through holes D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... and the remaining conductive through holes are similar.

[0065] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits ( Figure 2A Only one of the driving circuits is shown in a dotted box, and the rest of the driving circuits are not framed), and each conductive through hole is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 2A Each conductive via group corresponds to one data selector, that is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective driving circuits. In other words, the data selector can select which conductive via transmits the signal to be output to the inside of the memory chip or which conductive via the signal output by the memory chip is output to.

[0066] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management, and the signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive through hole D0 in the logic chip, conductive through hole D0 in memory chip 0 - conductive through hole D0 in memory chip 1 - conductive through hole D0 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D0 in memory chip 4 - conductive through hole D0 in memory chip 5 - conductive through hole D0 in memory chip 6 - conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 via the aforementioned electrical path; the output process of the signal can be understood similarly.

[0067] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1... That is, each memory chip only needs to obtain signals from one of the conductive vias in a conductive via group. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using Figure 2A In the chip stacking structure shown, each conductive through hole corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel, and the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases the power consumption, and also restricts the number of chip stacks in the three-dimensional device.

[0068] In another embodiment, see Figure 2B , which shows another schematic diagram of signal transmission of a chip stacking structure. In particular, Figure 2B Only some conductive vias are marked (D0 to D3), and the others are omitted. Figure 2B For example, the conductive vias aligned along the third direction have the same identifier. Figure 2BAs shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through hole in each memory chip is rotationally connected to another conductive through hole at a different position in another memory chip, and a spiral ascending connection is realized as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through hole D0 in the logic chip - conductive through hole D1 in memory chip 0 - conductive through hole D2 in memory chip 1 - conductive through hole D3 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D1 in memory chip 4 - conductive through hole D2 in memory chip 5 - conductive through hole D3 in memory chip 6 - conductive through hole D0 in memory chip 7", and the other signals are similar.

[0069] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of conductive via D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of conductive via D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of conductive via D0 in memory chip 1, memory chip 3 can obtain signal Signal_CH5 through the input end of conductive via D0 in memory chip 2... For each memory chip, only one conductive via in each conductive via group is required to connect to the drive circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2A The conductive through-hole direct connection configuration, Figure 2B The process of rotating the conductive through hole is more complicated. Specifically, Figure 2B A horizontal interconnection structure ( Figure 2B Only one of them is marked with a five-pointed star), the signal interconnection structure can be a metal interconnection line, a conductive through hole, etc. In order to realize the rotation connection of the conductive through hole, the input signal signal_CH0 must first be transmitted upward from the conductive through hole D0 of the logic chip to the interconnection structure below the conductive through hole D0 of the memory chip 0 (not connected to the conductive through hole D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive through hole D0 of the memory chip 0 to the conductive through hole D1 of the memory chip 0. That is: Figure 2B The structure shown in the figure also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0070] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are actively facing upward, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0071] In summary, on the one hand, Figure 2A The chip stacking structure requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 2A and Figure 2B There are certain problems with the stacking structure, and it cannot be directly applied to the face-to-face stacking structure. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as the active side up and the active side down. This method has high process complexity and uncontrollable cost; another way is to make an extra set of conductive vias and connect the two sets of conductive vias to the same drive circuit in the memory chip, but this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity, but also increase power consumption.

[0072] In another embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the structure of a memory chip 10 provided by an embodiment of the present disclosure. Figure 3 As shown, the memory chip 10 includes m channels ( Figure 3 Taking m=4 as an example for illustration), the m channels are arranged in sequence along the first direction, the memory chip 10 has a chip axis YY' extending in the second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis YY'; each channel includes a first memory array area, a channel signal area, and a second memory array area distributed in sequence along the second direction, and the center of each channel signal area coincides with the center of the channel to which it belongs.

[0073] It should be noted that during the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made in the reference channel (for example, the first channel) of the storage chip 10, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and other channels can be identified in combination with the active surface orientation of the chip.

[0074] Figure 3Take m=4 as an example, and m=4 is also used as an example for explanation below, but m can be any positive integer. Specifically, if m is an even number, then m / 2 channels are located on one side of the global signal area along the first direction, and the remaining m / 2 channels are located on the other side of the global signal area along the first direction; if m is an odd number, then the (m+1) / 2th channel needs to be divided into two parts and located on both sides of the global signal area along the first direction, while the other (m-1) / 2 channels are located on one side of the global signal area along the first direction, and the remaining (m-1) / 2 channels are located on the other side of the global signal area along the first direction.

[0075] Figure 3 It can be considered as a cross-sectional view of the active surface of the memory chip. Figure 3 As shown, the center of the active surface of the memory chip and its adjacent area are defined as the global signal area, and the first channel, the second channel, the global signal area, the third channel and the fourth channel are sequentially distributed along the first direction. The signal transmitted by the global signal area is used by the m channels of the memory chip; while the signal transmitted by each channel signal area is only used by the channel to which it belongs.

[0076] See also Figure 4 , which specifically shows a schematic diagram of a channel signal area 11 of a first channel, a channel signal area 12 of a second channel, a channel signal area 13 of a third channel, and a channel signal area 14 of a fourth channel. Figure 4 The global signal region is omitted.

[0077] like Figure 4 As shown, each channel signal region has a first axis AA' and a second axis BB'. The first axis AA' extends along the first direction or the second direction. The second axis BB' is perpendicular to the first axis AA' and intersects at the center of the corresponding channel signal region. Figure 4 The first axis AA' extending along the first direction is taken as an example for illustration, and other situations are understood adaptively.

[0078] Each channel signal area is divided into 2×2 through-hole areas distributed in an array, the first through-hole area 21 and the second through-hole area 22 are symmetrical along the first axis AA' of the channel signal area to which they belong, the third through-hole area 23 and the fourth through-hole area 24 are symmetrical along the first axis AA' of the channel signal area to which they belong, and the first through-hole area 21 and the fourth through-hole area 24 are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0079] Each through-hole region includes n conductive through-hole groups ( Figure 4 Only a portion of the conductive through-hole groups are shown), and n conductive through-hole groups penetrate the substrate of the memory chip 10 in a direction perpendicular to the active surface of the memory chip 10, where n is a natural number.

[0080] At the same time, the areas of the m channel signal regions are the same, and the distribution positions of the conductive through-hole groups in the m channel signal regions are the same. In this way, when manufacturing the memory chip 10, the layouts of the channel signal regions of different channels are completely consistent, and the same mask plate can be used to reduce manufacturing costs.

[0081] Specifically, in the same channel signal area, the n conductive through-hole groups of the first through-hole area 21 and the n conductive through-hole groups of the second through-hole area 22 are symmetrical about the first axis AA' of the channel signal area to which they belong; the n conductive through-hole groups of the third through-hole area 23 and the n conductive through-hole groups of the fourth through-hole area 24 are symmetrical about the first axis AA' of the channel signal area to which they belong, and the n conductive through-hole groups of the first through-hole area 21 and the n conductive through-hole groups of the fourth through-hole area 24 are symmetrical about the second axis BB' of the channel signal area to which they belong.

[0082] like Figure 4 As shown, the distance between the center of a conductive through-hole group in the first through-hole area 21 and the first axis AA' is recorded as V A The distance between the center of the conductive via group symmetrical to the second via region 22 and the first axis AA' is recorded as V C The distance between the center of the conductive via group symmetrical to the third via region 23 and the first axis AA' is recorded as V D The distance between the center of the conductive via group symmetrical to the fourth via region 24 and the first axis AA' is recorded as V B , then V A =V C =V D =V B Similarly, the distance between the center of a conductive through-hole group in the first through-hole area 21 and the edge of the channel signal area extending along the second direction is recorded as H A , the distance between the center of a conductive via group in the second via region 22 and the edge of the channel signal region extending along the second direction is recorded as H C The distance between the center of a conductive via group in the third via region 23 and the edge of the channel signal region extending along the second direction is recorded as H D The distance between the center of a conductive via group in the fourth via region 24 and the edge of the channel signal region extending along the second direction is recorded as H B , then H A =H C =H D =H B .

[0083] It should be noted that the number and specific positions of the conductive through holes in the conductive through hole group are very flexible to choose. For example, each conductive through hole group can have only 1 conductive through hole, or 1×2 through holes, or 2×2 through holes, or 2×3 through holes. It is only necessary to ensure that the conductive through hole groups in different through hole areas follow the above symmetrical relationship.

[0084] The following is a specific description using the example that each conductive via group includes 2×2 conductive vias ( D0 , D1 , D2 , D3 ) distributed in an array. Please adapt to other situations.

[0085] See also Figure 5 Each conductive through-hole group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive through-hole group to which they belong; the first conductive through-hole D0 and the second conductive through-hole D1 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, the third conductive through-hole D2 and the fourth conductive through-hole D3 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, and the first conductive through-hole D0 and the fourth conductive through-hole D3 are symmetrical about the fourth axis DD' of the conductive through-hole group to which they belong.

[0086] In this way, a conductive through-hole group in the first through-hole area 21, a corresponding conductive through-hole group in the second through-hole area 22, a corresponding conductive through-hole group in the third through-hole area 23 and a corresponding conductive through-hole group in the fourth through-hole area 24 are formed as a whole which is symmetrical about the first axis AA' and about the second axis BB'; for each conductive through-hole group, the first through-hole, the second through-hole, the third through-hole and the fourth through-hole are symmetrical about the third axis CC' and about the fourth axis DD', so that when the chip stacking structure is subsequently formed, a point-to-point direct conductive path can be formed to reduce parasitic capacitance and parasitic resistance. Please refer to the subsequent description for details.

[0087] In some embodiments, see Figure 4 , in each channel signal area, there is the following symmetric relationship:

[0088] (1) The n first conductive vias D0 in the first via region 21 and the n second conductive vias D1 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n third conductive vias D2 in the third via region 23 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n first conductive vias D0 in the first via region 21 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong;

[0089] (2) The n second conductive vias D1 in the first via region 21 and the n first conductive vias D0 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n fourth conductive vias D3 in the third via region 23 and the n third conductive vias D2 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n second conductive vias D1 in the first via region 21 and the n third conductive vias D2 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong;

[0090] (3) The n third conductive vias D2 in the first via region 21 and the n fourth conductive vias D3 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n first conductive vias D0 in the third via region 23 and the n second conductive vias D1 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n third conductive vias D2 in the first via region 21 and the n second conductive vias D1 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong;

[0091] (4) The n fourth conductive vias D3 in the first via region 21 and the n third conductive vias D2 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n second conductive vias D1 in the third via region 23 and the n first conductive vias D0 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n fourth conductive vias D3 in the first via region 21 and the n first conductive vias D0 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong.

[0092] In some embodiments, see Figure 4 or Figure 5 The memory chip 10 further includes (4×m×n) first drive circuits 30; the (4×m×n) first drive circuits 30 are coupled one-to-one with the (4×m×n) first conductive vias D0; specifically, the first drive circuits 30 are coupled with the portion of the first conductive vias D0 located on the active surface; the first drive circuits 30 are used to send the signal transmitted by the correspondingly connected first conductive vias D0 to the internal circuit of the memory chip 10; or, send the signal generated by the internal circuit of the memory chip 10 to the correspondingly connected first conductive vias D0.

[0093] Thus, for each conductive via group, only the first conductive via D0 is connected to the internal circuit of the memory chip through the first driving circuit 30, and there is no need to set a data selector for via selection, which can reduce the number of components and thus reduce parasitic capacitance.

[0094] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal region to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal.

[0095] For example, for a chip stacking structure of multiple memory chips and logic chips, there are multiple chip selection signals CS_0, CS_1, CS_2, etc., which are respectively used to indicate whether the memory array areas of different channels are selected; at this time, Figure 4 The first conductive through hole D0 located in the first through hole area 21 in the channel signal area 11, the first conductive through hole D0 located at the same position of the first through hole area 21 in the channel signal area 12, the first conductive through hole D0 located at the same position of the first through hole area 21 in the channel signal area 13, and the first conductive through hole D0 located at the same position of the first through hole area 21 in the channel signal area 14 all transmit the chip select signal CS, but the values ​​of the chip select signal CS transmitted by the first conductive through holes D0 in different channel signal areas may be different, for example, the first conductive through hole D0 in the first through hole area 21 in the channel signal area 11 is used to transmit CS_0 (corresponding to the first channel in the first memory chip), the first conductive through hole D0 in the first through hole area 21 in the channel signal area 12 is used to transmit CS_1 (corresponding to the first channel of the second memory chip), and the first conductive through hole D0 in the first through hole area 21 in the channel signal area 13 is used to transmit CS_2 (corresponding to the fourth channel of the third memory chip)...

[0096] In addition, for the same channel signal area, the four conductive through holes symmetrically along the first axis and along the second axis transmit the same type of signals, but the specific signal values ​​may be different.

[0097] In some embodiments, the conductive via can at least be embodied as a through silicon via (TSV), which is specifically a vertical interconnect structure penetrating a silicon wafer / memory chip, for example Figure 1 Type 1 in the diagram; of course, conductive vias can also be Figure 1 Type 2 in the embodiment, which realizes signal transmission together with the contact structure. In other embodiments, other electrical connection structures can also be selected as the conductive through hole.

[0098] The conductive via is prepared by any one or more of the processes of via-first, via-middle, via-last, and back side via-last; different conductive vias in the same memory chip 10 are electrically isolated.

[0099] It should be noted that the through-hole process first refers to a through-hole process method for manufacturing a through-hole structure before manufacturing a device, such as a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET or MOS tube for short). The intermediate through-hole process is a through-hole structure formed during the manufacturing process of the process flow, and is often a through-hole process manufactured after the device is formed and before the stack is manufactured. The through-hole process after is a manufacturing process in which a through-hole is formed from the front side of the wafer after the back end of line (BEOL) process is completed. The back through-hole process is a manufacturing process in which a through-hole structure is formed from the back side of the wafer after the BEOL process is completed. In other words, the through-hole process first can refer to making a through-hole first and then making a circuit; the intermediate through-hole process can refer to making a circuit and part of the metal layer first, then making a through-hole, and finally making the remaining through-holes; the through-hole process after and the back through-hole process can refer to making a circuit and a metal layer first, and finally making a through-hole.

[0100] Thus, the embodiment of the present disclosure provides a memory chip 10, which includes a plurality of channels, the plurality of channels are symmetrical about the chip axis, and the conductive through holes of each channel are symmetrical about the first axis and about the second axis, which can be directly applied to a face-to-face stacking structure without two sets of masks or two sets of through holes; in addition, only one conductive through hole in each conductive through hole group is connected to the driving circuit, and there is no need to set a data selector for through hole selection, which can reduce the number of components, thereby reducing the number of components compared to the conventional memory chip 10. Figure 2A The memory chip reduces parasitic capacitance, which not only saves circuit area, but also reduces chip manufacturing costs; the subsequent memory chip 10 forms a point-to-point direct conductive path when forming a stacked structure, which can also be compared to Figure 2B The memory chip reduces the parasitic resistance (see the subsequent explanation for the specific reasons).

[0101] In yet another embodiment of the present disclosure, see Figure 6 , which shows a schematic diagram of the structure of a logic chip 40 provided in an embodiment of the present disclosure. Figure 6 As shown, the logic chip 40 includes m channel signal areas ( Figure 6 Taking m=4 as an example, the m channel signal regions are arranged in sequence along the first direction, the logic chip 40 has a chip axis YY' extending along the second direction and passing through the center of the logic chip 40, and the m channel signal regions are symmetrical about the chip axis YY'. Here, the area of ​​the channel signal region in the logic chip 40 is the same as the area of ​​the channel signal region in the memory chip.

[0102] Similar, such as Figure 6As shown, the center of the active surface of the logic chip 40 and its adjacent area are also defined as the global signal area. At this time, the first channel signal area 11, the second channel signal area 12, the global signal area, the third channel signal area 13, and the fourth channel signal area 14 are distributed in sequence along the first direction, but the logic chip does not have a storage array area, that is, the two sides of the channel signal area of ​​the logic chip 40 are not storage cell arrays, but some logic control circuits of the stacked memory. The signals transmitted by the global signal area are used in common by the m channels of the storage chip; and the signals transmitted by each channel signal area are only used by the channel to which it belongs. In particular, the area of ​​the active surface of the logic chip 40 may be the same as the area of ​​the active surface of the storage chip 10, or the area of ​​the logic chip 40 may be larger than the area of ​​the storage chip 10.

[0103] like Fig. 7A As shown, each channel signal region has a first axis AA' and a second axis BB', and the first axis AA' extends along the first direction or the second direction ( Fig. 7A Taking the first axis AA' along the first direction as an example, the second axis BB' and the first axis AA' are perpendicular to each other and intersect at the center of the channel signal area to which they belong; each channel signal area is divided into 2×2 through-hole areas distributed in an array, the first through-hole area 21 and the second through-hole area 22 are symmetrical along the first axis AA' of the channel signal area to which they belong, the third through-hole area 23 and the fourth through-hole area 24 are symmetrical along the first axis AA' of the channel signal area to which they belong, and the first through-hole area 21 and the fourth through-hole area 24 are symmetrical along the second axis BB' of the channel signal area to which they belong; the second direction is perpendicular to the first direction.

[0104] Each through-hole area includes n conductive through-hole groups, and the n conductive through-hole groups penetrate the substrate of the logic chip in a direction perpendicular to the active surface of the logic chip 40, where n is a natural number; the areas of the m channel signal areas are the same, and the distribution positions of the conductive through-hole groups in the m channel signal areas are the same; in the same channel signal area, the n conductive through-hole groups of the first through-hole area 21 and the n conductive through-hole groups of the second through-hole area 22 are symmetrical about the first axis AA' of the channel signal area to which they belong, the n conductive through-hole groups of the third through-hole area 23 and the n conductive through-hole groups of the fourth through-hole area 24 are symmetrical about the first axis AA' of the channel signal area to which they belong, and the n conductive through-hole groups of the first through-hole area 21 and the n conductive through-hole groups of the fourth through-hole area 24 are symmetrical about the second axis BB' of the channel signal area to which they belong.

[0105] Similarly, for the logic chip 40, the number and positions of the conductive vias included in the conductive via group can be flexibly determined. The following is an example in which each conductive via group includes 2×2 conductive vias (D0, D1, D2 and D3) distributed in an array.

[0106] like Figure 7B As shown, each conductive through-hole group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive through-hole group to which they belong; the first conductive through-hole D0 and the second conductive through-hole D1 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, the third conductive through-hole D2 and the fourth conductive through-hole D3 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, and the first conductive through-hole D0 and the fourth conductive through-hole D3 are symmetrical about the fourth axis DD' of the conductive through-hole group to which they belong.

[0107] Similarly, for the logic chip 40, the areas of the m channel signal regions are the same, and the distribution positions of the conductive via groups in the m channel signal regions are the same. In this way, when manufacturing the logic chip 40, the layouts of the channel signal regions of different channels are completely consistent, and the same mask plate can be used to reduce manufacturing costs.

[0108] In some embodiments, see Fig. 7A , in each channel signal area, there is the following symmetric relationship:

[0109] (1) The n first conductive vias D0 in the first via region 21 and the n second conductive vias D1 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n third conductive vias D2 in the third via region 23 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n first conductive vias D0 in the first via region 21 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong;

[0110] (2) The n second conductive vias D1 in the first via region 21 and the n first conductive vias D0 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n fourth conductive vias D3 in the third via region 23 and the n third conductive vias D2 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n second conductive vias D1 in the first via region 21 and the n third conductive vias D2 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong;

[0111] (3) The n third conductive vias D2 in the first via region 21 and the n fourth conductive vias D3 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n first conductive vias D0 in the third via region 23 and the n second conductive vias D1 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n third conductive vias D2 in the first via region 21 and the n second conductive vias D1 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong;

[0112] (4) The n fourth conductive vias D3 in the first via region 21 and the n third conductive vias D2 in the second via region 22 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n second conductive vias D1 in the third via region 23 and the n first conductive vias D0 in the fourth via region 24 are symmetrical about the first axis AA' of the channel signal region to which they belong; the n fourth conductive vias D3 in the first via region 21 and the n first conductive vias D0 in the fourth via region 24 are symmetrical about the second axis BB' of the channel signal region to which they belong.

[0113] In some embodiments, see Fig. 7A or Figure 7B The logic chip 40 also includes (16×m×n) second driving circuits 50, and the (16×m×n) second driving circuits 50 are coupled to the (16×m×n) conductive vias one by one, and the second driving circuits 50 are coupled to the conductive vias located on the active surface; the second driving circuits 50 are used to send the signals transmitted by the corresponding conductive vias to the internal circuit of the logic chip 40; or, send the signals generated by the internal circuit of the logic chip 40 to the corresponding conductive vias.

[0114] It should be noted that, for the logic chip 40, each conductive via in its conductive via group is connected to the internal circuit of the logic chip 40, so as to transmit corresponding signals to different memory array parts (different channels) in the chip stacking structure.

[0115] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal. The conductive via is prepared by any one or more of the processes of via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same logic chip are electrically isolated from each other.

[0116] Thus, the embodiment of the present disclosure provides a logic chip 40, which includes a plurality of channels, and the conductive through holes of each channel have a special symmetry, which can be directly applied to a face-to-face stacking structure without two sets of masks or two sets of through holes; the chip stacking structure formed by the memory chip 10 and the logic chip 40 is compared with Figure 2A The memory chip reduces parasitic capacitance, which not only saves circuit area but also reduces chip manufacturing costs; in addition, when forming a chip stacking structure, a point-to-point direct conductive path can be formed, which can also be compared with Figure 2B The memory chip reduces the parasitic resistance (see the subsequent explanation for the specific reasons).

[0117] In another embodiment of the present disclosure, see Figure 8 , which shows a schematic structural diagram of a chip stacking structure 70 provided by an embodiment of the present disclosure. Figure 8 As shown, the chip stacking structure 70 includes the aforementioned logic chip 40 and at least one stacking unit, the logic chip 40 and the at least one stacking unit are stacked in sequence along a third direction, each stacking unit includes a first memory chip 10A, a second memory chip 10B, a third memory chip 10C and a fourth memory chip 10D stacked in sequence along the third direction, the third direction is perpendicular to the active surface of each memory chip, the first memory chip 10A, the second memory chip 10B, the third memory chip 10C and the fourth memory chip 10D are all the aforementioned memory chips 10; the logic chip 40 and the first memory chip 10A are stacked face to back or back to back; the first memory chip 10A and the second memory chip 10B are stacked face to face; the second memory chip 10B and the third memory chip 10C are stacked back to back; the third memory chip 10C and the fourth memory chip 10D are stacked face to face.

[0118] In the embodiments of the present disclosure, face-to-face stacking means that the top surfaces of the two chips are approximately aligned along the third direction, and the center points, the first axis and the second axis of the top surfaces of the two chips are all aligned along the third direction; back-to-back stacking means that the bottom surfaces of the two chips are approximately aligned along the third direction; and back-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. When logic chip or memory chip is not specified, "chip" can refer to both logic chip and memory chip.

[0119] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding columns); for two chips connected back to back or for two chips connected face to back, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a conductive bump (UBump, also known as a micro-bump).

[0120] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected face to back, the bonding surfaces of both (positions where the middle conductive vias are aligned along the third direction) are connected through a hybrid bonding structure. That is, the bonding surfaces between the two chips connected face to face (positions where the middle conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure, and the bonding surfaces between the two chips connected back to back (positions where the middle conductive vias are aligned along the third direction) and the bonding surfaces between the two chips connected face to back (positions where the middle conductive vias are aligned along the third direction) are also electrically connected through a hybrid bonding structure.

[0121] In another possibility, for two chips connected face to face or for back to back connection or for two chips connected face to back, the bonding surfaces of both (positions where the conductive vias are aligned along the third direction) are connected through conductive bumps. That is, the bonding surfaces between the two chips connected face to face (positions where the conductive vias are aligned along the third direction) are connected through conductive bumps, and the bonding surfaces between the two chips connected back to back (positions where the conductive vias are aligned along the third direction) and the bonding surfaces between the two chips connected face to back (positions where the conductive vias are aligned along the third direction) are also connected through conductive bumps.

[0122] Here, the above chip may refer to a logic chip 40 or a memory chip 10 .

[0123] It should be noted that compared with the conductive bump process, the face-to-face connection using the hybrid bonding process can make the adjacent chips fit more closely, with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, two chips connected back to back can also be connected through a hybrid bonding structure, but its connection performance is weaker than that of the case of connection through the conductive bump process.

[0124] It should be noted that the logic chip 40 or the memory chip can be divided into a high-order transmission area and a low-order transmission area. Figures 9A to 12BThe arrows in the figure are all located in the high-order transmission area of ​​the chip. In particular, the high-order transmission area and the low-order transmission area in the embodiment of the present disclosure are only two areas to distinguish the memory chip, and have no additional restrictions, and have nothing to do with the high-order data and low-order data commonly mentioned in data transmission.

[0125] It is also necessary to note that see Fig. 9A The logic chip 40 includes m channel signal areas arranged along a first direction, each memory chip has m channels arranged along the first direction (m=4 is illustrated as an example), and each channel includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction.

[0126] When the logic chip 40 and the first memory chip 10A are stacked back to back, and the first axis AA' of the logic chip 40 and each memory chip extends along the first direction (i.e., the first axis AA' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the high-order transmission area of ​​the logic chip 40, the high-order transmission area of ​​the first memory chip 10A, the low-order transmission area of ​​the second memory chip 10B, the low-order transmission area of ​​the third memory chip 10C, and the high-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction; the low-order transmission area of ​​the logic chip 40, the low-order transmission area of ​​the first memory chip 10A, the high-order transmission area of ​​the second memory chip 10B, the high-order transmission area of ​​the third memory chip 10C, and the low-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction.

[0127] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the mi-th channel signal area in the logic chip 40 is aligned along the third direction with the channel signal area in the i+1-th channel in the first memory chip 10A, the channel signal area in the i+1-th channel in the second memory chip 10B, the channel signal area in the mi-th channel in the third memory chip 10C, and the channel signal area in the mi-th channel in the fourth memory chip 10D; wherein i is a natural number less than m.

[0128] Fig. 9A Take m=4 as an example, in this case:

[0129] (1) the fourth channel signal region 14 in the logic chip 40 and the channel signal region 11 in the first channel in the first memory chip 10A are aligned along the third direction, the channel signal region 11 in the first channel in the second memory chip 10B is aligned along the third direction, the channel signal region 14 in the fourth channel in the third memory chip 10C is aligned along the third direction, and the channel signal region 14 in the fourth channel in the fourth memory chip 10D is aligned along the third direction;

[0130] (2) the third channel signal region 13 in the logic chip 40 and the channel signal region 12 in the second channel in the first memory chip 10A are aligned along the third direction, the channel signal region 12 in the second channel in the second memory chip 10B is aligned along the third direction, the channel signal region 13 in the third channel in the third memory chip 10C is aligned along the third direction, and the channel signal region 13 in the third channel in the fourth memory chip 10D is aligned along the third direction;

[0131] (3) the second channel signal region 12 in the logic chip 40 and the channel signal region 13 in the third channel in the first memory chip 10A are aligned along the third direction, the channel signal region 13 in the third channel in the second memory chip 10B is aligned along the third direction, the channel signal region 12 in the second channel in the third memory chip 10C is aligned along the third direction, and the channel signal region 12 in the second channel in the fourth memory chip 10D is aligned along the third direction;

[0132] (4) The first channel signal region 11 in the logic chip 40 and the channel signal region 14 in the fourth channel in the first memory chip 10A are aligned along the third direction, the channel signal region 14 in the fourth channel in the second memory chip 10B is aligned along the third direction, the channel signal region 11 in the first channel in the third memory chip 10C is aligned along the third direction, and the channel signal region 11 in the first channel in the fourth memory chip 10D is aligned along the third direction.

[0133] In other embodiments, see Fig. 10A (Using m=4 as an example for illustration), when the logic chip 40 and the first memory chip 10A are stacked back to back, and the second axis BB' of the logic chip 40 and each memory chip extends along the first direction (that is, the second axis BB' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the low-order transmission area of ​​the logic chip 40, the high-order transmission area of ​​the first memory chip 10A, the high-order transmission area of ​​the second memory chip 10B, the low-order transmission area of ​​the third memory chip 10C, and the low-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction; the high-order transmission area of ​​the logic chip 40, the low-order transmission area of ​​the first memory chip 10A, the low-order transmission area of ​​the second memory chip 10B, the high-order transmission area of ​​the third memory chip 10C, and the high-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction.

[0134] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the i+1th channel signal area in the logic chip 40 is aligned along the third direction with the channel signal area in the i+1th channel in the first memory chip 10A, the channel signal area in the mith channel in the second memory chip 10B, the channel signal area in the mith channel in the third memory chip 10C, and the channel signal area in the i+1th channel in the fourth memory chip 10D; wherein i is a natural number less than m.

[0135] Fig. 10A Take m=4 as an example, in this case:

[0136] (1) the first channel signal region 11 in the logic chip 40, the channel signal region 11 in the first channel in the first memory chip 10A, the channel signal region 14 in the fourth channel in the second memory chip 10B, the channel signal region 14 in the fourth channel in the third memory chip 10C, and the channel signal region 11 in the first channel in the fourth memory chip 10D are aligned along a third direction;

[0137] (2) the second channel signal region 12 in the logic chip 40, the channel signal region 12 in the second channel in the first memory chip 10A, the channel signal region 13 in the third channel in the second memory chip 10B, and the channel signal region 13 in the third channel in the third memory chip 10C are aligned along the third direction, and the channel signal region 12 in the second channel in the fourth memory chip 10D is aligned along the third direction;

[0138] (3) the third channel signal region 13 in the logic chip 40, the channel signal region 13 in the third channel in the first memory chip 10A, the channel signal region 12 in the second channel in the second memory chip 10B, the channel signal region 12 in the second channel in the third memory chip 10C, and the channel signal region 13 in the third channel in the fourth memory chip 10D are aligned along a third direction;

[0139] (4) The fourth channel signal region 14 in the logic chip 40, the channel signal region 14 in the fourth channel in the first memory chip 10A, the channel signal region 11 in the first channel in the second memory chip 10B, the channel signal region 11 in the first channel in the third memory chip 10C, and the channel signal region 14 in the fourth channel in the fourth memory chip 10D are aligned along the third direction.

[0140] Simply put, for Figures 9A to 10B , the logic chip 40 and the fourth memory chip 10D are placed in the same manner.

[0141] It should also be noted that whether Fig. 9B or Fig. 10B , the channel signal area in each channel of the memory chip and logic chip is divided into 2×2 through-hole areas distributed in an array. Fig. 9A or Fig. 9B , for multiple channel signal areas aligned along the third direction, it has the following characteristics:

[0142] (1) the fourth through hole area 24 of the logic chip 40, the first through hole area 21 of the first memory chip 10A, the second through hole area 22 of the second memory chip 10B, the third through hole area 23 of the third memory chip 10C, and the fourth through hole area 24 of the fourth memory chip 10D are aligned along the third direction;

[0143] (2) the third through hole area 23 belonging to the logic chip 40, the second through hole area 22 belonging to the first memory chip 10A, the first through hole area 21 belonging to the second memory chip 10B, the fourth through hole area 24 belonging to the third memory chip 10C, and the third through hole area 23 belonging to the fourth memory chip 10D are aligned along the third direction;

[0144] (3) the second through hole area 22 of the logic chip 40, the third through hole area 23 of the first memory chip 10A, the fourth through hole area 24 of the second memory chip 10B, the first through hole area 21 of the third memory chip 10C, and the second through hole area 22 of the fourth memory chip 10D are aligned along the third direction;

[0145] (4) The first through-hole area 21 belonging to the logic chip 40, the fourth through-hole area 24 belonging to the first memory chip 10A, the third through-hole area 23 belonging to the second memory chip 10B, the second through-hole area 22 belonging to the third memory chip 10C, and the first through-hole area 21 belonging to the fourth memory chip 10D are aligned along the third direction.

[0146] In some embodiments, when each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, see Fig. 9B or Fig. 10B Each through-hole area of ​​the memory chip and the logic chip 40 includes n conductive through-hole groups with the same distribution position, each conductive through-hole group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive through-hole group to which they belong; the first conductive through-hole D0 and the second conductive through-hole D1 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, the third conductive through-hole D2 and the fourth conductive through-hole D3 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, and the first conductive through-hole D0 and the fourth conductive through-hole D3 are symmetrical about the fourth axis DD' of the conductive through-hole group to which they belong.

[0147] For multiple via fields aligned along the third direction:

[0148] (1) the fourth conductive via D3 of the logic chip 40, the first conductive via D0 of the first memory chip 10A, the second conductive via D1 of the second memory chip 10B, the third conductive via D2 of the third memory chip 10C, and the fourth conductive via D3 of the fourth memory chip 10D are aligned along the third direction;

[0149] (2) the third conductive via D2 of the logic chip 40, the second conductive via D1 of the first memory chip 10A, the first conductive via D0 of the second memory chip 10B, the fourth conductive via D3 of the third memory chip 10C, and the third conductive via D2 of the fourth memory chip 10D are aligned along the third direction;

[0150] (3) the second conductive via D1 of the logic chip 40, the third conductive via D2 of the first memory chip 10A, the fourth conductive via D3 of the second memory chip 10B, the first conductive via D0 of the third memory chip 10C, and the second conductive via D1 of the fourth memory chip 10D are aligned along the third direction;

[0151] (4) The first conductive through hole D0 of the logic chip 40, the fourth conductive through hole D3 of the first memory chip 10A, the third conductive through hole D2 of the second memory chip 10B, the second conductive through hole D1 of the third memory chip 10C, and the first conductive through hole D0 of the fourth memory chip 10D are aligned along a third direction; wherein, the plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

[0152] In some other embodiments, see Fig.11A (Using m=4 as an example for illustration), when the logic chip 40 and the first memory chip 10A are stacked back to back, and the first axis AA' of the logic chip 40 and each memory chip extends along the first direction (that is, the first axis AA' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the low-order transmission area of ​​the logic chip 40, the high-order transmission area of ​​the first memory chip 10A, the low-order transmission area of ​​the second memory chip 10B, the low-order transmission area of ​​the third memory chip 10C, and the high-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction; the high-order transmission area of ​​the logic chip 40, the low-order transmission area of ​​the first memory chip 10A, the high-order transmission area of ​​the second memory chip 10B, the high-order transmission area of ​​the third memory chip 10C, and the low-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction.

[0153] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the i+1th channel signal area in the logic chip 40 is aligned along the third direction with the channel signal area in the i+1th channel in the first memory chip 10A, the channel signal area in the i+1th channel in the second memory chip 10B, the channel signal area in the mi-th channel in the third memory chip 10C, and the channel signal area in the mi-th channel in the fourth memory chip 10D; wherein i is a natural number less than m.

[0154] Fig.11A Take m=4 as an example. At this time:

[0155] (1) the first channel signal region 11 in the logic chip 40, the channel signal region 11 in the first channel in the first memory chip 10A, the channel signal region 11 in the first channel in the second memory chip 10B, the channel signal region 14 in the fourth channel in the third memory chip 10C, and the channel signal region 14 in the fourth channel in the fourth memory chip 10D are aligned along a third direction;

[0156] (2) the second channel signal region 12 in the logic chip 40, the channel signal region 12 in the second channel in the first memory chip 10A, the channel signal region 12 in the second channel in the second memory chip 10B, the channel signal region 13 in the third channel in the third memory chip 10C, and the channel signal region 13 in the third channel in the fourth memory chip 10D are aligned along a third direction;

[0157] (3) the third channel signal region 13 in the logic chip 40, the channel signal region 13 in the third channel in the first memory chip 10A, the channel signal region 13 in the third channel in the second memory chip 10B, the channel signal region 12 in the second channel in the third memory chip 10C, and the channel signal region 12 in the second channel in the fourth memory chip 10D are aligned along a third direction;

[0158] (4) The fourth channel signal region 14 in the logic chip 40, the channel signal region 14 in the fourth channel in the first memory chip 10A, the channel signal region 14 in the fourth channel in the second memory chip 10B, the channel signal region 11 in the first channel in the third memory chip 10C, and the channel signal region 11 in the first channel in the fourth memory chip 10D are aligned along the third direction.

[0159] In some other embodiments, see Fig. 12A(Taking m=4 as an example for illustration), when m=4 and the logic chip 40 and the first memory chip 10A are stacked back to back, and the second axis BB' of the logic chip 40 and each memory chip extends along the first direction (i.e., the second axis BB' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the high-order transmission area of ​​the logic chip 40, the high-order transmission area of ​​the first memory chip 10A, the high-order transmission area of ​​the second memory chip 10B, the low-order transmission area of ​​the third memory chip 10C, and the low-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction; the low-order transmission area of ​​the logic chip 40, the low-order transmission area of ​​the first memory chip 10A, the low-order transmission area of ​​the second memory chip 10B, the high-order transmission area of ​​the third memory chip 10C, and the high-order transmission area of ​​the fourth memory chip 10D are aligned along the third direction.

[0160] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the mi-th channel signal area in the logic chip 40 is aligned along the third direction with the channel signal area in the i+1-th channel in the first memory chip 10A, the channel signal area in the mi-th channel in the second memory chip 10B, the channel signal area in the mi-th channel in the third memory chip 10C, and the channel signal area in the i+1-th channel in the fourth memory chip 10D; wherein i is a natural number less than m.

[0161] (1) the fourth channel signal region 14 in the logic chip 40, the channel signal region 11 in the first channel in the first memory chip 10A, the channel signal region 14 in the fourth channel in the second memory chip 10B, the channel signal region 14 in the fourth channel in the third memory chip 10C, and the channel signal region 11 in the first channel in the fourth memory chip 10D are aligned along a third direction;

[0162] (2) the third channel signal region 13 in the logic chip 40, the channel signal region 12 in the second channel in the first memory chip 10A, the channel signal region 13 in the third channel in the second memory chip 10B, the channel signal region 13 in the third channel in the third memory chip 10C, and the channel signal region 12 in the second channel in the fourth memory chip 10D are aligned along a third direction;

[0163] (3) the second channel signal region 12 in the logic chip 40, the channel signal region 13 in the third channel in the first memory chip 10A, the channel signal region 12 in the second channel in the second memory chip 10B, the channel signal region 12 in the second channel in the third memory chip 10C, and the channel signal region 13 in the third channel in the fourth memory chip 10D are aligned along the third direction;

[0164] (4) The first channel signal region 11 in the logic chip 40, the channel signal region 14 in the fourth channel in the first memory chip 10A, the channel signal region 11 in the first channel in the second memory chip 10B, the channel signal region 11 in the first channel in the third memory chip 10C, and the channel signal region 14 in the fourth channel in the fourth memory chip 10D are aligned along a third direction.

[0165] Simply put, for Figures 11A to 12B , the logic chip 40 and the second memory chip 10B are placed in the same manner.

[0166] In some embodiments, see Fig. 11B and Fig. 12B , the channel signal area in each channel of the memory chip and the logic chip 40 is divided into 2×2 through-hole areas distributed in an array. Fig. 11B and Fig. 12B , for multiple channel signal regions aligned along the third direction:

[0167] (1) the second through hole area 22 of the logic chip 40, the first through hole area 21 of the first memory chip 10A, the second through hole area 22 of the second memory chip 10B, the third through hole area 23 of the third memory chip 10C, and the fourth through hole area 24 of the fourth memory chip 10D are aligned along the third direction;

[0168] (2) the first through-hole area 21 of the logic chip 40, the second through-hole area 22 of the first memory chip 10A, the first through-hole area 21 of the second memory chip 10B, the fourth through-hole area 24 of the third memory chip 10C, and the third through-hole area 23 of the fourth memory chip 10D are aligned along the third direction;

[0169] (3) the fourth through hole area 24 belonging to the logic chip 40, the third through hole area 23 belonging to the first memory chip 10A, the fourth through hole area 24 belonging to the second memory chip 10B, the first through hole area 21 belonging to the third memory chip 10C, and the second through hole area 22 belonging to the fourth memory chip 10D are aligned along the third direction;

[0170] (4) The third through hole area 23 belonging to the logic chip 40, the fourth through hole area 24 belonging to the first memory chip 10A, the third through hole area 23 belonging to the second memory chip 10B, the second through hole area 22 belonging to the third memory chip 10C, and the first through hole area 21 belonging to the fourth memory chip 10D are aligned along the third direction.

[0171] See also Fig. 11B or Fig. 12B, in the case where each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, see Fig. 11B or Fig. 12B Each through-hole area of ​​the memory chip and the logic chip 40 includes n conductive through-hole groups with the same distribution position, each conductive through-hole group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive through-hole group to which they belong; the first conductive through-hole D0 and the second conductive through-hole D1 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, the third conductive through-hole D2 and the fourth conductive through-hole D3 are symmetrical about the third axis CC' of the conductive through-hole group to which they belong, and the first conductive through-hole D0 and the fourth conductive through-hole D3 are symmetrical about the fourth axis DD' of the conductive through-hole group to which they belong.

[0172] For multiple via fields aligned along the third direction:

[0173] (1) the second conductive via D1 of the logic chip 40, the first conductive via D0 of the first memory chip 10A, the second conductive via D1 of the second memory chip 10B, the third conductive via D2 of the third memory chip 10C, and the fourth conductive via D3 of the fourth memory chip 10D are aligned along a third direction;

[0174] (2) the first conductive via D0 of the logic chip 40, the second conductive via D1 of the first memory chip 10A, the first conductive via D0 of the second memory chip 10B, the fourth conductive via D3 of the third memory chip 10C, and the third conductive via D2 of the fourth memory chip 10D are aligned along the third direction;

[0175] (3) the fourth conductive via D3 of the logic chip 40, the third conductive via D2 of the first memory chip 10A, the fourth conductive via D3 of the second memory chip 10B, the first conductive via D0 of the third memory chip 10C, and the second conductive via D1 of the fourth memory chip 10D are aligned along the third direction;

[0176] (4) the third conductive via D2 of the logic chip 40, the fourth conductive via D3 of the first memory chip 10A, the third conductive via D2 of the second memory chip 10B, the second conductive via D1 of the third memory chip 10C, and the first conductive via D0 of the fourth memory chip 10D are aligned along the third direction;

[0177] A plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

[0178] As can be seen from the above, for each embodiment shown in FIG. 9 to FIG. 12, the plurality of conductive through holes aligned in the third direction are respectively the first conductive through hole D0, the second conductive through hole D1, the third conductive through hole D2 and the fourth conductive through hole D3, so that when using similar Figure 2A The direct connection configuration in Figure 2B The rotating connection in the chip stacking structure not only has low parasitic resistance and low parasitic capacitance, but also enables face-to-face stacking.

[0179] Only Fig. 9A and Fig. 9B The stacking method shown is used as an example to illustrate the principle of signal transmission. Please adapt to other situations.

[0180] like Fig. 9A and Fig. 9B As shown, taking m=4 as an example, each memory chip includes 4 channels, each stacking unit includes 16 channels, and there are corresponding 16 channel signal areas. Fig.13 , which shows a schematic diagram of signal transmission of each chip in a chip stacking structure, in particular, Fig.13 The top surface of each chip is shown. Fig.13 As shown, the fourth channel signal area to the first channel signal area in the logic chip 40 are called S0, S1, S2 and S3 in sequence. The four channel signal areas corresponding to the fourth channel to the first channel in the first memory chip 10A are called CH0, CH1, CH2 and CH3; the four channel signal areas corresponding to the fourth channel to the first channel in the second memory chip 10B are called CH4, CH5, CH6 and CH7; the four channel signal areas corresponding to the first channel to the fourth channel in the third memory chip 10C are called CH8, CH9, CH10 and CH11; the four channel signal areas corresponding to the first channel to the fourth channel in the fourth memory chip 10D are called CH12, CH13, CH14 and CH15. These 16 channels have their own control signals, Fig.13 It shows the transmission of four types of control signals: chip select signal (CS_0 ~ CS_15), virtual channel signal (PC_0 ~ PC_15), write enable signal (WE_0 ~ WE_15), memory address signal (BA_0 ~ BA_15), of course, there are many control signals, such as command address signal CA, memory group signal BG, read enable signal, etc. The following only takes CS_0 ~ CS_15 as an example for specific description.

[0181] See also Fig.14 and Fig.15In each channel of the logic chip 40, four conductive through holes that are symmetrical about the first axis and symmetrical about the second axis are used to transmit chip select signals. Taking channel S0 in the logic chip 40 as an example, the fourth through hole D3 (in the fourth through hole area) is used to transmit CS_0, the third through hole D2 (in the third through hole area) is used to transmit CS_4, the second through hole D1 (in the second through hole area) is used to transmit CS_8, and the first through hole D0 (in the first through hole area) is used to transmit CS_12.

[0182] For CS_0, it is transmitted upward in sequence through the fourth through hole D3 of the logic chip 40 (the fourth through hole area of ​​channel S0), the first through hole D0 of the first memory chip 10A (the first through hole area 21 of channel CH0), the second through hole D1 of the second memory chip 10B (the second through hole area 22 of channel CH4), the third through hole D2 of the third memory chip 10C (the third through hole area 23 of channel CH8), the fourth through hole D3 of the fourth memory chip 10D (the fourth through hole area 24 of channel CH12), etc.; on this transmission route, CS_0 enters the channel CH0 of the first memory chip 10A in each stacking unit through the first through hole D0, thereby exerting a control effect on the corresponding part; however, since the second through hole D1, the third through hole D2 and the fourth through hole D3 are not provided with a driving circuit, and are thus electrically isolated from the internal circuits of the chips to which they belong, CS_0 will not enter the second memory chip 10B, the third memory chip 10C, and the fourth memory chip 10D;

[0183] Similarly, for CS_4, it is transmitted upward in sequence through the third through hole D2 of the logic chip 40 (the third through hole area of ​​channel S0), the second through hole D1 of the first memory chip 10A (the second through hole area of ​​channel CH0), the first through hole D0 of the second memory chip 10B (the first through hole area of ​​channel CH4), the fourth through hole D3 of the third memory chip 10C (the fourth through hole area of ​​channel CH8), the third through hole D2 of the fourth memory chip 10D (the third through hole area of ​​channel CH12), etc.; on this transmission route, CS_4 enters the channel CH4 of the second memory chip 10B in each stacking unit through the corresponding first through hole D0, thereby exerting a control effect on the corresponding part; however, since the second through hole D1, the third through hole D2 and the fourth through hole D3 are not provided with a driving circuit, and are thus electrically isolated from the internal circuits of the chips to which they belong, CS_0 does not enter the first memory chip 10A, the third memory chip 10C, and the fourth memory chip 10D;

[0184] ...Please refer to the rest for understanding.

[0185] Thus, for the chip stacking structure 40, from a physical point of view, the conductive vias therein are still in a direct connection configuration, but from the absolute position of the conductive vias on the active surface, the conductive vias therein can be regarded as a functionally rotated configuration, that is, a similar rotation configuration is achieved through the physical direct connection configuration. Figure 2B The signal transmission effect (i.e. the rotation transmission effect of through hole D0-through hole D1-through hole D2-through hole D3...). In simple terms, Figure 2B The chip stacking structure 40 in the embodiment requires a physical spiral structure, in which there must be a lateral interconnection structure. Fig.14 The chip stacking structure 40 is physically a direct connection structure, without the need for a lateral interconnection structure, so the parasitic resistance is greatly reduced, and the transmission speed and transmission performance are greatly improved.

[0186] In yet another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of the structure of a memory 80 provided by an embodiment of the present disclosure. Fig.15 As shown, the memory 80 at least includes the aforementioned chip stacking structure 70. The memory 80 may be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0187] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory chip, characterized in that: The memory chip comprises m channels, the m channels are arranged in sequence along a first direction, the memory chip has a chip axis extending in a second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis; each of the channels comprises a first storage array region, a channel signal region, and a second storage array region distributed in sequence along the second direction, and the center of each channel signal region coincides with the center of the corresponding channel, and m is a positive integer; the first direction is perpendicular to the second direction; Each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the channel signal region to which it belongs; each of the channel signal regions is divided into 2×2 through-hole regions distributed in an array, the first through-hole region and the second through-hole region are symmetrical along the first axis of the channel signal region to which they belong, the third through-hole region and the fourth through-hole region are symmetrical along the first axis of the channel signal region to which they belong, and the first through-hole region and the fourth through-hole region are symmetrical along the second axis of the channel signal region to which they belong; Each of the through-hole regions includes n conductive through-hole groups, and the n conductive through-hole groups penetrate the substrate of the memory chip in a direction perpendicular to the active surface of the memory chip, where n is a natural number; the areas of the m channel signal regions are the same, and the distribution positions of the conductive through-hole groups in the m channel signal regions are the same; In the same channel signal area, the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong, the n conductive through-hole groups in the third through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong, and the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong.

2. The memory chip according to claim 1, characterized in that: Each of the conductive via groups has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group; In the case where each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical about a third axis of the conductive via group to which they belong, the third conductive via and the fourth conductive via are symmetrical about a third axis of the conductive via group to which they belong, and the first conductive via and the fourth conductive via are symmetrical about a fourth axis of the conductive via group to which they belong; In each of the channel signal regions, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n first conductive vias in the first via region and the n fourth conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong; The n second conductive vias in the first via region and the n first conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n fourth conductive vias in the third via region and the n third conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n second conductive vias in the first via region and the n third conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong; The n third conductive vias in the first via region and the n fourth conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n first conductive vias in the third via region and the n second conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n third conductive vias in the first via region and the n second conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; The n fourth conductive vias in the first via area and the n third conductive vias in the second via area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive vias in the third via area and the n first conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n first conductive vias in the fourth via area are symmetrical about the second axis of the channel signal area to which they belong.

3. The memory chip according to claim 2, characterized in that: The memory chip further includes (4×m×n) first driving circuits; (4×m×n) first driving circuits are coupled to (4×m×n) first conductive vias in a one-to-one correspondence, and the first driving circuits are coupled to portions of the first conductive vias located on the active surface; The first driving circuit is used to send a signal transmitted by the correspondingly connected first conductive via to an internal circuit of the memory chip; or to send a signal generated by the internal circuit of the memory chip to the correspondingly connected first conductive via.

4. The memory chip according to any one of claims 1 to 3, characterized in that: The coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal.

5. The memory chip according to claim 4, characterized in that: The conductive vias are prepared by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last; and different conductive vias in the same memory chip are electrically isolated.

6. A logic chip, characterized in that: The logic chip comprises m channel signal regions, the m channel signal regions are arranged in sequence along a first direction, the logic chip has a chip axis extending along a second direction and passing through the center of the logic chip, and the m channel signal regions are symmetrical about the chip axis; m is a positive integer; Each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the channel signal region to which it belongs; each of the channel signal regions is divided into 2×2 through-hole regions distributed in an array, the first through-hole region and the second through-hole region are symmetrical along the first axis of the channel signal region to which they belong, the third through-hole region and the fourth through-hole region are symmetrical along the first axis of the channel signal region to which they belong, and the first through-hole region and the fourth through-hole region are symmetrical along the second axis of the channel signal region to which they belong; the second direction is perpendicular to the first direction; Each of the through-hole regions includes n conductive through-hole groups, and the n conductive through-hole groups penetrate the substrate of the logic chip in a direction perpendicular to the active surface of the logic chip, where n is a natural number; the areas of the m channel signal regions are the same, and the distribution positions of the conductive through-hole groups in the m channel signal regions are the same; In the same channel signal area, the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the second through-hole area are symmetrical about the first axis of the channel signal area to which they belong, the n conductive through-hole groups in the third through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the first axis of the channel signal area to which they belong, and the n conductive through-hole groups in the first through-hole area and the n conductive through-hole groups in the fourth through-hole area are symmetrical about the second axis of the channel signal area to which they belong.

7. The logic chip according to claim 6, characterized in that: Each of the conductive via groups has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group; In the case where each of the conductive via groups includes the first conductive via, the second conductive via, the third conductive via and the fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical about the third axis of the conductive via group, the third conductive via and the fourth conductive via are symmetrical about the third axis of the conductive via group, and the first conductive via and the fourth conductive via are symmetrical about the fourth axis of the conductive via group; in each of the channel signal regions, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical about the first axis of the channel signal region; the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region; the n first conductive vias in the first via region and the n fourth conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region; The n second conductive vias in the first via region and the n first conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n fourth conductive vias in the third via region and the n third conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n second conductive vias in the first via region and the n third conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong; The n third conductive vias in the first via region and the n fourth conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong; the n first conductive vias in the third via region and the n second conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; the n third conductive vias in the first via region and the n second conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong; The n fourth conductive vias in the first via area and the n third conductive vias in the second via area are symmetrical about the first axis of the channel signal area to which they belong; the n second conductive vias in the third via area and the n first conductive vias in the fourth via area are symmetrical about the first axis of the channel signal area to which they belong; the n fourth conductive vias in the first via area and the n first conductive vias in the fourth via area are symmetrical about the second axis of the channel signal area to which they belong.

8. The logic chip according to claim 7, characterized in that: The logic chip further includes (16×m×n) second driving circuits, the (16×m×n) second driving circuits are coupled to the (16×m×n) conductive vias in a one-to-one correspondence, and the second driving circuits are coupled to portions of the conductive vias located on the active surface; The second driving circuit is used to send the signal transmitted by the corresponding conductive through hole to the internal circuit of the logic chip; or send the signal generated by the internal circuit of the logic chip to the corresponding conductive through hole.

9. The logic chip according to any one of claims 6 to 8, characterized in that: Determine the coordinate position of each conductive via based on the center of the via signal area to which it belongs, and the four conductive vias with the same coordinate position transmit the same type of signal; The conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same logic chip are electrically isolated from each other.

10. A chip stacking structure, characterized in that: The chip stacking structure comprises the logic chip as claimed in claims 6 to 9 and at least one stacking unit, wherein the logic chip and at least one stacking unit are sequentially stacked along a third direction, each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip sequentially stacked along the third direction, the third direction is perpendicular to the active surface of each of the memory chips, and the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as claimed in any one of claims 1 to 5; The logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner; The first memory chip and the second memory chip are stacked in a face-to-face manner; The second memory chip and the third memory chip are stacked in a back-to-back manner; The third memory chip and the fourth memory chip are stacked in a face-to-face manner.

11. The chip stacking structure according to claim 10, characterized in that: The logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; In the case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the first axes of the logic chip and each of the memory chips extend along the first direction, The mi-th channel signal area in the logic chip is aligned along a third direction with the channel signal area in the i+1-th channel in the first memory chip, the channel signal area in the i+1-th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the mi-th channel in the fourth memory chip; wherein i is a natural number less than m.

12. The chip stacking structure according to claim 10, characterized in that: The logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; In a case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips extends along the first direction, The i+1th channel signal area in the logic chip is aligned along a third direction with the channel signal area in the i+1th channel in the first memory chip, the channel signal area in the mith channel in the second memory chip, the channel signal area in the mith channel in the third memory chip, and the channel signal area in the i+1th channel in the fourth memory chip; wherein i is a natural number less than m.

13. The chip stacking structure according to claim 11 or 12, characterized in that: The channel signal area in each of the channels is divided into 2×2 through-hole areas distributed in an array; Only for the plurality of channel signal regions aligned along the third direction: The fourth through-hole area belonging to the logic chip, the first through-hole area belonging to the first memory chip, the second through-hole area belonging to the second memory chip, the third through-hole area belonging to the third memory chip, and the fourth through-hole area belonging to the fourth memory chip are aligned along a third direction; The third through-hole area belonging to the logic chip, the second through-hole area belonging to the first memory chip, the first through-hole area belonging to the second memory chip, the fourth through-hole area belonging to the third memory chip, and the third through-hole area belonging to the fourth memory chip are aligned along a third direction; The second through-hole area belonging to the logic chip, the third through-hole area belonging to the first memory chip, the fourth through-hole area belonging to the second memory chip, the first through-hole area belonging to the third memory chip, and the second through-hole area belonging to the fourth memory chip are aligned along a third direction; The first through-hole area belonging to the logic chip, the fourth through-hole area belonging to the first memory chip, the third through-hole area belonging to the second memory chip, the second through-hole area belonging to the third memory chip, and the first through-hole area belonging to the fourth memory chip are aligned along a third direction.

14. The chip stacking structure according to claim 13, characterized in that: Each of the through-hole areas includes n conductive through-hole groups with the same distribution position, each conductive through-hole group has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group; in the case where each of the conductive through-hole groups includes 2×2 first conductive through-holes, second conductive through-holes, third conductive through-holes and fourth conductive through-holes distributed in a 2×2 array, the first conductive through-hole and the second conductive through-hole are symmetrical about the third axis of the conductive through-hole group, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the third axis of the conductive through-hole group, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the fourth axis of the conductive through-hole group; Only for the plurality of through-hole regions aligned along the third direction: The fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along a third direction; The third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along a third direction; The second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along a third direction; The first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along a third direction; A plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

15. The chip stacking structure according to claim 10, characterized in that: The logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; In a case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the first axis of the logic chip and each memory chip extends along a first direction, The i+1th channel signal area in the logic chip is aligned along a third direction with the channel signal area in the i+1th channel in the first memory chip, the channel signal area in the i+1th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the mi-th channel in the fourth memory chip; wherein i is a natural number less than m.

16. The chip stacking structure according to claim 15, characterized in that: The logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along a second direction; In a case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips extends along the first direction, The mi-th channel signal area in the logic chip is aligned along a third direction with the channel signal area in the i+1-th channel in the first memory chip, the channel signal area in the mi-th channel in the second memory chip, the channel signal area in the mi-th channel in the third memory chip, and the channel signal area in the i+1-th channel in the fourth memory chip; wherein i is a natural number less than m.

17. The chip stacking structure according to claim 15 or 16, characterized in that: Only for the plurality of channel signal regions aligned along the third direction: The second through-hole area belonging to the logic chip, the first through-hole area belonging to the first memory chip, the second through-hole area belonging to the second memory chip, the third through-hole area belonging to the third memory chip, and the fourth through-hole area belonging to the fourth memory chip are aligned along a third direction; The first through-hole area belonging to the logic chip, the second through-hole area belonging to the first memory chip, the first through-hole area belonging to the second memory chip, the fourth through-hole area belonging to the third memory chip, and the third through-hole area belonging to the fourth memory chip are aligned along a third direction; The fourth through-hole area belonging to the logic chip, the third through-hole area belonging to the first memory chip, the fourth through-hole area belonging to the second memory chip, the first through-hole area belonging to the third memory chip, and the second through-hole area belonging to the fourth memory chip are aligned along a third direction; The third through-hole area belonging to the logic chip, the fourth through-hole area belonging to the first memory chip, the third through-hole area belonging to the second memory chip, the second through-hole area belonging to the third memory chip, and the first through-hole area belonging to the fourth memory chip are aligned along a third direction.

18. The chip stacking structure according to claim 17, characterized in that: Each of the through-hole areas includes n conductive through-hole groups with the same distribution positions, each conductive through-hole group has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive through-hole group; In the case where each of the conductive via groups includes 2×2 first conductive vias, second conductive vias, third conductive vias, and fourth conductive vias distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical about the third axis of the conductive via group to which they belong, the third conductive via and the fourth conductive via are symmetrical about the third axis of the conductive via group to which they belong, and the first conductive via and the fourth conductive via are symmetrical about the fourth axis of the conductive via group to which they belong; For the plurality of through-hole regions aligned along the third direction: The second conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along a third direction; The first conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along a third direction; The fourth conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along a third direction; The third conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along a third direction; A plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

19. The chip stacking structure according to any one of claims 10 to 18, characterized in that: For two chips connected face to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or for two chips connected face to back, the positions where the conductive vias are aligned along the third direction are electrically connected by a conductive bump bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected face to back, the conductive through holes aligned along the third direction in both chips are electrically connected by a hybrid bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected face to back, the conductive through holes aligned along the third direction are electrically connected by a conductive bump bonding process.

20. A memory, characterized in that: Comprising a chip stacking structure as described in any one of claims 10-19.

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