ASIC chip for high-performance AOIP network audio stream transmission

Abstract

The invention discloses an ASIC chip for high-performance AOIP network audio stream transmission, and the interior of the chip comprises a function simulation circuit subsystem, a sensor controller, a clock, and a reset control module. The high-speed peripheral interface subsystem is arranged on the first bus, the hardware acceleration subsystem is arranged on the second bus, the low-speed peripheral interface subsystem is arranged on the third bus, the second bus is connected with the first bus and the third bus, and the function simulation circuit subsystem is connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or 100M bit medium independent interfaces and a real-time transport protocol RTP transceiving engine; the two gigabit or 100M bit medium independent interfaces are compatible with the simplified medium independent interface, one of the two gigabit or 100M bit medium independent interfaces is used as a main network interface, and the other one is used as a standby network interface. The reliability problem of AOIP network audio stream transmission is solved.

Description

Technical Field

[0001] The present application belongs to the technical field of chip architecture design, and in particular, relates to an ASIC chip for high-performance AOIP network audio stream transmission. Background Art

[0002] With the rapid development of technologies such as cloud computing, the Internet of Things, big data, artificial intelligence, and mobile Internet, the professional audio industry has ushered in important development opportunities for digitalization, networking, and intelligence. Currently, professional audio equipment and systems are in an important development stage of transformation and upgrading from analog systems and digital systems to networking. High-performance AOIP network audio streaming technology solves the problem of analog audio and digital audio networking, simplifying the complexity of professional audio system architecture and equipment connection.

[0003] However, the high-performance AOIP network audio stream transmission chips currently used in the professional audio industry are all SoC chips. First of all, these chips are obviously inferior to the implementation methods of hardware circuits in terms of timeliness, reliability, stability and security. Secondly, these chips are all based on ARM architecture single-core processing and have single functions. They have serious defects in information security protection and comprehensive processing capabilities and cannot meet the needs of the current rapid development of the digital economy. Summary of the invention

[0004] The embodiment of the present application provides an ASIC chip for high-performance AOIP network audio stream transmission, which is used to at least solve the problem in the related art that the chip has a single function and has serious defects in information security and comprehensive processing capabilities.

[0005] The embodiment of the present application provides an ASIC chip for high-performance AOIP network audio stream transmission, the chip internally includes: a functional analog circuit subsystem, a sensor controller, a clock and reset control module, and a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, the second bus is respectively connected to the first bus and the third bus, and the functional analog circuit subsystem is connected to the third bus through the sensor controller;

[0006] Wherein, the hardware acceleration subsystem includes multiple processor cores, two Gigabit or 100Mbit media independent interfaces and a real-time transport protocol RTP transceiver engine;

[0007] Multiple processor cores are implemented with 32-bit or higher instruction sets;

[0008] The two Gigabit or 100 Mbit media independent interfaces are both compatible with the simplified media independent interface. One of the two Gigabit or 100 Mbit media independent interfaces serves as a primary network interface, and the other serves as a backup network interface.

[0009] The RTP transceiver engine is used to encapsulate and send the network RTP data packets of the digital audio stream, and to parse and restore the network audio stream RTP data packets.

[0010] The ASIC chip for high-performance AOIP network audio stream transmission in the embodiment of the present application is a high-performance AOIP network audio stream transmission chip built on a core with an instruction set of 32 bits or above, which has strong autonomous controllability and avoids the unfavorable factors of the industrial chain and supply chain being restricted; the designed dedicated chip (ASIC) architecture has a great advantage in processing speed compared to the SoC chip, and is the first dedicated chip design for high-performance AOIP network audio stream transmission; a multi-core processing architecture is adopted to realize digital audio processing on the basis of realizing high-performance AOIP network audio stream transmission, and can provide safe, reliable and high-quality audio signals; two gigabit or 100-megabit medium independent interfaces are used on the dedicated chip to transmit high-performance AOIP network audio streams, and it is compatible with a simplified media independent interface, which can be connected to a gigabit or 100-megabit external physical layer chip, and supports primary and standby network redundancy, which can realize seamless switching, and well solves the reliability problem of AOIP network audio stream transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 It is a schematic diagram of the internal structure of an ASIC chip for high-performance AOIP network audio stream transmission provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0014] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0015] AoIP (Audio over IP) refers to the technology of transmitting high-fidelity digital audio signals in real time in the form of IP (Internet Protocol) streams on ordinary Ethernet networks. It can be applied to many professional audio fields including live sound reinforcement. The high fidelity of AoIP means sampling rates above 44.1kHz, linear quantization above 16bit (usually 48kHz sampling, 24bit quantization), and low latency (hundreds of microseconds to milliseconds), without any lossy or lossless compression processing.

[0016] With the increasing development of artificial intelligence algorithms and application technologies, and the gradual maturity of the artificial intelligence dedicated chip ASIC industry environment, fully customized artificial intelligence ASIC has gradually demonstrated its own advantages. ASIC chip is an integrated circuit (ASIC, Application Specific Integrated Circuit) chip technology used for special applications. In the integrated circuit industry, it is considered to be an integrated circuit designed for a special purpose.

[0017] With the rapid development of technologies such as cloud computing, the Internet of Things, big data, artificial intelligence, and mobile Internet, the professional audio industry has ushered in important development opportunities for digitalization, networking, and intelligence. Currently, professional audio equipment and systems are in an important development stage of transformation and upgrading from analog systems and digital systems to networking. High-performance AOIP network audio stream (sampling rate not less than 44.1kHz, quantization accuracy not less than 16 bits, delay less than 10ms, linear PCM encoding) transmission technology solves the problem of analog audio and digital audio networking, simplifies the complexity of professional audio system architecture and equipment connection, and can realize intelligent monitoring, control, management, and maintenance of the system at the remote end, which can not only improve the work efficiency of user operation and maintenance personnel, but also enhance the user experience.

[0018] However, the high-performance AOIP network audio stream transmission chips currently used in the professional audio industry are all SoC chips, and the RTP audio stream transceiver engine, network clock synchronization, digital media clock management, digital audio processing, peripheral interface and system control management functions are implemented through software on general SoC chips. Therefore, this type of chip is obviously inferior to the hardware circuit implementation method in terms of timeliness, reliability, stability and security. Secondly, this type of chip is based on ARM architecture single-core processing, with a single function and no digital audio processing and encryption and decryption functions. There are serious defects in information security protection and comprehensive processing capabilities, and it cannot meet the needs of the current rapid development of the digital economy.

[0019] In order to solve the problems of the related art, an embodiment of the present application provides an ASIC chip for high-performance AOIP network audio stream transmission.

[0020] The following is a detailed description of the ASIC chip for high-performance AOIP network audio stream transmission provided by the embodiment of the present application through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0021] refer to Figure 1 , is a schematic diagram of the internal structure of an ASIC chip for high-performance AOIP network audio stream transmission according to an embodiment of the present application. Figure 1 As shown in the figure, the ASIC chip for high-performance AOIP network audio streaming transmission includes: high-speed peripheral interface subsystem, hardware acceleration subsystem, low-speed peripheral interface subsystem, functional analog circuit subsystem, sensor controller (SSC), clock and reset control module (Clk / Reset). Among them, based on the clock and reset control module, the digital audio signals entering and leaving each node in the network are accurately synchronized.

[0022] Specifically, the high-speed peripheral interface subsystem is set on the first bus, the hardware acceleration subsystem is set on the second bus, the low-speed peripheral interface subsystem is set on the third bus, and the second bus is connected to the first bus and the third bus respectively.

[0023] Optional, such as Figure 1 As shown, the first bus is an AHB high-speed bus (Advanced High_performance Bus), the second bus is an AXI bus (Advanced eXtensible Interface), and the third bus is an APB 32bit 100MHz bus (Advanced Peripheral Bus).

[0024] Among them, AHB high-speed bus is a bus interface. This chip uses a bus width of more than 32 bits, which is mainly used for communication between the chip processor core, DMA and external MCU and DSP. The AHB bus consists of a master module, a slave module and an infrastructure. The transmission is sent by the master module, and the slave module is responsible for responding. The infrastructure consists of an arbitrator, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a virtual slave module, and a virtual master module.

[0025] The AXI bus is an on-chip bus for high performance, high bandwidth, and low latency. This chip uses a bus width of more than 128 bits. The protocol can achieve high-frequency operations without the use of complex bridges. Its address control and data stages are separated, supporting data transmission with unaligned addresses. In burst-based transmission, only the first address is required, and the separate read and write data channels have a total of five independent channels, supporting significant transmission access and out-of-order access, and it is easy to add pipeline stages to obtain high-frequency timing.

[0026] The APB 32-bit bus is mainly used for connecting low-bandwidth peripherals. Its bus architecture does not support multiple master modules like AHB. The only master module in APB is the APB bridge. Its features include: two clock cycle transmission, no waiting cycle and response signal, simple control logic, and only four control signals.

[0027] It should be noted that the first bus and the second bus are mutually converted through a protocol conversion bridge, wherein the protocol conversion bridge includes a data conversion processing module and a protocol parsing module corresponding to each of the first bus and the second bus. Taking the first bus as an AHB high-speed bus and the second bus as an AXI bus as an example, the AHB and AXI buses need to be mutually converted through a protocol conversion bridge (APB AXI Bridge), including a data conversion processing module and a protocol parsing module of each bus.

[0028] In some embodiments, the hardware acceleration subsystem includes multiple processor (CPU) cores, namely Figure 1 Specifically, the multiple processor (CPU) cores are all implemented based on an instruction set of 32 bits or more, support single- and double-precision floating-point operations, and can assume corresponding functions such as system management, DSP processing, etc. according to needs.

[0029] Among these multiple processor (CPU) cores, processor core 1 has built-in ICache and DCache for external interfaces and internal control. Through standard SPI (slave mode) and UART interfaces, users can interact and manage the CPU to achieve different functional settings: the external interface realizes the control and management of user routing, events and security access, and the internal interface realizes RTP packet delay, sampling rate control, PTP clock deviation control and digital audio interface control. At the same time, a JTAG interface is reserved, and GDB can be used for code debugging to improve development and debugging efficiency.

[0030] Processor core 2 supports single- and double-precision floating-point operations and can be used as a floating-point unit (FPU) to perform gain, inversion, equalization, and compression on multi-channel digital audio signals input from I2S or TDM.

[0031] In some embodiments, the hardware acceleration subsystem includes two Gigabit or 100-Mbit media independent interfaces (RGMII / RMII, Reduced GigabitMedia Independent Interface / Reduced MediaIndependent Interface, is Reduced GMII / MII), namely Figure 1 Specifically, the two Gigabit or 100Mbit media independent interfaces both use a 4-bit data interface, a working clock of 125MHz, and transmit data at both the rising and falling edges, so the transmission rate can reach 1000Mbps, which can be used for communication between the media access control layer MAC and the physical layer PHY.

[0032] As an optional embodiment, one of the two Gigabit or 100 Mbit media independent interfaces serves as a primary network interface, and the other serves as a backup network interface.

[0033] As an optional embodiment, the two Gigabit or 100Mbit media independent interfaces are compatible with the Reduced Media Independent Interface (RMII interface), so that they can be connected to the Gigabit or 100M external PHY chip and support primary and standby network redundancy to achieve seamless switching.

[0034] As an optional embodiment, two Gigabit or 100 Mbit media independent interfaces are also connected to the APB bus, mainly used for connecting and configuring low-speed peripherals and IP registers.

[0035] Furthermore, in some embodiments, the hardware acceleration subsystem includes a real-time transport protocol RTP transceiver engine. Specifically, the RTP transceiver engine uses a dedicated hardware circuit (ASIC), which is a layer between the kernel and the RTP stack. The kernel provides a series of callback interfaces to complete different transactions (such as audio output, etc.), and the RTP engine needs to adapt these interfaces, that is, to encapsulate or decapsulate the RTP stack. Therefore, the RTP transceiver engine can be used to encapsulate and send network RTP data packets of digital audio streams, and to parse and restore network audio stream RTP data packets.

[0036] Optionally, the RTP transceiver engine receives and sends digital audio signals, the sampling frequency should support at least 44.1kHz, 48kHz, 96kHz and 192kHz, and the quantization accuracy should support at least 16 bits, 24 bits and 32 bits.

[0037] In this way, the hardware acceleration subsystem, based on the above-mentioned components it includes, can be used to encapsulate the digital audio stream accessed through the low-speed peripheral interface subsystem into RTP data packets according to the RTP network protocol through the RTP transceiver engine and send it to the media access control layer, and transmit it to the external physical layer chip through the gigabit medium independent interface, and, through the RTP transceiver engine, parse the RTP data packets of the network audio stream entering through the gigabit medium independent interface into digital audio streams for output through the low-speed peripheral interface subsystem.

[0038] That is to say, the digital audio stream is transmitted to the network audio stream RTP data packet encapsulation IP core through the TDM / I2S interface of the low-speed peripheral interface subsystem, and the digital audio stream is encapsulated into an RTP data packet according to the RTP network protocol and sent to the MAC layer, and enters the external PHY chip through the RGMII interface to realize the sending of high-performance network audio stream; the network audio stream RTP data packet enters the network audio stream RTP data packet decapsulation IP core through the PHY and RGMII interfaces, and is parsed into a digital audio stream, and output through the TDM / I2S interface, thereby realizing the reception of the network audio stream.

[0039] Therefore, the designed application-specific chip (ASIC) architecture has a great advantage in processing speed compared to SoC chips, and is the first application-specific chip design for high-performance AOIP network audio stream transmission; it adopts a multi-core processing architecture to realize digital audio processing on the basis of high-performance AOIP network audio stream transmission, and can provide safe, reliable, and high-quality audio signals; two gigabit or 100-megabit medium independent interfaces are used on the dedicated chip to transmit high-performance AOIP network audio streams, and it is compatible with a simplified media independent interface, which can be connected to a gigabit or 100-megabit external physical layer chip, and supports primary and standby network redundancy, which can realize seamless switching and well solve the reliability problem of AOIP network audio stream transmission.

[0040] Furthermore, in some embodiments, the hardware acceleration subsystem includes an encryption module and a decryption module. The encryption module is used to encrypt the digital audio signal, and the decryption module is used to decrypt the digital audio signal. Specifically, the encryption module and the decryption module support at least the following algorithms: AES128 F8, AES CTR, SM2, SM3, and SM4.

[0041] In some optional embodiments, the hardware acceleration subsystem includes two distributed controllers (Direct Memory Access, DMA), namely Figure 1 DMA controller 1 and DMA controller 2 in the system. Specifically, a distributed controller is a unique peripheral that transfers data within the system. It can be regarded as a controller that can connect internal and external memory to each DMA-capable peripheral through a set of dedicated buses. It performs the transfer under the programming control of the processor. Memory access technology for direct access of data between memory and peripherals. The control logic is composed of the core and the DMA control interface logic chip. Only peripherals with large data traffic need to support DMA capabilities, such as audio, video and network interfaces.

[0042] It should be noted that one of the two distributed controllers is used in conjunction with the primary network interface, and the other is used in conjunction with the backup network interface, that is, the two distributed controllers are used in conjunction with the primary network interface and the backup network interface, respectively.

[0043] As an optional embodiment, the two distributed controllers also set corresponding registers through the AHB bus.

[0044] In some optional embodiments, the hardware acceleration subsystem includes a static random access memory (SRAM), an automatic forwarding FIFO, and a true random number generator (TRNG). The static random access memory can keep the stored data permanently as long as it is powered on, and the data will disappear after the power supply stops; the automatic forwarding FIFO is a first-in-first-out data buffer for RTP data forwarding; the true random number generator is a device for generating random numbers, and the random numbers it outputs are generated based on physical random phenomena or processes, which have inherent randomness.

[0045] In another embodiment, the true random number generator further sets the true random number register via the APB bus.

[0046] In some optional embodiments, the hardware acceleration subsystem includes an IEEE1588 network precision clock synchronization module for time stamping the sent or received messages. Optionally, a dedicated hardware circuit is used to install a special clock synchronization packet detector and a timestamp marking unit at the media independent interface (RGMII) interface connecting the media access control layer (MAC) and the physical layer (PHY) to achieve time stamping for each special message (such as: Sync and Delay_Req) ​​sent or received. PTP (Precise Time Protocol) can achieve sub-microsecond time synchronization accuracy, which is mainly achieved through the Delay Request-Response Mechanism.

[0047] It can be understood that IEEE1588, the precise clock synchronization protocol for network measurement and control systems, can achieve frequency and phase synchronization between master and slave nodes through the sending of time messages and error measurement between the two, with an accuracy better than 100ns. Therefore, applying this technology to the media clock transmission of AoIP can achieve precise synchronization.

[0048] In some optional embodiments, the hardware acceleration subsystem can implement digital media clock management. Specifically, the digital media clock management performs frequency division processing on the synchronized local clock, provides a standard clock to TDM / I2S, and allows each audio device using a network transmission chip to closely track and synchronize to the reference clock, ensuring that nodes at any location in the network can output source signals with the same sampling frequency at the same reference time, so that audio data will not be lost due to synchronization loss caused by cache data overload (or cache bypass caused by too little data).

[0049] Optionally, for digital media clock management, the supported sampling frequencies shall include at least: 44.1kHz, 48kHz, 96kHz and 192kHz.

[0050] In summary, the hardware acceleration subsystem is based on the processor core 1, processor core 2, SRAM, automatic forwarding FIFO, encryption module, decryption module, true random number generator, IEEE1588 network precision clock synchronization module, RGMII interface 1, RGMII interface 2, RTP transceiver engine, DMA controller 1 and DMA controller 2 modules, and these modules are mounted on the AXI 128bit bus, which can realize hardware accelerated processing of business data, that is, through ASIC hardware acceleration, digital audio signal encryption and decryption, RTP audio stream transceiver, network clock synchronization, digital media clock management, digital audio processing and system control management functions can be realized.

[0051] In addition, in some embodiments, the high-speed peripheral interface subsystem includes a memory interface (ROM, read only memory), a first serial peripheral interface (ie Figure 1 The main SPI), the second serial peripheral interface (ie Figure 1 Specifically, the memory interface is used to store the secure boot program; the first serial peripheral interface provides high-speed, full-duplex synchronous serial communication, which is used to control the sending and receiving of audio data and the generation of clock signals; the second serial peripheral interface provides high-speed, full-duplex synchronous serial communication, which is used to receive the audio data and clock signals sent by the master device (i.e., the first serial peripheral interface), and transmit audio data under the control of the master device; the serial FLASH controller is used to communicate and control the external SPI FLASH, and store and read the audio data.

[0052] In this way, the high-speed peripheral interface subsystem is based on the ROM, SFC interface, master SPI, slave SPI interface, etc., and these interfaces are mounted on the AHB 32-bit high-speed bus, which can realize the reception, transmission, storage and read-write control of system control and management data inside and outside the dedicated chip.

[0053] Further, in some embodiments, the low-speed peripheral interface subsystem is used for chip status monitoring, control management data communication, burning protection, system control authority, real-time clock control, timing, counting, digital audio signal input and output, etc., mainly including some low-speed peripheral interface modules and system management modules, such as but not limited to: OTP (one time programmable interface), SysCtrl, GPIO (General-Purpose Input / Output, general input and output interface), I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), Watchdog, RTC (Real-Time-Clock, precise clock signal interface), TIMER, I2S (Inter-IC Sound) and TDM (Time Division Multiplexing). These modules are all mounted on the APB 32bit 100MHz bus, and the APB bus is also connected to the AXI 128bit bus corresponding to the hardware acceleration subsystem.

[0054] The following is a detailed description of each module in the low-speed peripheral interface subsystem:

[0055] OTP is used to store data that cannot be changed or can only be programmed once, ensuring that the code when the device starts cannot be changed. It can also store a unique serial number or device ID to prevent the device from being copied or impersonated. It can also store device configuration parameters such as calibration data and network settings, which will not be changed after leaving the factory. It can also store encryption keys or security authentication keys for encrypted communications or device authentication to improve security.

[0056] Sysctrl is mainly used for system control (responsible for managing various on-chip peripherals, including peripheral reset, clock management (such as clock source, frequency setting, gating, etc.), DMA planning, etc.), power management (by accessing the power management unit PMU, responsible for managing the power supply of the chip, including voltage regulation, clock control and reset), clock management (responsible for generating and managing the clock signal of the chip, including high-speed clock HSI, low-speed clock LSI, external clock HSE and internal oscillator MSI), reset management (detecting and processing reset events through the reset controller RST, including external reset, internal reset and watchdog reset), etc. It mainly controls these functions of the chip by accessing a series of registers and bit fields to ensure stable and efficient operation of the chip, and handle problems such as chip stuck or system crash.

[0057] GPIO is the basic module for the chip to interact with external devices. It can be configured as input mode (reading the level status of external devices) or output mode (output high or low level to control peripherals). It supports multiple modes (input mode, output mode, analog mode, multiplexed function mode) and configuration options (no pull-up or pull-down, pull-up or pull-down mode). It can also be configured as interrupt mode (responding to external events to improve system response speed and efficiency). It also usually contains protection diodes (to protect the chip from damage) and pull-up and pull-down resistors (setting the default state of the pin to avoid the influence of the pin's uncertain state). GPIO is mainly used for the chip to communicate with external devices, control hardware equipment, collect data, etc.

[0058] I2C is a bidirectional, two-wire serial communication interface, which is mainly used to realize the communication between the chip and other peripheral devices, such as sensors, memory and display. It can realize bidirectional communication and can connect multiple slave devices, up to 128. Each connected device has a unique address, and can send data to the slave device by broadcasting. After receiving the data, the slave device can confirm the reception through the response signal. It supports standard mode (100kHz) and fast mode (400kHz), and supports power management function, and can work in low power mode.

[0059] UART is mainly used to realize data transmission and communication between chips. It is an asynchronous serial communication interface that can realize bidirectional transmission. The working process is divided into three stages: data encoding (the sending end converts parallel data into serial data), data transmission (data is sent through the serial interface, and the receiving end detects changes in baud rate and bit period to determine the data transmission status) and data decoding (the receiving end converts the received serial data into parallel data, and uses parity check or cyclic redundancy check to detect and correct errors). The interface can also connect printers, sensors, industrial automation equipment, etc., and can also be used for program debugging, etc.

[0060] Watchdog is mainly used to prevent the system from crashing due to accidental running away. It monitors the running status of the system through the timer mechanism to ensure that the system can automatically restart when an abnormality occurs. The interface usually contains a timer (Watchdog Time, referred to as WDT). The timer has an input end (watchdog feeding end) and an output end. Under normal circumstances, the system will periodically send a signal to the watchdog feeding end to reset the timer. If the system stops sending signals for some reason, the timer will be triggered after the preset time is reached and send a reset signal to the system reset end to restart the system. This can effectively prevent the system from entering an infinite loop or freezing state due to program errors or hardware failures.

[0061] RTC, access to external precise clock signal, provides more accurate time information for the chip and maintains time accuracy after system power failure or restart.

[0062] TIMER is mainly used for periodic task processing and event timing. It controls the operation of the counter through the internal clock source or external trigger signal to achieve the timing function. It is mainly based on the operation and overflow mechanism of the counter. When the counter reaches the preset value, it will overflow and trigger an interrupt to execute the related timing tasks. Usually there are Oneshot mode (the counter stops after reaching the preset value and needs to be restarted), Auto reload mode (the counter automatically reloads and continues counting after reaching the preset value), UP mode (the counter starts to increase from 0 to the preset value), and DOWN mode (the counter decreases from the preset value to 0).

[0063] I2S is mainly used for the transmission of digital audio data. It is a serial bus standard that mainly includes a clock signal (SCK, which provides a clock reference for data transmission and controls the rate of data transmission), a word select signal (WS, which is used to distinguish between left and right channel data. When the level is low, the left channel data is transmitted, and when the level is high, the right channel data is transmitted), and a data signal (which transmits the actual audio data).

[0064] TDM is mainly used to transmit data of multiple audio channels simultaneously on a single data line, thereby reducing the number of chip pins. It uses time division multiplexing to distribute the data of multiple audio channels to different time slots. The data of each channel occupies 1 / N time of the frame, where N is a power of 2.

[0065] Furthermore, in some embodiments, the functional analog circuit subsystem includes an internal RC oscillator (IRC), a phase-locked loop (PLL), a low dropout linear regulator (LDO), an analog-to-digital converter (ADC SENSOR), a power-on reset circuit (POR), and a power-off reset circuit (BOR). Specifically, the internal RC oscillator is used to provide a stable clock signal and frequency source with low cost; the phase-locked loop is used to lock the phase and frequency of the input signal to a reference signal to generate an output signal consistent with the phase and frequency of the reference signal, and is mainly used for the chip to run at high frequency; the low dropout linear regulator is used to output the input voltage stably as a constant DC voltage, that is, to stabilize the input voltage to a constant output voltage, and provide a stable DC voltage to ensure that the system can operate normally under various working conditions; the analog-to-digital converter is used to convert the analog signal into a digital signal.

[0066] The main function of the power-on reset circuit is to ensure that the analog and digital modules can be initialized to a known state after power is applied, thereby avoiding the "competition" phenomenon and making the device static until the power supply voltage reaches a threshold that can ensure normal operation. It mainly includes power-on detection (when the chip is powered on, the power supply voltage will gradually rise), delay (after the power-on detection circuit detects that the power supply voltage has reached the threshold, it is necessary to give other circuits inside the chip a certain amount of time to adapt to the change in power supply voltage) and reset operation (after the delay ends, the reset circuit inside the chip starts to perform the reset operation).

[0067] The power-off reset circuit mainly protects the system from potential damage caused by low voltage. It mainly detects the change of power supply voltage and triggers the reset signal when the power supply voltage drops to a certain threshold. This mechanism ensures that the system can automatically enter the reset state when the power supply voltage is lower than the preset threshold, thereby preventing system errors or damage caused by low voltage.

[0068] In this way, the functional analog circuit subsystem can provide the chip with functions such as high-precision clock, phase-locked loop control, power-on / power-off reset, temperature and voltage sensing, and DC voltage stabilization based on the analog circuit modules it contains (IRC, PLL, POR, BOR, ADC sensor and LDO, etc.), and all data are mainly connected to the APB 32bit 100MHz bus corresponding to the low-speed peripheral interface subsystem through the SSC (sensor controller).

[0069] In addition, in some embodiments, the functional analog circuit subsystem is connected to the third bus via a sensor controller, wherein the sensor controller is used to perform signal type conversion of the audio signal between the sensor module of the functional analog circuit subsystem and the third bus.

[0070] Therefore, the ASIC chip for high-performance AOIP network audio stream transmission in the embodiment of the present application is the first to use a dedicated chip (ASIC) to achieve high-performance AOIP network audio transmission. The core functions are all accelerated in the hardware circuit, with fast processing speed and outstanding timeliness; it uses multi-core processing and is the first to achieve high-performance AOIP network audio transmission, digital audio processing and digital audio encryption and decryption functions; it is the first to use dual RGMII interfaces to transmit high-performance AOIP network audio streams, and is compatible with the RMII interface, can be connected to gigabit or 100 megabit external PHY chips, and supports primary and standby network redundancy to achieve seamless switching.

[0071] It should be noted that, for the convenience of description, the above device or system is described as various modules according to their functions. Of course, when implementing this application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0072] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0073] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0074] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0075] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. An ASIC chip for high-performance AOIP network audio stream transmission, characterized in that: The chip includes: a functional simulation circuit subsystem, a sensor controller, a clock and reset control module, and a high-speed peripheral interface subsystem arranged on a first bus, a hardware acceleration subsystem arranged on a second bus, and a low-speed peripheral interface subsystem arranged on a third bus, wherein the second bus is connected to the first bus and the third bus respectively, and the functional simulation circuit subsystem is connected to the third bus through the sensor controller; Wherein, the hardware acceleration subsystem includes multiple processor cores, two Gigabit or 100Mbit media independent interfaces and a real-time transport protocol RTP transceiver engine; Multiple processor cores are implemented with 32-bit or higher instruction sets; The two Gigabit or 100 Mbit media independent interfaces are both compatible with the simplified media independent interface. One of the two Gigabit or 100 Mbit media independent interfaces serves as a primary network interface, and the other serves as a backup network interface. The RTP transceiver engine is used to encapsulate and send the network RTP data packets of the digital audio stream, and to parse and restore the network audio stream RTP data packets.

2. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The hardware acceleration subsystem is used to encapsulate the digital audio stream accessed through the low-speed peripheral interface subsystem into RTP data packets according to the RTP network protocol through the RTP transceiver engine and send it to the media access control layer, and transmit it to the external physical layer chip through the gigabit medium independent interface, and to parse the network audio stream RTP data packets entering through the gigabit medium independent interface into digital audio streams through the RTP transceiver engine for output through the low-speed peripheral interface subsystem.

3. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The hardware acceleration subsystem also includes a static random access memory, an automatic forwarding FIFO, a true random number generator and two distributed controllers; One of the two distributed controllers cooperates with the active network interface, and the other cooperates with the standby network interface.

4. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The hardware acceleration subsystem also includes an IEEE1588 network precision clock synchronization module, which is used to add a time stamp to the sent or received messages.

5. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The hardware acceleration subsystem also includes an encryption module and a decryption module; The encryption module is used to encrypt the digital audio signal; The decryption module is used to perform decryption processing on the digital audio signal.

6. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 5, characterized in that: The algorithms supported by the encryption module and the decryption module include at least: AES128 F8, AES CTR, SM2, SM3, and SM4.

7. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The high-speed peripheral interface subsystem includes a memory interface, a first serial peripheral interface, a second serial peripheral interface and a serial FLASH controller; The memory interface is used to store a secure boot program; The first serial peripheral interface is used to control the sending and receiving of audio data and the generation of a clock signal; The second serial peripheral interface is used to receive the audio data and the clock signal sent by the first serial peripheral interface, and to perform audio data transmission under the control of the first serial peripheral interface; The serial FLASH controller is used to store and read audio data.

8. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The sensor controller is used to convert the signal type of the audio signal between the functional analog circuit subsystem and the third bus.

9. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The functional analog circuit subsystem includes an internal RC oscillator, a phase-locked loop, a low-dropout linear regulator, an analog-to-digital converter, a power-on reset circuit, and a power-off reset circuit; The internal RC oscillator is used to provide a stable clock signal and frequency source; The phase-locked loop is used to lock the phase and frequency of the input signal to the reference signal to generate an output signal consistent with the phase and frequency of the reference signal; The low voltage drop linear regulator is used to stably output the input voltage as a constant DC voltage; The analog-to-digital converter is used to convert an analog signal into a digital signal.

10. The ASIC chip for high-performance AOIP network audio stream transmission according to claim 1, characterized in that: The first bus and the second bus perform mutual conversion via a protocol conversion bridge, wherein the protocol conversion bridge comprises a data conversion processing module and protocol parsing modules corresponding to the first bus and the second bus respectively.

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