A coarse-grained reconfigurable array and a hardware modeling generation method thereof

Abstract

The application discloses a coarse-grained reconfigurable array and a hardware modeling generation method thereof, and belongs to the field of digital circuit design and processing technology. The coarse-grained reconfigurable array comprises a processing unit array of a reconfigurable array formed by M rows and N columns of processing units, a configuration memory for temporarily storing processing unit operation configuration information, a configuration bus and an input / output interface for connecting the configuration memory and the processing units. The modeling generation method comprises generating sub-module design parameters from top to bottom and generating hardware RTL level code from bottom to top by using an input top-level hardware design parameter. The coarse-grained reconfigurable array and the hardware modeling generation method can complete agile modeling and RTL level code generation of the coarse-grained reconfigurable array, realize target redirection of a driving compilation tool by designing a hardware description intermediate representation, and greatly improve the efficiency of hardware design and software stack development of a hardware accelerator.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design and processing technology, and in particular to a coarse-grained reconfigurable array and its hardware modeling generation method. Background Technology

[0002] In related technologies, traditional computing hardware includes general-purpose processors and application-specific integrated circuits (ASICs). The former offers greater flexibility but cannot meet the real-time requirements of specific application domains. Domain-specific hardware accelerators can provide orders of magnitude more speedup and energy efficiency than general-purpose processors; however, they require significant manual work in hardware design and software stack development and cannot simultaneously achieve flexibility. In recent years, coarse-grained reconfigurable arrays (CGRAs) have attracted widespread attention due to their favorable trade-off between programming flexibility and performance / energy consumption.

[0003] Traditional hardware RTL design directly maps to the hardware architecture, allowing designers to achieve extremely high performance through meticulous optimization, but this approach is inefficient. Existing automated hardware generation methods, such as high-level synthesis, can translate high-level languages ​​(e.g., C, C++, SystemC) into hardware RTL-level languages, but the resulting hardware often introduces greater area and performance overhead, and is difficult to debug and verify. Summary of the Invention

[0004] The purpose of this invention is to provide a coarse-grained reconfigurable array and its hardware modeling generation method, which can complete agile modeling and RTL-level code generation of coarse-grained reconfigurable arrays; achieve target redirection of the driver compilation tool by designing an intermediate hardware description representation; and greatly improve the efficiency of hardware accelerators in hardware design and software stack development.

[0005] To achieve the above objectives, the present invention provides a coarse-grained reconfigurable array, comprising:

[0006] The processing unit array is a reconfigurable array formed by M rows and N columns of processing units, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 1. The processing unit performs calculation or access operations according to the input operation configuration information and input data, and outputs the calculation or access results.

[0007] Configuration memory is used to temporarily store the operation configuration information required by each node in the processing unit array during execution;

[0008] A configuration bus is used to connect the configuration memory and the processing unit, and to input operation configuration information to at least one processing unit.

[0009] Input / output interfaces connect the processing unit to external devices, allowing data to be input into the processing unit or the calculation results to be output.

[0010] Preferably, each of the processing units in a column shares a configuration bus.

[0011] Preferably, the processing unit is an access unit or a computing unit;

[0012] The access unit is used to store and retrieve data. When the coarse-grained reconfigurable array is working, it stores input data before the computing unit starts computing, temporarily stores intermediate data during computing, and stores output data after the computing unit finishes computing.

[0013] The calculation unit is used to perform calculation operations based on the input operation configuration information and input data, and output the execution results.

[0014] Preferably, the access unit includes:

[0015] The storage configuration register is used to temporarily store storage operation configuration information input from the configuration bus;

[0016] The note storage device, composed of SRAM, is used to cache data;

[0017] The storage multiplexer is connected to the adjacent computing unit and selects the corresponding input data according to the storage operation configuration information in the storage register;

[0018] The logic unit is used to execute the logic of the access unit; according to the storage operation configuration information, when working in the loading state, it retrieves data from the note memory and outputs it; when working in the storage state, it stores input data in the note memory and directly outputs the input data.

[0019] Preferably, the storage operation configuration information includes input strobe information, address information for accessing data, and access operation code.

[0020] Preferably, the computing unit includes:

[0021] The calculation configuration register is used to temporarily store the calculation operation configuration information of the configuration bus input;

[0022] The calculation multiplexer connects to adjacent calculation units and selects the corresponding input data according to the calculation operation configuration information in the calculation register;

[0023] The synchronizer delays the input data selected by the multiplexer to synchronize the input data, and selects the corresponding data to be input into the arithmetic operation unit according to the delay selection information in the calculation operation configuration information.

[0024] The arithmetic operation unit performs arithmetic operations according to the calculation operation configuration information to obtain the result data; or directly outputs the input data.

[0025] Preferably, the computation operation configuration information includes input gating information, immediate values, delay gating information, and computation operation codes.

[0026] Preferably, the computing unit has a synchronizer only after the computing multiplexer on one side, and the operation is performed immediately when the next clock arrives after the input data of the computing multiplexer on the other side arrives.

[0027] The hardware modeling and generation method based on the above coarse-grained reconfigurable array includes the following steps:

[0028] S1. Modeling: The hardware structure of the coarse-grained reconfigurable array is divided into top-level design primitives, intermediate-level design primitives, and bottom-level design primitives. The top-level design primitive is the coarse-grained reconfigurable array itself. The intermediate-level design primitives include configuration memory, bus, computation unit, and access unit. The bottom-level design primitives include computation configuration register, computation multiplexer, synchronizer, arithmetic operation unit, storage configuration register, storage multiplexer, and note memory. Based on the input top-level hardware design parameters, the hardware of the top-level design primitives, intermediate-level design primitives, and bottom-level design primitives is modeled from top to bottom, and the sub-module hardware design parameters of the top-level design primitives, intermediate-level design primitives, and bottom-level design primitives are generated. The intermediate hardware description is output to drive the target redirection of the compilation tool.

[0029] S2. Generation: After modeling is completed, the hardware generator is instantiated from the bottom layer to the top layer based on the top-level hardware design parameters, intermediate-level hardware design parameters, and bottom-level hardware design parameters, and outputs hardware RTL-level code.

[0030] Preferably, in step S1, the hardware description intermediate representation includes a hardware architecture description and a hardware configuration description.

[0031] The advantages and positive effects of the coarse-grained reconfigurable array and its hardware modeling generation method described in this invention are: by designing an intermediate hardware description representation, the target redirection of the driver compilation tool is achieved. The coarse-grained reconfigurable array and its hardware modeling generation method described in this invention can greatly improve the efficiency of hardware accelerators in hardware design and software stack development, support highly flexible interconnect networks for processing unit arrays, and retain the good trade-off between programming flexibility and performance / power consumption of coarse-grained reconfigurable arrays.

[0032] 1. This invention can perform agile modeling and RTL-level code generation for coarse-grained reconfigurable arrays within a vast design space comprised of processing unit arrays and their homogeneity, interconnection networks, configuration systems, memory, etc.

[0033] 2. This invention makes it possible to design a retargetable compilation mapping method by designing an intermediate representation of the hardware description.

[0034] 3. This invention greatly improves the efficiency of hardware accelerators in hardware design and software stack development, supports highly flexible interconnection networks for processing unit arrays, and retains the good trade-off between programming flexibility and performance and power consumption of coarse-grained reconfigurable arrays.

[0035] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a coarse-grained reconfigurable array according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the computing unit of a coarse-grained reconfigurable array according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the access unit of a coarse-grained reconfigurable array according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the synchronizer for a coarse-grained reconfigurable array according to an embodiment of the present invention;

[0040] Figure 5 This is a flowchart of the coarse-grained reconfigurable array hardware modeling generation method according to an embodiment of the present invention. Detailed Implementation

[0041] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0042] In this application, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. In case of any inconsistency, the meaning as set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application. To accurately describe the technical content of this application and to accurately understand the invention, the following explanations or definitions of the terms used in this specification are provided before describing specific embodiments:

[0043] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0044] Example

[0045] like Figure 1 As shown. A coarse-grained reconfigurable array includes: a configuration memory, a processing unit array, a configuration bus, and input / output interfaces.

[0046] The processing unit array is a reconfigurable array consisting of M rows and N columns of processing units, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 1. Each processing unit performs specific calculations or access operations based on the input operation configuration information and input data, and outputs the calculation or access results.

[0047] The configuration memory, consisting of an array of registers, is used to temporarily store the operational configuration information required by each node in the processing unit array during execution. This operational configuration information includes the type of computation performed by each processing unit in the array, circuit selection information, and address information for accessing data.

[0048] The configuration bus is used to connect the configuration memory and the processing unit. The configuration bus inputs operation configuration information to at least one processing unit.

[0049] Each processing unit shares a configuration bus.

[0050] Input / output interfaces connect the processing unit directly to external devices such as memory, allowing data to be input into the processing unit or the calculation results to be output.

[0051] The processing unit array consists of two types of processing units: computing units (PE, Process Element) and storage units (LSU, Load Store Unit).

[0052] The access unit is used to store and retrieve data. When the coarse-grained reconfigurable array is working, it stores input data before the computing unit starts computing, temporarily stores intermediate data during computing, and stores output data after the computing unit finishes computing.

[0053] The calculation unit is used to perform calculation operations or logical operations based on the input operation configuration information and input data, and output the execution results.

[0054] The number of rows and columns in the processing unit array can be configured by the top-level hardware design parameters in the modeling method. Each processing unit can be connected to any other processing unit or input / output interface in the array, and the interconnection network of the processing units can be configured by the top-level hardware design parameters in the modeling method.

[0055] In this embodiment, the first and last columns of processing units in the processing unit array are configured as access units or computation units by the top-level hardware design parameters in the modeling method. The types of arithmetic or logical operations supported by the computation units are configured by the top-level hardware design parameters in the modeling method. Input / output interfaces can be connected to any processing unit, and the positions of the input / output interfaces are configured by the top-level hardware design parameters in the modeling method.

[0056] Figure 1 In this array, the interconnection network of the processing units is of type N2N (neighbor to neighbor). The first column of the processing unit array is configured as access units, and the last column of computing units is configured with input / output interfaces.

[0057] like Figure 2 As shown. The computing unit includes:

[0058] The Calculation Configuration Register (Config) is used to temporarily store the calculation operation configuration information of the configuration bus input.

[0059] The computation operation configuration information includes input gating information, immediate values ​​(const), delay gating information, and computation opcodes.

[0060] The computation multiplexer (MUX) connects to multiple adjacent computation units and selects the corresponding input data based on the computation operation configuration information in the computation register.

[0061] A synchronizer delays the input data selected by a multiplexer to synchronize the input data.

[0062] like Figure 4 As shown. The synchronizer consists of a cascaded register group, which can delay the input data selected by the multiplexer. The number of delay cycles is determined by the delay gating information in the calculation operation configuration information within this unit, so that the two input data of the calculation unit can be synchronized and the calculation operation can be performed within the same clock cycle.

[0063] The Arithmetic Logic Unit (ALU) performs arithmetic operations based on the opcodes in the computation operation configuration information to obtain the result data. It can also directly output input data, in which case the computation unit is used as a routing unit.

[0064] The arithmetic operation unit supports arithmetic operations including addition, subtraction, multiplication, shifting, comparison, and other arithmetic and logical operations.

[0065] The computation unit has a synchronizer only after a computational multiplexer on the right side. Input data requiring a delay is selected from the right-side computational multiplexer, and the operation is executed immediately when the next clock cycle arrives after the left-side input data arrives. This single-sided synchronizer design effectively reduces the hardware area while supporting data synchronization.

[0066] The types of arithmetic operations supported by the arithmetic operation unit and the depth of the synchronizer, i.e., the maximum number of delay cycles that can be supported, are configured by the top-level hardware design parameters in the modeling method. The number of input ports of the computation unit and the bit width of the configuration register are obtained by further calculation from the top-level design parameters in the modeling method.

[0067] like Figure 3 As shown. The access unit includes:

[0068] The storage configuration register is used to temporarily store storage operation configuration information input from the configuration bus.

[0069] Storage operation configuration information includes input strobe information, address information for accessing data, and access operation codes.

[0070] The note storage device, composed of SRAM (Static Random Access Memory), is used to cache data.

[0071] The storage multiplexer connects to multiple adjacent computing units and selects the corresponding input data based on the storage operation configuration information in the storage register.

[0072] The logic unit executes the logic of the access unit. Based on the storage operation configuration information, when working in the loading state, it retrieves data from the notepad memory and outputs it; when working in the storage state, it stores input data in the notepad memory and directly outputs the input data.

[0073] The word width and word length of the notepad memory, i.e., the memory capacity, are configured by the top-level design parameters in the modeling method. The number of input ports of the access unit and the bit width of the access configuration register are obtained through further calculations based on the top-level design parameters in the modeling method.

[0074] like Figure 5As shown. The above-described hardware modeling and generation method for coarse-grained reconfigurable arrays includes the following steps:

[0075] S1. Modeling: The coarse-grained reconfigurable array is abstracted into a series of hardware primitives. Based on the hardware structure of the coarse-grained reconfigurable array, the hardware primitives include three levels: top-level design primitives, intermediate-level design primitives, and bottom-level design primitives. The top-level design primitives represent the coarse-grained reconfigurable array itself. The intermediate-level design primitives include configuration memory, bus, computation unit, and access unit. The bottom-level design primitives include computation configuration register, computation multiplexer, synchronizer, arithmetic unit, memory configuration register, memory multiplexer, and notepad memory. Each hardware primitive corresponds to a hardware generator, and the input to the hardware generator is the design parameters of that hardware.

[0076] The hardware design parameters are validated based on the input top-level hardware design parameters to confirm their validity, and then a hardware architecture description (.json file) is generated. After the hardware architecture description is generated, the submodule hardware design parameters corresponding to the top-level design primitives, intermediate-level design primitives, and bottom-level design primitives are generated sequentially from top to bottom. After the submodule hardware design parameters are determined, a hardware configuration description is generated.

[0077] The hardware description intermediate representation (ADIR) output during the modeling process of coarse-grained reconfigurable arrays, including hardware architecture description and hardware configuration description (.json file), can be further used to drive target redirection of the compilation tool.

[0078] S2, Generation, starts after modeling is complete. After modeling is complete, the hardware generator is instantiated from the bottom layer to the top layer based on the top-level hardware design parameters, intermediate-level hardware design parameters, and bottom-level hardware design parameters, and outputs hardware RTL-level code.

[0079] The specific operation process is as follows: The top-level hardware design parameters are shown in Table 1.

[0080] Table 1 Top-level hardware design parameters

[0081]

[0082]

[0083] Table 1 shows the top-level hardware design parameters, their descriptions, and possible values. From these top-level hardware design parameters, design parameters for instantiating hardware generators at each level can be obtained directly or indirectly. `connect_topology` and `additional_connections` together form the complete interconnect network of the processing unit array. `connect_topology` represents the basic interconnect network, supporting systolic, N2N (n2n), diagonally connected N2N (n2n_diag), torus, and multi-hop connections. `additional_connections` represents additional routes added on top of the basic interconnect network. When `connect_topology` is "none", the interconnect network is uniquely determined by `additional_connections`.

[0084] The types of operations in the arithmetic operation unit of the calculation unit are shown in Table 2.

[0085] Table 2 shows the types of operations supported by the arithmetic operation unit.

[0086]

[0087] Table 2 shows that the arithmetic operation unit in this embodiment supports a total of 14 operation types, covering arithmetic operations, bitwise operations, and comparison operations. op0 and op1 represent the two operands input to the arithmetic operation unit, where op0 represents the operand selected by the synchronizer in the calculation unit, and op1 represents another operand directly selected by the calculation multiplexer in the calculation unit. The arithmetic operation unit determines the operation type to be executed based on the calculation operation configuration information (i.e., the opcode) corresponding to the arithmetic operation unit in the calculation configuration register, thus realizing reconfigurable calculation requirements.

[0088] The configuration bit widths of the computation multiplexers mux0 and mux1 in the computation unit, the configuration bit width alu in the arithmetic unit, the immediate bit width const, the synchronization unit bit width sync, and the total bit width of the computation configuration register pe_cfg_width can be calculated using the following formula:

[0089]

[0090] const = data_width

[0091]

[0092] The configuration bit width (alu) of the arithmetic operation unit is independent of the number of operations supported in the top-level hardware design parameters during hardware instantiation; it is only related to the number of operations supported by the arithmetic operation unit. More specifically, according to embodiments of this disclosure, as shown in Table 2, if the number of operations supported by the arithmetic operation unit is 14, then alu = 4, and the correspondence between the computation opcode and the operation type remains unchanged.

[0093] for Figure 1 The interconnection network is of N2N type. The first column is configured as access units, and the last column is configured as input / output ports. Each processing unit is connected to the four processing units above, below, left, and right. The access unit has 2 read ports and 1 write port, and the input / output interface has 2 inputs and 1 output. Therefore, max(inputs_num) = 5. If max_delay = 3, then according to the above formula, sync = 2 can be calculated. The complete configuration information of the computing unit is shown in Table 3. It can be represented by the following concatenation, where the right side represents the low-order bits, the left side represents the high-order bits, and the high-order bits are padded with 0.

[0094] Table 3. Complete configuration information of the computing unit

[0095] 20 bit, complement 0 2 bit, sync 3 bit, mux 1 3 bit, mux 0 4 bit, alu 32 bit, const

[0096] The configuration bit width mux of the memory multiplexer in the access unit, the memory address selection bit width sel_addr, and the total bit width lsu_cfg_width of the configuration register can be calculated using the following formulas:

[0097]

[0098] for Figure 1 The interconnect network is of N2N type. The first column of the processing unit array is configured as an access unit with only 1 input. Therefore, the access unit multiplexer is configured with a bit width of mux = 0. When sram_depth = 128, sel_addr = 8. The least significant bit WEN indicates write enable and is active low. Therefore, the complete configuration information of the access unit is shown in Table 4. The right side represents the low-order bits, and the left side represents the high-order bits, with high-order bits padded with 0.

[0099] Table 4. Complete configuration information of the access unit

[0100] 7 bit, complement 0 8 bit, sel_addr 1 bit, WEN

[0101] In the modeling process of coarse-grained reconfigurable arrays, the output intermediate hardware description includes a hardware architecture description and a hardware configuration description. The hardware architecture description extends the input top-level hardware design parameters and specifies the hardware's computation, storage, and routing resources. The hardware configuration description stores the one-to-one correspondence between the different multiplexer gating states, delay clock cycles, access addresses, and read / write enable parameters of the computation and access units—reconfigurable operating states and opcodes that require explicit configuration. The generated intermediate hardware description is used to drive subsequent reconfigurable compile-map designs.

[0102] Therefore, by employing the coarse-grained reconfigurable array and its hardware modeling generation method described in this invention, agile modeling and RTL-level code generation of coarse-grained reconfigurable arrays can be achieved; by designing an intermediate hardware description representation, the target redirection of the driver compilation tool can be realized; and the efficiency of hardware accelerators in hardware design and software stack development can be greatly improved.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A coarse-grained reconfigurable array, characterized in that, include: The processing unit array is a reconfigurable array formed by M rows and N columns of processing units, where M is an integer greater than or equal to 1 and N is an integer greater than or equal to 1. The processing unit performs calculation or access operations according to the input operation configuration information and input data, and outputs the calculation or access results. Configuration memory is used to temporarily store the operation configuration information required by each node in the processing unit array during execution; A configuration bus is used to connect the configuration memory and the processing unit, and to input operation configuration information to at least one processing unit. Input / output interfaces connect the processing unit to external devices, allowing data to be input into the processing unit or the calculation results to be output from the processing unit. The processing unit array consists of two types of processing units: computing units and storage units. The processing unit is either an access unit or a computing unit; The access unit is used to store and retrieve data. When the coarse-grained reconfigurable array is working, it stores input data before the computing unit starts computing, temporarily stores intermediate data during computing, and stores output data after the computing unit finishes computing. The calculation unit is used to perform calculation operations based on the input operation configuration information and input data, and output the execution results; The access unit includes: The storage configuration register is used to temporarily store storage operation configuration information input from the configuration bus; The note storage device, composed of SRAM, is used to cache data; The storage multiplexer is connected to the adjacent computing unit and selects the corresponding input data according to the storage operation configuration information in the storage register; The logic unit is used to execute the logic of the access unit; according to the storage operation configuration information, when working in the loading state, it retrieves data from the note memory and outputs it; when working in the storage state, it stores input data in the note memory and directly outputs the input data. The computing unit includes: The calculation configuration register is used to temporarily store the calculation operation configuration information of the configuration bus input; The calculation multiplexer connects to adjacent calculation units and selects the corresponding input data according to the calculation operation configuration information in the calculation register; The synchronizer delays the input data selected by the multiplexer to synchronize the input data, and selects the corresponding data to be input into the arithmetic operation unit according to the delay selection information in the calculation operation configuration information. The arithmetic operation unit performs arithmetic operations according to the operation code in the operation configuration information to obtain the result data; or directly outputs the input data. The computing unit has a synchronizer only on one side of the computing multiplexer, and the operation is performed immediately when the next clock arrives after the input data of the computing multiplexer on the other side arrives. A hardware modeling and generation method for coarse-grained reconfigurable arrays, characterized by comprising the following steps: S1. Modeling: The hardware structure of the coarse-grained reconfigurable array is divided into top-level design primitives, intermediate-level design primitives, and bottom-level design primitives. The top-level design primitive is the coarse-grained reconfigurable array itself. The intermediate-level design primitives include configuration memory, bus, computation unit, and access unit. The bottom-level design primitives include computation configuration register, computation multiplexer, synchronizer, arithmetic operation unit, storage configuration register, storage multiplexer, and note memory. Based on the input top-level hardware design parameters, the hardware of the top-level design primitives, intermediate-level design primitives, and bottom-level design primitives is modeled from top to bottom, and the sub-module hardware design parameters of the top-level design primitives, intermediate-level design primitives, and bottom-level design primitives are generated. The intermediate hardware description is output to drive the target redirection of the compilation tool. S2. Generation: After modeling is completed, the hardware generator is instantiated from the bottom layer to the top layer based on the top-level hardware design parameters, intermediate-level hardware design parameters, and bottom-level hardware design parameters, and outputs hardware RTL-level code.

2. The coarse-grained reconfigurable array according to claim 1, characterized in that: Each of the processing units in the column shares a configuration bus.

3. The coarse-grained reconfigurable array according to claim 1, characterized in that: The storage operation configuration information includes input strobe information, address information for accessing data, and access operation code.

4. A coarse-grained reconfigurable array according to claim 1, characterized in that: The computational operation configuration information includes input gating information, immediate values, delayed gating information, and computational opcodes.

5. A coarse-grained reconfigurable array according to claim 1, characterized in that: In S1, the hardware description intermediate representation includes hardware architecture description and hardware configuration description.

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