FRD process control method with positive conduction voltage drop as positive temperature characteristic

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to an FRD process control method with the characteristic that forward conduction voltage drop is positive temperature, and the method comprises the following steps: S1, ring base region process, S2, cut-off ring process, S3, Control process, S4, PT sputtering, S5, Pt kill, S6, metallization, S7, irradiation treatment, S8, back thinning, and S9, back gold process. In particular, through comprehensive application of the implantation dosage of boron ions, the diffusion condition of a platinum layer and electron irradiation, the method can ensure that the FRD has optimized performance that the forward conduction voltage drop is approximate to zero temperature or the positive temperature characteristic; and the forward conduction voltage drop can be kept in a relatively stable range and can also be improved along with the temperature rise, so that the current conduction capability and the thermal stability of the parallel device are improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to a FRD process control method with a forward conduction voltage drop having a positive temperature characteristic. Background Art

[0002] Fast recovery diodes (FRDs) are key components in power electronic devices, and their performance is crucial to the efficiency and reliability of the system. However, traditional FRDs have the problem of a forward voltage drop decreasing with increasing temperature under high-temperature working conditions, which seriously affects the performance and stability of the device in parallel application scenarios.

[0003] In traditional technologies, the forward voltage drop characteristics of FRDs usually show a trend of decreasing with increasing temperature. This characteristic will cause a series of problems in high temperature environments, such as directional increase in current density and thermal runaway, which will seriously affect the stability and life of the device. In order to solve this problem, the industry has been exploring how to develop an FRD whose forward voltage drop can increase with increasing temperature to ensure that excellent performance can be maintained under temperature conditions of different operating conditions.

[0004] Carrier lifetime is one of the key factors affecting the reverse recovery time and forward conduction voltage drop of FRD. In the prior art, although the carrier lifetime is regulated by introducing platinum diffusion (Pt killing) or irradiation treatment, these methods either have large leakage that affects reliability, or have negative temperature characteristics, making it difficult to achieve ideal temperature characteristics and high reliability requirements. As a result, in practical applications, the performance of FRD is often limited by the carrier lifetime regulation technology.

[0005] In addition, the existing FRD manufacturing process also faces many challenges. From high-energy ion implantation, chemical vapor deposition (CVD) to sputtering, electron irradiation and other technical means, each step requires precise control of parameters to ensure the performance of the final product. However, there is still room for improvement in some aspects of the existing process, such as optimization of doping concentration, improvement of withstand voltage performance, and metallization and contact processing, which need further research and improvement.

[0006] At the same time, the heat dissipation and welding interface design on the back of the wafer are also important factors affecting the reliability and application range of the device. The shortcomings of traditional processes in these aspects make FRD face many limitations in practical applications. Summary of the invention

[0007] 1. Technical issues to be resolved

[0008] In view of the deficiencies in the prior art, the present invention provides a FRD process control method with a forward conduction voltage drop having a positive temperature characteristic.

[0009] (II) Technical solution

[0010] To achieve the above object, the present invention provides the following technical solution: A FRD process control method with a forward conduction voltage drop having a positive temperature characteristic of the present invention comprises the following steps:

[0011] S1, Ring base area process

[0012] On the high-resistance epitaxial layer of the chip, a window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology with an implantation dose of 1e15 to 5e12;

[0013] S2, cut-off ring process

[0014] Phosphorus oxychloride (POCl3) is deposited in the chip terminal area using chemical vapor deposition (CVD) technology to form a cutoff ring;

[0015] S3, Contact process

[0016] Open the base window of the chip through photolithography to facilitate the subsequent contact metallization process;

[0017] S4, PT sputtering

[0018] A platinum layer is formed on the active area of ​​the chip using a sputtering device. The thickness of the platinum layer is The platinum layer is used to achieve subsequent Pt diffusion processing;

[0019] S5, Pt killing

[0020] The chip is placed in a high temperature environment (860-930°C) and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si epitaxial layer.

[0021] S6. Metallization

[0022] Using evaporation and photolithography processes, a metal layer is formed in the active area of ​​the chip to ensure a good current transmission path;

[0023] S7. Irradiation treatment

[0024] A high-energy electron beam is used to penetrate the chip, and the electron beam penetration parameter is 8 to 40 kGy, and annealing is performed at 280°C to 350°. The high-energy electron beam uses electron irradiation technology to further adjust the carrier lifetime;

[0025] S8, back thinning

[0026] Grind away excess substrate material from the chip to reduce thermal resistance and optimize device performance;

[0027] S9, Back Gold Process

[0028] A TiNiAg alloy layer is formed on the back side of the wafer using evaporation technology to provide good heat dissipation and welding interface.

[0029] Preferably, in step S1, the resistivity of the high-resistance epitaxial layer is 10-100 Ω·cm; and in step S2, the temperature range of the chemical vapor deposition (CVD) is 800-950°C.

[0030] Further preferably, in step S5, the diffusion temperature in the high temperature environment is 860°C to 930°C; in step S7, the dose of the high energy electron beam is 8 to 40 kgy, and the annealing temperature is 280°C to 350°C.

[0031] Again preferably, in step S8, the thickness of the wafer after grinding is 200 μm to 300 μm; in step S9, the thickness of the TiNiAg alloy layer is 1 to 5 μm.

[0032] Preferably, the method further comprises the following additional steps:

[0033] S10, testing and screening: Conduct electrical performance tests on the FRDs that have completed all the above process steps, and screen out qualified products that meet the forward conduction voltage drop and positive temperature characteristics;

[0034] S11. Packaging: The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

[0035] Further preferably, in step S1, the high energy ion implantation dose is 1e15-5e12; in step S2, the cut-off ring process further comprises: 3 After deposition, an annealing treatment is performed, wherein the diffusion temperature is 800-950° C. and the annealing time is 10-50 minutes.

[0036] Again preferably, in step S4, the formation of the platinum layer also includes pre-treatment of the active area surface before sputtering, and the pre-treatment includes any one of a cleaning treatment and an activation treatment; in step S5, the Pt killing process also includes pre-oxidation treatment before diffusion, wherein the pre-oxidation temperature is 800-900°C and the time is 10-30 minutes.

[0037] Preferably, in step S7, the irradiation treatment further comprises an annealing treatment after the electron irradiation, wherein the temperature range is: 280°C to 350°C.

[0038] (III) Beneficial effects

[0039] Compared with the prior art, the present invention provides a FRD process control method with a forward conduction voltage drop having a positive temperature characteristic, which has the following beneficial effects:

[0040] Optimizing forward conduction characteristics: By precisely controlling the process steps, especially the implantation dose of boron ions, the diffusion conditions of the platinum layer, and the comprehensive application of electron irradiation, this method can ensure that the FRD has an optimized performance of forward conduction voltage drop close to zero temperature or positive temperature characteristics. This characteristic enables the forward conduction voltage drop of the diode to remain within a relatively stable range when the temperature rises, and it can also increase with the increase in temperature, thereby improving the current conduction capability and thermal stability of the parallel device.

[0041] Improve reverse withstand voltage performance: Through specific process treatments, such as chemical vapor deposition to form a cutoff ring, the reverse withstand voltage reliability performance of FRD is effectively improved. This enables the diode to work more reliably under reverse voltage and reduces the risk of device failure caused by voltage breakdown.

[0042] Fast reverse recovery capability: Due to the use of special platinum layer diffusion and irradiation treatment process steps, this method enables FRD to have fast reverse recovery capability. This means that when the diode switches from the forward conduction state to the reverse blocking state, its recovery time is greatly shortened, thereby improving the overall response speed and efficiency of the circuit.

[0043] Improve reliability and stability: The entire process control method focuses on detail optimization and precise control, including additional steps such as testing and screening, packaging, etc., to ensure the reliability and stability of FRD in practical applications. This enables the diode to work stably for a long time in various harsh environments, reducing maintenance costs and failure rates.

[0044] In summary, this FRD process control method with a forward conduction voltage drop and a positive temperature characteristic significantly improves the performance and reliability of FRD by precisely controlling the process steps and optimizing the device structure, providing strong support for the application of high-frequency and high-power electronic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the process flow of the present invention;

[0046] Figure 2 It is a detailed schematic diagram of the key process steps of the present invention;

[0047] Figure 3 Schematic diagram of additional processing steps of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] See also Figure 1-3 The present invention provides a FRD process control method with a forward conduction voltage drop having a positive temperature characteristic, comprising the following steps:

[0050] S1, Ring base area process

[0051] On the high-resistance epitaxial layer of the chip, a window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology with an implantation dose of 1e15 to 5e12;

[0052] S2, cut-off ring process

[0053] Phosphorus oxychloride (POCl3) is deposited in the chip terminal area using chemical vapor deposition (CVD) technology to form a cutoff ring;

[0054] S3, Contact process

[0055] Open the base window of the chip through photolithography to facilitate the subsequent contact metallization process;

[0056] S4, PT sputtering

[0057] A platinum layer is formed on the active area of ​​the chip using a sputtering device. The thickness of the platinum layer is The platinum layer is used to achieve subsequent Pt diffusion processing;

[0058] S5, Pt killing

[0059] The chip is placed in a high temperature environment (860-930°C) and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si epitaxial layer.

[0060] S6. Metallization

[0061] Using evaporation and photolithography processes, a metal layer is formed in the active area of ​​the chip to ensure a good current transmission path;

[0062] S7. Irradiation treatment

[0063] A high-energy electron beam is used to penetrate the chip, and the electron beam penetration parameter is 8 to 40 kGy, and annealing is performed at 280°C to 350°. The high-energy electron beam uses electron irradiation technology to further adjust the carrier lifetime;

[0064] S8, back thinning

[0065] Grind away excess substrate material from the chip to reduce thermal resistance and optimize device performance;

[0066] S9, Back Gold Process

[0067] A TiNiAg alloy layer is formed on the back side of the wafer using evaporation technology to provide good heat dissipation and welding interface.

[0068] The FRD process control method with positive temperature characteristics of forward voltage drop provides a fast recovery diode (FRD) for insulated gate bipolar field effect transistor (IGBT) freewheeling tube. Through a series of precise process steps, it is ensured that the FRD has the characteristic that the forward voltage drop increases with the increase of temperature. The core working principles include:

[0069] Carrier lifetime control:

[0070] Platinum diffusion (Pt killing) and electron irradiation technology are used to precisely control the carrier lifetime, thereby affecting the reverse recovery time and forward conduction voltage drop of the device.

[0071] Doping concentration optimization:

[0072] By high-energy ion implantation of boron ions, the base doping concentration is optimized and the electrical properties are improved.

[0073] Improved pressure resistance:

[0074] A cut-off ring is formed in the terminal area to improve the edge voltage resistance of the device.

[0075] Metallization and contact optimization:

[0076] To ensure good current transmission paths and electrical connections, a base window is opened by photolithography and a metal layer is formed in the active area.

[0077] Heat dissipation and welding interface:

[0078] A TiNiAg alloy layer is evaporated on the back of the wafer to provide good heat dissipation and welding interface.

[0079] Working principles of each preferred technical solution

[0080] Ring base area process (S1)

[0081] Working principle: A window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology to optimize the base doping concentration and adjust the resistivity to improve the electrical properties.

[0082] Optimal parameters: the resistivity of the high-resistance epitaxial layer is 10 to 100 Ω·cm; the implantation depth is 0.5 to 2 μm.

[0083] Stop ring process (S2)

[0084] Working principle: Phosphorus oxychloride (POCl) is deposited in the terminal area using chemical vapor deposition (CVD) technology. 3 ), forming a cut-off ring and enhancing the edge pressure resistance.

[0085] Optimized parameters: POCl 3 After deposition, an annealing treatment is performed at a temperature of 900 to 1000° C. for 30 to 60 minutes.

[0086] Contact process (S3)

[0087] Working Principle: Photolithography is used to open a base window to ensure good electrical connection for subsequent contact metallization.

[0088] PT sputtering (S4)

[0089] Working principle: Use sputtering equipment to form a platinum layer in the active area with a thickness of Prepare for subsequent Pt diffusion treatment.

[0090] Pt killing(S5)

[0091] Working principle: FRD is placed in a high temperature environment (860℃~930℃), and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si substrate, shortening the carrier lifetime and increasing the reverse recovery speed.

[0092] Optimal parameters: diffusion time is 30 to 60 minutes; pre-oxidation treatment is performed before diffusion, the pre-oxidation temperature is 800 to 900° C., and the time is 10 to 30 minutes.

[0093] Metallization (S6)

[0094] Working principle: Deposition and photolithography processes are used to form a metal layer in the FRD active area to ensure a good current transmission path.

[0095] Irradiation treatment (S7)

[0096] Working principle: High-energy electron beam is used to penetrate FRD to adjust the carrier lifetime and further enhance the device stability and reliability.

[0097] Optimal parameters: electron beam dose of 8 to 40 kGy; annealing after irradiation at a temperature range of 280°C to 350°C.

[0098] Backside thinning (S8)

[0099] Working principle: Grind away excess FRD substrate material to reduce thermal resistance and optimize device performance.

[0100] Optimized parameters: The thickness of the wafer after grinding is 200μm to 300μm;

[0101] Back gold process (S9)

[0102] Working principle: Evaporation technology is used to form a TiNiAg alloy layer on the back of the wafer, providing good heat dissipation and welding interface.

[0103] Optimized parameters: TiNiAg alloy layer thickness is 1-5 μm; pre-plating treatment is performed before evaporation, such as titanium primer.

[0104] Detailed workflow

[0105] S1, Ring base area process

[0106] On the high-resistance epitaxial layer of the chip, a window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology with an implantation dose of 1e15 to 5e12;

[0107] S2, cut-off ring process

[0108] Phosphorus oxychloride (POCl3) is deposited in the chip terminal area using chemical vapor deposition (CVD) technology to form a cutoff ring;

[0109] S3, Contact process

[0110] Open the base window of the chip through photolithography to facilitate the subsequent contact metallization process;

[0111] S4, PT sputtering

[0112] A platinum layer is formed on the active area of ​​the chip using a sputtering device. The thickness of the platinum layer is The platinum layer is used to achieve subsequent Pt diffusion processing;

[0113] S5, Pt killing

[0114] The chip is placed in a high temperature environment (860-930°C) and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si epitaxial layer.

[0115] S6. Metallization

[0116] Using evaporation and photolithography processes, a metal layer is formed in the active area of ​​the chip to ensure a good current transmission path;

[0117] S7. Irradiation treatment

[0118] A high-energy electron beam is used to penetrate the chip, and the electron beam penetration parameter is 8 to 40 kGy, and annealing is performed at 280°C to 350°. The high-energy electron beam uses electron irradiation technology to further adjust the carrier lifetime;

[0119] S8, back thinning

[0120] Grind away excess substrate material from the chip to reduce thermal resistance and optimize device performance;

[0121] S9, Back Gold Process

[0122] A TiNiAg alloy layer is formed on the back side of the wafer using evaporation technology to provide good heat dissipation and welding interface.

[0123] S10. Testing and screening

[0124] The electrical performance of the chips that have completed all the above process steps is tested to screen out qualified products that meet the forward conduction voltage drop and positive temperature characteristics.

[0125] S11. Packaging

[0126] The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

[0127] Summarize

[0128] The present invention provides a FRD process control method with a positive temperature characteristic of forward conduction voltage drop. Through a series of fine process steps, the excellent performance of FRD under different temperature conditions is ensured. The key technical point is to use the global Pt lifetime control technology and the global irradiation lifetime control technology in combination to accurately control the carrier lifetime. At the same time, the specific parameters and sequence of each step also constitute an important part of patent protection. In addition, the additional testing, screening and packaging steps further ensure the reliability and stability of the product.

[0129] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A FRD process control method with a forward conduction voltage drop having a positive temperature characteristic, characterized in that: The following steps are involved: S1, Ring base area process On the high-resistance epitaxial layer of the chip, a window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology with an implantation dose of 1e15 to 5e12; S2, cut-off ring process Phosphorus oxychloride (POCl3) is deposited in the chip terminal area using chemical vapor deposition (CVD) technology to form a cutoff ring; S3, Contact process Open the base window of the chip through photolithography to facilitate the subsequent contact metallization process; S4, PT sputtering A platinum layer is formed on the active area of ​​the chip using a sputtering device. The thickness of the platinum layer is The platinum layer is used to achieve subsequent Pt diffusion processing; S5, Pt killing The chip is placed in a high temperature environment (860-930°C) and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si epitaxial layer. S6. Metallization Using evaporation and photolithography processes, a metal layer is formed in the active area of ​​the chip to ensure a good current transmission path; S7. Irradiation treatment A high-energy electron beam is used to penetrate the chip, and the electron beam penetration parameter is 8 to 40 kGy, and annealing is performed at 280°C to 350°. The high-energy electron beam uses electron irradiation technology to further adjust the carrier lifetime; S8, back thinning Grind away excess substrate material from the chip to reduce thermal resistance and optimize device performance; S9, Back Gold Process A TiNiAg alloy layer is formed on the back side of the wafer using evaporation technology to provide good heat dissipation and welding interface.

2. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 1, characterized in that: In step S1, the resistivity of the high-resistance epitaxial layer is 10-100 Ω·cm; in step S2, the temperature range of the chemical vapor deposition (CVD) is 800-950°C.

3. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 2, characterized in that: In step S5, the diffusion temperature in the high temperature environment is 860°C to 930°C; in step S7, the dose of the high energy electron beam is 8 to 40 kgy, and the annealing temperature is 280°C to 350°C.

4. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 3, characterized in that: In step S8, the thickness of the wafer after grinding is 200-300 μm; in step S9, the thickness of the TiNiAg alloy layer is 1-5 μm.

5. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 4, characterized in that: The following additional steps are also included: S10, testing and screening: Conduct electrical performance tests on the FRDs that have completed all the above process steps, and screen out qualified products that meet the forward conduction voltage drop and positive temperature characteristics; S11. Packaging: The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

6. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 5, characterized in that: In step S1, the high energy ion implantation dose is 1e15-5e12; in step S2, the cut-off ring process further includes annealing after POCl3 deposition, wherein the diffusion temperature is 800-950°C and the annealing time is 10-50 minutes.

7. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 6, characterized in that: In step S4, the formation of the platinum layer also includes pre-treatment of the active area surface before sputtering, and the pre-treatment includes any one of a cleaning treatment and an activation treatment; in step S5, the Pt killing process also includes pre-oxidation treatment before diffusion, wherein the pre-oxidation temperature is 800-900°C and the time is 10-30 minutes.

8. The FRD process control method with a forward conduction voltage drop having a positive temperature characteristic according to claim 7, characterized in that: In step S7, the irradiation treatment further includes an annealing treatment after the electron irradiation, wherein the temperature range is: 280°C to 350°C.

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