A method for manufacturing a piezoresistive chip of a monolithic integrated CMOS circuit

Abstract

The application discloses a manufacturing method of a piezoresistive chip of a monolithic integrated CMOS circuit, and belongs to the field of MEMS sensor and CMOS chip manufacturing. In order to solve the problems of high manufacturing complexity and high cost in the process of monolithic integration of the piezoresistive chip and the CMOS circuit, the application mainly adopts a combination of multiple ion implantation processes in a standard CMOS process, and generates a mask layout pattern of a piezoresistive sensitive unit accurately by modifying a layout generation rule, so that multiple doping concentration distribution designs of the piezoresistive sensitive unit are realized. The method can manufacture the piezoresistive chip of the monolithic integrated CMOS circuit with different performance indexes, adapt to diversified application requirements, and is compatible with the standard CMOS process, has the advantages of low research and development cost and large-scale production, is widely applicable to the production of commercial CMOS foundries, and can meet the rapidly growing market demand of the piezoresistive chip.

Description

Technical Field

[0001] This invention belongs to the field of MEMS sensors and CMOS chip manufacturing, and specifically relates to a method for manufacturing a piezoresistive chip with a monolithic integrated CMOS circuit. Background Technology

[0002] MEMS (Micro Electro Mechanical Systems) is an emerging interdisciplinary high-tech research field that enables the sensing, processing, and execution of signals such as force, electricity, light, magnetism, and sound. It has already found widespread application in industries such as manufacturing, automotive electronics, aerospace, and biomedicine. Piezoresistive chips, due to their advantages of small size, high reliability, simple signal conditioning circuitry, and simple fabrication processes, are widely manufactured as MEMS piezoresistive sensors for detecting physical quantities such as pressure, acceleration, and flow rate. Their market size and demand have increased rapidly in recent years.

[0003] A piezoresistive chip is a chip in which the piezoresistive sensing element has been fabricated, but the MEMS structure has not yet been processed for the specific sensor type. Its working principle is based on the piezoresistive effect, where the piezoresistive sensing element, made of semiconductor material, exhibits a change in resistance under stress, thereby converting a non-electrical signal into an electrical signal output. Therefore, the performance of a piezoresistive chip mainly depends on the performance of the piezoresistive sensing element, including sensitivity, linearity, temperature coefficient, and noise. Fabricating a high-performance piezoresistive chip is fundamental to the subsequent fabrication of high-performance MEMS piezoresistive sensors.

[0004] To achieve high-performance piezoresistive chips, besides adjusting the design of the piezoresistive sensing element, such as its size and doping concentration distribution, another approach is to monolithically integrate the piezoresistive chip with a CMOS circuit. Leveraging the advantages of CMOS circuits in fast and precise signal processing, the output of the piezoresistive chip can be amplified, temperature drift compensated, nonlinearity corrected, and analog-to-digital converted, while simultaneously eliminating additional noise from lead connections, thereby improving its performance.

[0005] However, achieving monolithic integration of piezoresistive chips with CMOS circuits and mass production to meet market demand still presents challenges in manufacturing processes. A major difficulty lies in manufacturing the piezoresistive sensing element while maintaining monolithic integration with CMOS circuits. Currently, piezoresistive sensing elements are manufactured using a single ion implantation process. Designing different piezoresistive sensing elements requires adjusting the parameters of this ion implantation process, such as implantation energy, dosage, and impurity types. In a laboratory environment, adjusting the ion implantation process parameters is easy, allowing for repeated experiments to produce piezoresistive chips with optimal performance. However, the processing and time costs make it difficult to scale up laboratory samples for commercial production. To address this, some well-known sensor companies have launched self-developed process flows that balance mass production and experimental costs, such as Bosch's advanced porous silicon process and Toshiba's silicon migration technology. However, developing specialized manufacturing processes requires significant R&D investment to build production lines, limiting the large-scale application of such solutions. Summary of the Invention

[0006] The objective of this invention is to solve the aforementioned problems by providing a method for manufacturing a piezoresistive chip with a monolithic integrated CMOS circuit. Based on a standard CMOS process production line, this method uses a combination of multiple ion implantation processes to fabricate the piezoresistive sensing unit. This method allows for prediction of the piezoresistive chip's performance during the design phase, eliminating the need for repeated iterative experiments, resulting in low R&D costs, enabling large-scale production, and meeting the growing market demand.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A method for manufacturing a piezoresistive chip for a monolithic integrated CMOS circuit includes the following steps:

[0009] 1)Perform performance simulation of piezoresistive sensitive units fabricated by different ion implantation process combinations, analyze the temperature coefficient of resistance, temperature coefficient of sensitivity, sensitivity and noise parameters, and select the ion implantation process combination that meets the application requirements.

[0010] 2) Select a silicon wafer as the substrate;

[0011] 3) A silicon dioxide oxide layer is grown on the surface of a silicon wafer, silicon nitride is deposited, and trenches are formed by photolithography and etching. After filling the trenches, planarization is performed to form an STI structure.

[0012] 4) A sacrificial oxide layer of silicon dioxide is grown on the surface of the silicon wafer. After photolithography, N-well implantation, P-well implantation and deep N-well implantation are performed to form N-wells, P-wells and deep N-wells. If the selected ion implantation process combination includes one or more of N-well implantation, P-well implantation and deep N-well implantation, the selected ion implantation process is also used to implant the region forming the piezoresistive sensitive cell. After all is completed, rapid thermal annealing is performed.

[0013] 5) Remove the sacrificial oxide layer from the silicon wafer surface, grow the gate oxide layer and deposit polysilicon, and form the polysilicon gate through photolithography and etching; after photolithography, perform N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, P-type low-voltage lightly doped source / drain implantation, and P-type high-voltage lightly doped source / drain implantation to form the lightly doped source / drain region of the MOS device, as well as the lightly doped connection region for connecting the piezoresistive sensitive cell to the metal interconnect layer; if the selected ion implantation process combination includes one or more of N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, P-type low-voltage lightly doped source / drain implantation, and P-type high-voltage lightly doped source / drain implantation, the selected ion implantation process is also used to implant the region forming the piezoresistive sensitive cell; after all are completed, perform rapid thermal annealing;

[0014] 6) A composite dielectric layer is deposited on the silicon wafer surface, and sidewalls surrounding the polysilicon gate are etched. After photolithography, N-type source / drain, P-type source / drain, trap contact region, and heavily doped connection region are formed by N-type source / drain implantation and P-type source / drain implantation. If the selected ion implantation process combination includes one or both of N-type and P-type source / drain implantation, the selected ion implantation process is also used to implant the region forming the piezoresistive sensitive cell. After all is completed, rapid thermal annealing is performed.

[0015] 7) Perform photolithography to form a high-resistance polysilicon resistor by implanting a high-resistance polysilicon resistor; perform photolithography to form an electrostatic discharge NMOS transistor by implanting an electrostatic discharge transistor; if the selected ion implantation process combination includes one or both of high-resistance polysilicon resistor implantation and electrostatic discharge implantation, the selected ion implantation process is used simultaneously to implant the region forming the piezoresistive sensitive cell.

[0016] 8) A metal silicide barrier layer is deposited on the silicon wafer surface. The protected area is then masked by photolithography and etching. A layer of cobalt metal is then deposited on the silicon wafer surface. After two rapid annealing processes, cobalt silicide is formed in the areas not protected by the metal silicide barrier layer. A dielectric layer and a passivation layer are deposited on the silicon wafer surface and planarized. Vias are formed by photolithography and etching. Tungsten metal is then filled into the vias and planarized. A metal interconnect layer is then deposited on the silicon wafer surface and photolithography and etching are performed. The dielectric layer and passivation layer are then deposited again. This process is repeated to form multiple layers of metal interconnect layers, dielectric layers, and passivation layers, ultimately completing the fabrication of a monolithic integrated CMOS piezoresistive chip.

[0017] Furthermore, the ion implantation process combination in step 1) includes one or more of the following P-type ion implantation and N-type ion implantation;

[0018] P-type ion implantation includes P-well implantation, P-type low-voltage lightly doped source / drain implantation, P-type high-voltage lightly doped source / drain implantation, P-type source / drain implantation, electrostatic discharge implantation, and high-resistance polysilicon resistor implantation.

[0019] N-type ion implantation includes N-well implantation, deep N-well implantation, N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, and N-type source / drain implantation.

[0020] Furthermore, step 1) involves analyzing the temperature coefficient of resistance, temperature coefficient of sensitivity, sensitivity, and noise parameters, including:

[0021] The doping concentration distribution of piezoresistive sensitive cells under different combinations of ion implantation processes was simulated using process simulation tools.

[0022] The average longitudinal and transverse stress difference distribution on the surface of the piezoresistive sensitive element was simulated and calculated using finite element analysis tools.

[0023] Substituting the doping concentration distribution and the average longitudinal and transverse stress difference distribution into the resistance temperature coefficient model, sensitivity temperature coefficient model, sensitivity model, and noise model, the resistance temperature coefficient, sensitivity temperature coefficient, sensitivity, and noise parameters are calculated.

[0024] Furthermore, in step 2), the silicon wafer selected as the substrate is P-type single crystal silicon with the following parameters: crystal plane is (100), and the Notch slot position orientation is crystal direction. <110> The surface resistivity is 8.5–11.5 Ω·cm.

[0025] Furthermore, step 3) involves forming the trenches through photolithography and etching, including:

[0026] A mask is set on the surface of a silicon wafer to create the active region, and the areas used to manufacture the source / drain / channel, well contact and piezoresistive sensitive cell of the MOS transistor are preserved by photolithography.

[0027] Trenches are formed by etching the non-active regions of silicon nitride, silicon dioxide, and the silicon substrate.

[0028] Furthermore, in step 3), high-density plasma chemical vapor deposition technology is used to deposit silicon oxide to fill the trenches; and chemical mechanical polishing process is used to remove excess silicon oxide and silicon nitride from the surface to achieve global planarization.

[0029] Further, during N-trap implantation in step 4), impurities phosphorus, phosphorus, and arsenic are implanted sequentially, with implantation energies and doses as follows:

[0030] Phosphorus: Injection energy 400-450 keV, injection dose 10 13 ~10 14 cm -2 ;

[0031] Phosphorus: Injection energy 150-200 keV, injection dose 10 12 ~10 13 cm-2 ;

[0032] Arsenic: Injection energy 150-200 keV, injection dose 10 13 ~10 14 cm -2 ;

[0033] During deep N-well implantation, impurity phosphorus is injected twice, with the following injection energies and doses:

[0034] Phosphorus: Injection energy 1500-2000 keV, injection dose 10 13 ~10 14 cm -2 ;

[0035] Phosphorus: Injection energy 500-1000 keV, injection dose 10 12 ~10 13 cm -2 ;

[0036] During P-well implantation, impurities boron, indium, and boron are implanted sequentially, with implantation energies and doses as follows:

[0037] Boron: Implantation energy 150-200 keV, implantation dose 10 13 ~10 14 cm -2 ;

[0038] Indium: Implantation energy 150–200 keV, implantation dose 10 12 ~10 13 cm -2 ;

[0039] Boron: Injection energy 20-50 keV, injection dose 10 12 ~10 13 cm -2 .

[0040] Furthermore, in step 4), a PMOS device is fabricated in the N-well and an NMOS device is fabricated in the P-well to form a PN junction for isolation.

[0041] Further, in step 5), wet etching is used to remove the sacrificial oxide layer on the surface; a first oxidation process is performed on the silicon wafer surface, followed by photolithography and etching to define the thin gate oxide region, and then a second oxidation process is performed to grow the thick gate oxide layer of the high-voltage MOS transistor and the thin gate oxide layer of the low-voltage MOS transistor.

[0042] Furthermore, step 5) involves forming the polysilicon gate through photolithography and etching, including:

[0043] A mask for setting polysilicon gates is placed on the surface of a silicon wafer, and photolithography is performed to etch away the polysilicon in the non-CMOS device gate and polysilicon resistor regions.

[0044] After etching to remove the resist, the silicon wafer and polysilicon are re-oxidized to form a thin oxide layer, which ultimately forms the polysilicon gate.

[0045] Furthermore, during N-type low-voltage lightly doped source-drain implantation in step 5), indium and arsenic impurities are implanted sequentially, with implantation energies and doses as follows:

[0046] Indium: Implantation energy 150–200 keV, implantation dose 10 13 ~10 14 cm -2 ;

[0047] Arsenic: Injection energy 5-20 keV, injection dose 10 14 ~10 15 cm -2 ;

[0048] During N-type high-voltage, lightly doped source / drain implantation, phosphorus impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 13 ~10 14 cm -2 ;

[0049] During P-type low-voltage lightly doped source-drain implantation, arsenic impurities and boron fluoride are implanted sequentially, with implantation energies and doses as follows:

[0050] Arsenic: Injection energy 150-200 keV, injection dose 10 13 ~10 14 cm -2 ;

[0051] Boron fluoride: Implantation energy 5–20 keV, implantation dose 10 14 ~10 15 cm -2 ;

[0052] During P-type high-voltage, lightly doped source-drain implantation, boron fluoride impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 13 ~10 14 cm -2 .

[0053] Furthermore, in step 6), a low-pressure chemical vapor deposition process is used to sequentially deposit silicon oxide, silicon nitride, and silicon oxide to form a composite dielectric layer.

[0054] Further, during the N-type source / drain injection in step 6), impurities arsenic and phosphorus are injected sequentially, with the injection energy and dosage as follows:

[0055] Arsenic: Injection energy 20-100 keV, injection dose 10 15 ~10 16 cm -2 ;

[0056] Phosphorus: Injection energy 20-50 keV, injection dose 10 13 ~10 14 cm -2 ;

[0057] During P-type source / drain implantation, impurity boron is injected twice, with the following injection energies and doses:

[0058] Arsenic: Injection energy 5-20 keV, injection dose 10 15 ~10 16 cm -2 ;

[0059] Phosphorus: Injection energy 20-50 keV, injection dose 10 13 ~10 14 cm -2 .

[0060] Further, in step 7), during the implantation of the high-resistivity polycrystalline silicon resistor, boron fluoride impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 14 ~10 15 cm -2 During electrostatic discharge injection, the injected impurity is boron, the injection energy is 20–50 keV, and the injection dose is 10 times the injection dose. 13 ~10 14 cm -2 .

[0061] Furthermore, in step 8), a silicon-rich oxide layer is deposited on the silicon wafer surface using a plasma chemical vapor deposition process as a metal silicide barrier layer.

[0062] Furthermore, in step 8), a layer of cobalt metal is deposited on the silicon wafer surface using a physical vapor deposition process.

[0063] Further, in step 8), the silicon wafer surface is subjected to dry etching and wet etching to remove areas not protected by the metal silicide barrier layer.

[0064] Furthermore, in step 8), one or more of the following processes are used: plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, and high-density plasma chemical vapor deposition to deposit various materials such as silicon oxynitride, borosilicate glass, silicon dioxide, fluorosilicon glass, undoped silicon glass, and silicon nitride to form a dielectric layer and a passivation layer.

[0065] Furthermore, in step 8), the tungsten surface is ground and planarized using a chemical mechanical polishing process.

[0066] Further, in step 8), an aluminum-copper alloy is deposited on the silicon wafer surface as a metal interconnect layer material, and the metal interconnect layer is planarized by a chemical mechanical polishing process.

[0067] Furthermore, the number of metal interconnect layers in step 8) is 3, 4, 5 or 6.

[0068] The beneficial effects achieved by this invention are as follows:

[0069] 1. This invention provides a method for manufacturing a piezoresistive chip based on standard CMOS technology and a monolithically integrated CMOS circuit, thereby realizing the monolithic integration of the piezoresistive chip and the CMOS circuit, achieving functions such as signal processing, amplification, drift compensation, nonlinear correction and analog-to-digital conversion, avoiding the influence of lead connection noise, and improving the performance of the piezoresistive chip.

[0070] 2. By combining different ion implantation processes, this invention can prepare piezoresistive sensitive units with different doping concentration distributions, realize piezoresistive chips with monolithic integrated CMOS circuits of various performance indicators, and meet the needs of different application scenarios.

[0071] 3. This invention, by appropriately modifying and optimizing the standard CMOS process layout generation rules, enables the correct generation of piezoresistive sensitive cell patterns on the masks corresponding to all ion implantation processes without affecting the generation of CMOS circuit patterns on the masks. This allows for the combination of different ion implantation processes to fabricate piezoresistive sensitive cells with adjustable performance.

[0072] 4. The manufacturing method used in this invention is compatible with standard CMOS processes, requires no special requirements for existing processes, can be implemented in most commercial CMOS foundries, reduces R&D costs, enables large-scale production, and meets the growing market demand. Attached Figure Description

[0073] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate specific embodiments of the manufacturing method and their descriptions, serving to explain the principles of the invention.

[0074] Figure 1 A schematic diagram of the P-type silicon substrate used;

[0075] Figure 2 This is a schematic diagram of the STI structure after it has been formed.

[0076] Figure 3 A schematic diagram of CMOS circuitry and piezoresistive sensing elements implanted using the P-well implantation process;

[0077] Figure 4A schematic diagram of CMOS circuitry and piezoresistive sensing cells implanted using a P-type high-voltage lightly doped source-drain implantation process;

[0078] Figure 5 A schematic diagram of CMOS circuitry and heavily doped connection regions implanted using a P-type source / drain implantation process;

[0079] Figure 6 A schematic diagram of implanting high-resistance polysilicon resistors and piezoresistive sensing units using a high-resistance polysilicon resistor implantation process;

[0080] Figure 7 This is a schematic diagram of a piezoresistive chip that has been processed to form a monolithic integrated CMOS circuit.

[0081] Explanation of markings in the diagram:

[0082] 1-Substrate; 2-STI structure;

[0083] 3-Silica; 4-Deep N-well;

[0084] 5-N trap; 6-P trap;

[0085] 7 - Piezoresistive sensing element; 8 - P-well injection;

[0086] 9 - Polysilicon gate; 10 - Lightly doped N-type source / drain;

[0087] 11-P-type lightly doped source / drain; 12-Lightly doped connection region;

[0088] 13-P-type high-voltage lightly doped source / drain implantation; 14-Thick gate oxide layer;

[0089] 15-Sidewall; 16-N-type source / drain;

[0090] 17-P-type source / drain; 18-Heavily doped junction region;

[0091] 19-P type source-drain injection; 20-P type well contact region;

[0092] 21 - N-well contact region; 22 - High-resistance polysilicon resistor implantation;

[0093] 23 - High-resistance polysilicon resistor; 24 - Electrostatic discharge NMOS transistor;

[0094] 25-Metal silicide barrier layer; 26-Cobalt silicide;

[0095] 27 - Through-hole; 28 - Metal interconnect layer;

[0096] 29-Dielectric layer and passivation layer. Detailed Implementation

[0097] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in detail with reference to the accompanying drawings.

[0098] This invention provides a method for manufacturing a piezoresistive chip based on a 0.18μm mixed-signal 1P3M standard CMOS process production line with a monolithically integrated CMOS circuit. The monolithically integrated CMOS piezoresistive chip refers to the monolithic integration of a CMOS circuit and a piezoresistive sensing unit on a silicon substrate. This method uses a deep N-well as the substrate for the piezoresistive sensing unit and fabricates the piezoresistive sensing unit through a combination of ion implantation processes including P-well implantation, P-type high-voltage lightly doped source-drain implantation, and high-resistance polysilicon resistor implantation. The processing steps of this method are described below:

[0099] S1: Performance Simulation and Optimization

[0100] First, performance simulation analysis was performed on the piezoresistive sensing cell fabricated using a 0.18μm mixed-signal 1P3M standard CMOS process with different combinations of ion implantation processes. The specific steps are as follows:

[0101] 1. Ion implantation process combination:

[0102] P-type ion implantation includes P-type well implantation, P-type 1.8V lightly doped drain implantation, P-type 3.3V lightly doped drain implantation, P-type source / drain implantation, P-type electrostatic discharge implantation, and high-resistance polysilicon resistor implantation.

[0103] N-type ion implantation includes N-type well implantation, deep N-type well implantation, N-type 1.8V lightly doped drain implantation, N-type 3.3V lightly doped drain implantation, and N-type source / drain implantation.

[0104] 2. Simulation Analysis: Using process simulation tools, the doping concentration distribution of the piezoresistive sensing element under different ion implantation process combinations is simulated. Finite element analysis tools are used to simulate and calculate the average longitudinal and transverse stress difference distribution on the surface of the piezoresistive sensing element.

[0105] 3. Model Calculation: Substitute the doping concentration distribution and the average longitudinal and transverse stress difference distribution into the following calculation model for analysis:

[0106] Temperature coefficient of resistance (TCR) model: used to evaluate the effect of temperature change on resistance, the formula is as follows:

[0107]

[0108] Where TCR is the temperature coefficient of resistance, μ is the carrier mobility, h is the junction depth of the piezoresistive sensitive cell, z is the distance in the depth direction, and N is the doping concentration.

[0109] Sensitivity Temperature Coefficient (TCS) model: used to analyze the change in sensitivity with temperature, the formula is as follows:

[0110]

[0111] Where TCS is the temperature coefficient of sensitivity.

[0112] Sensitivity model: used to evaluate the sensitivity of the piezoresistive sensing element, the formula is as follows:

[0113]

[0114] in, π represents the rate of change of resistance, i.e., the sensitivity of the piezoresistive sensing element. ref Let P(z) be the piezoresistive coefficient of the piezoresistive sensing unit under low doping concentration and room temperature conditions, and let P(z) be the piezoresistive factor. This represents the average longitudinal and transverse stress difference along the longitudinal direction of the piezoresistive sensitive element surface.

[0115] Noise model: used to evaluate the impact of noise on performance, the formula is as follows:

[0116]

[0117] in, K represents the noise level of the piezoresistive sensing element, l represents the length of the piezoresistive sensing element, and K represents the noise level of the piezoresistive sensing element. b Boltzmann's constant, Where is the diffusion depth, w is the width of the piezoresistive sensitive cell, and f is the diffusion depth. max f is the upper limit of the operating frequency. min V is the lower limit of the operating frequency, and V is the bias voltage of the piezoresistive sensing element.

[0118] 4. Selecting an Optimization Scheme: Based on the calculation results of the above model, select an ion implantation process combination that meets the application requirements in terms of indicators (such as temperature coefficient of resistance, temperature coefficient of sensitivity, sensitivity, and noise). In this example, the optimal ion implantation process combination is selected, which combines P-well implantation, P-type high-voltage lightly doped source-drain implantation, and high-resistivity polysilicon resistor implantation, to fabricate piezoresistive sensitive cells.

[0119] In addition to the combinations mentioned above, other process combinations can be selected according to different needs. For example, P-well implantation has the best sensitivity performance, while the combination of P-type high-voltage lightly doped source / drain implantation, P-type source / drain implantation, and P-type electrostatic discharge implantation has the best temperature coefficient performance.

[0120] S2: Select the substrate to be processed, such as Figure 1 As shown:

[0121] The crystal plane is selected as (100), and the Notch slot position orientation is the crystal direction. <110> A P-type single-crystal silicon substrate with a surface resistivity of 8.5–11.5 Ω·cm and a thickness of 725 μm was used as substrate 1.

[0122] S3: STI structure formation and planarization, such as Figure 2 As shown:

[0123] 1. Oxide and Silicon Nitride Deposition: A substrate oxide layer of silicon dioxide is grown on the surface of silicon substrate 1, with a thickness of [missing information]. The oxidation temperature is 900–1000℃. Subsequently, silicon nitride is deposited on the silicon wafer surface, with a deposition thickness of [missing information]. The deposition temperature is 700–800℃.

[0124] 2. Photolithography and masking: A mask is set on the surface of the silicon wafer to create the active area. Through photolithography, the areas used to manufacture the source / drain / channel, well contact, and piezoresistive sensitive cells of the MOS transistor are preserved.

[0125] 3. Etching and trench formation: Etching is performed on the non-active regions of silicon nitride, silicon dioxide, and silicon substrate to form the desired trench structure.

[0126] 4. Thermal oxidation repair: After trench etching, thermal oxidation growth is performed to form a new substrate oxide layer, which is used to repair the damage to the trench edge surface during the etching process.

[0127] 5. Trench Filling and Planarization: High-density plasma-enhanced chemical vapor deposition (HDPCVD) is used to deposit silicon oxide to fill the trenches. Next, chemical mechanical polishing (CMP) is used to remove excess silicon oxide and silicon nitride from the surface, achieving global planarization and ensuring a smooth surface. After this step, an STI (Shallow Trench Isolation) structure is formed, isolating devices on both sides of the trench.

[0128] S4: Surface treatment and trap formation, such as Figure 3 As shown:

[0129] 1. Silicon wafer cleaning and oxide layer growth: After cleaning the silicon wafer surface, a sacrificial oxide layer, silicon dioxide 3, is grown. The thickness of this oxide layer is [missing information]. The oxidation temperature is 900–1000℃. The main function of this oxide layer is to repair substrate surface damage caused by chemical mechanical polishing (CMP), prevent direct contact between photoresist and substrate, avoid contamination, and prevent channeling effects during subsequent ion implantation.

[0130] 2. Masks and photolithography: Masks are set on the surface of the silicon wafer, specifically including N-well injection mask, deep N-well injection mask, and P-well injection mask, for photolithography applied to N-well injection, deep N-well injection, and P-well injection.

[0131] 3. Ion Implantation: Ion implantation processes are performed after photolithography to form N-well 5, deep N-well 4, P-well 6, and piezoresistive sensing element 7. The P-well implantation 8 uses boron, indium, and boron as impurities, with specific implantation energies and doses as follows:

[0132] Boron: Implantation energy 150-200 keV, implantation dose 10 13 ~10 14 cm -2 ;

[0133] Indium: Implantation energy 150–200 keV, implantation dose 10 12 ~10 13 cm -2 ;

[0134] Boron: Injection energy 20-50 keV, injection dose 10 12 ~10 13 cm -2 .

[0135] 4. Device Isolation and Piezoresistive Cell Fabrication: A PMOS device is fabricated in N-well 5, and an NMOS device is fabricated in P-well 6, forming a PN junction for isolation and ensuring electrical isolation between devices. The mask for P-well injection 8 includes the pattern of the piezoresistive cell. The piezoresistive cell 7 is fabricated simultaneously with P-well 6. Both the fully isolated NMOS transistor and the piezoresistive cell 7 are located in the deep N-well 4 region.

[0136] 5. Rapid Thermal Annealing: After implantation, rapid thermal annealing (RTA) is performed at a temperature of 900–1200℃ for 8–15 seconds. The main purpose of the annealing process is to activate the implanted impurity ions and repair lattice damage caused by ion implantation.

[0137] S5: Gate formation and lightly doped source / drain implantation, such as Figure 4 As shown:

[0138] 1. Removal of sacrificial oxide layer and cleaning of silicon wafer: Wet etching is used to remove the sacrificial oxide layer on the surface, and then the silicon wafer is thoroughly cleaned to remove surface impurities.

[0139] 2. Gate oxide layer growth and polysilicon deposition: A first oxidation process is performed on the silicon wafer surface, involving photolithography and etching to define a thin gate oxide region. A second oxidation process is then performed to grow the thick gate oxide layer 14 of the high-voltage MOS transistor. and the thin gate oxide layer of low-voltage MOS transistors Then, polycrystalline silicon is deposited with a thickness of [thickness value missing]. The deposition temperature is 600–700℃.

[0140] 3. Polysilicon Gate Photolithography and Etching: A mask for the polysilicon gate 9 is placed on the silicon wafer surface. Photolithography is performed to etch away the polysilicon in the non-CMOS device gate and polysilicon resistor regions. After etching and removing the resist, the silicon substrate and polysilicon are re-oxidized to form a thin oxide layer. This thin oxide layer repairs the damage to the gate oxide layer caused during etching and prevents channeling effects during subsequent ion implantation. Finally, the polysilicon gate 9 is formed.

[0141] 4. Lightly Doped Source / Drain Implantation Process: The following ion implantation masks are prepared on the silicon wafer surface: N-type low-voltage lightly doped source / drain implantation mask, N-type high-voltage lightly doped source / drain implantation mask, P-type low-voltage lightly doped source / drain implantation mask, and P-type high-voltage lightly doped source / drain implantation mask. Photolithography is performed on each mask, and through each ion implantation process, N-type lightly doped source / drain 10, P-type lightly doped source / drain 11, lightly doped connection region 12, and piezoresistive sensing unit 7 are formed. The lightly doped connection region 12 is used to connect the piezoresistive sensing unit 7 to the metal interconnect layer 28. This step helps to: reduce the peak electric field in the drain region, weaken the hot carrier injection effect, and improve device reliability.

[0142] 5. Rapid thermal annealing: The silicon wafer undergoes rapid thermal annealing at a temperature of 900–1000℃ for 8–15 seconds. The annealing process primarily activates the implanted impurity ions and simultaneously repairs lattice damage caused by ion implantation.

[0143] 6. Ion Implantation and Piezoresistive Sensing Cell Fabrication: During P-type high-voltage lightly doped source-drain implantation 13, the mask includes a pattern of piezoresistive sensing cells. Impurity ions are simultaneously implanted into the piezoresistive sensing cell 7. The implanted impurity is boron fluoride, the implantation energy is 20–50 keV, and the implantation dose is 10. 13 ~10 14 cm -2 .

[0144] S6: Source / drain implantation and heavily doped junction formation, such as Figure 5 As shown:

[0145] 1. Silicon Wafer Cleaning and Dielectric Layer Deposition: After cleaning the silicon wafer, silicon oxide, silicon nitride, and silicon oxide are deposited sequentially using low-pressure chemical vapor deposition (LPCVD) to form a composite dielectric layer. Anisotropic dry etching is then used to etch the composite dielectric layer surrounding the polysilicon gate 9, forming sidewalls 15. The function of these sidewalls 15 is to prevent the influence of subsequent source / drain ion implantation on the lightly doped source / drain regions, ensuring the accuracy of the implanted region.

[0146] 2. Source / Drain Region Photolithography and Implantation: The following ion implantation masks are prepared on the silicon wafer surface: N-type source / drain implantation mask and P-type source / drain implantation mask. Through various photolithography and ion implantation processes, N-type source / drain 16 and N-well contact region 21, and P-type source / drain 17 and P-well contact region 20 are formed, respectively. The purpose of forming these regions is to: increase the surface doping concentration to reduce the on-line series resistance; and reduce the concentration gradient between the implanted region and the well, thereby reducing leakage current.

[0147] 3. Rapid thermal annealing: The silicon wafer is subjected to rapid thermal annealing at 1000-1100℃ for 20-30 seconds. This step is used to activate the implanted impurity ions and repair the lattice damage caused during ion implantation.

[0148] 4. P-type source / drain implantation and heavily doped connection region formation: During P-type source / drain implantation 19, impurity ions are simultaneously implanted into the heavily doped connection region 18. The piezoresistive sensing unit 7 and the metal interconnect layer 28 are connected through the heavily doped connection region 18, reducing the series resistance and ensuring the transmission of electrical signals. The heavily doped connection region on the surface of the high-resistance polysilicon resistor 23 is used to form an ohmic contact, reducing the series resistance between the high-resistance polysilicon resistor 23 and the metal interconnect layer 28. The implanted impurity is boron, the implantation energy is 5–20 keV and 20–50 keV, and the implantation dose is 10. 15 ~1016 cm -2 10 13 ~10 14 cm -2 .

[0149] S7: Fabrication of high-resistivity polysilicon resistive implantation, electrostatic discharge implantation, and piezoresistive sensitive cells, such as... Figure 6 As shown:

[0150] 1. Silicon wafer cleaning: Clean the silicon wafer to remove surface impurities and prepare it for subsequent processes.

[0151] 2. Mask and Photolithography: A high-resistance polysilicon resistor implantation mask is set on the silicon wafer surface, photolithography is performed, and then high-resistance polysilicon resistor implantation 22 is performed to form a high-resistance polysilicon resistor 23. An electrostatic discharge (ESD) implantation mask is set on the silicon wafer surface, photolithography is performed, and then ESD implantation is performed to implant boron into the interface between the drain active region and the P-well of the ESD NMOS transistor 24. This makes the breakdown voltage of the PN junction at this interface lower than the tip breakdown voltage of the lightly doped source-drain region, thereby protecting the tip of the lightly doped source-drain region. At the same time, it also reduces the quick-return voltage of the ESD NMOS transistor 24, allowing its parasitic transistor to turn on and discharge static electricity at a lower voltage, improving the performance of the ESD NMOS transistor 24 and enhancing the CMOS circuit's ability to resist ESD.

[0152] 3. Ion Implantation and Piezoresistive Sensing Cell Fabrication: During high-resistivity polycrystalline silicon resistor implantation 22, the mask includes the pattern of the piezoresistive sensing cell. Impurity ions are simultaneously implanted into the piezoresistive sensing cell 7. The implanted impurity is boron fluoride, the implantation energy is 20–50 keV, and the implantation dose is 10. 14 ~10 15 cm -2 .

[0153] S8: Metal silicide formation and metal interconnect layer fabrication, such as Figure 7 As shown:

[0154] 1. Silicon wafer cleaning: First, the silicon wafer is cleaned to remove surface impurities and prepare it for subsequent processes.

[0155] 2. Deposition of silicon-rich oxide barrier layer: A silicon-rich oxide layer is deposited on the silicon wafer surface using plasma chemical vapor deposition (PECVD) as a metal silicide barrier layer 25 (SAB).

[0156] 3. Photolithography and Metal Silicate Barrier Mask: A mask is used to deposit a metal silicide barrier layer 25 on the surface of the silicon wafer. Through photolithography, the mask covers areas where metal silicide formation is not desired, protecting the silicon wafer surface.

[0157] 4. Cobalt Metal Deposition and Annealing: A layer of metallic cobalt is deposited on the silicon wafer surface using physical vapor deposition (PVD). This is followed by two rapid annealing processes.

[0158] First annealing: Annealing temperature is 500-600℃, annealing time is 30-40 seconds.

[0159] Second annealing: Annealing temperature is 800-900℃, annealing time is 30-40 seconds.

[0160] Annealing allows cobalt to react with the silicon surface to form cobalt silicide 26 (CoSi2), reducing the series resistance of the active region.

[0161] 5. Wet etching: Wet etching is performed on the surface of the silicon wafer to remove the area not protected by the metal silicide barrier layer 25, thus completing the formation of cobalt silicide 26.

[0162] 6. Deposition of dielectric and passivation layers: Dielectric and passivation layers of different materials are deposited using processes such as PECVD, SACVD (sub-atmospheric chemical vapor deposition), and HDPCVD, including: silicon oxynitride (SiON), borosilicate glass (BPTEOS), silicon dioxide (TEOS source), fluorosilicone glass (FSG), undoped silicon glass (FSG), and silicon nitride (Si3N4).

[0163] 7. Formation and Filling of Vias: A mask for vias 27 is formed on the silicon wafer surface, and the via areas are positioned using photolithography. The dielectric and passivation layers in the via areas are removed using etching to form vias 27, which are then filled with deposited tungsten. The tungsten surface is planarized using chemical mechanical polishing (CMP) to ensure a smooth surface.

[0164] 8. Deposition and Etching of Metal Interconnect Layers: An aluminum-copper alloy (Al-0.5% Cu) is deposited on the silicon wafer surface as the metal interconnect layer 28. The metal interconnect layer 28 is planarized using CMP to ensure good electrical connectivity. Photolithography and etching are performed to pattern the first metal interconnect layer, followed by the deposition of a dielectric layer and a passivation layer.

[0165] 9. Complete the metal interconnect and final structure: After repeated deposition of dielectric and passivation layers, formation and filling of vias, deposition and etching of metal interconnect layers, and CMP processing, three layers of metal interconnect, dielectric and passivation layers are finally formed, completing the fabrication of a monolithic integrated CMOS piezoresistive chip.

[0166] Since piezoresistive sensitive cells are not standard cells in the Process Design Kit (PDK), the mask patterns used in some ion implantation processes cannot be directly generated by the user in the layout design software. Therefore, the layout generation rules of the PDK need to be appropriately utilized or modified. For example, the pattern on the P-well implantation mask can be obtained by taking the logical NOT of the N-well implantation layout, thus eliminating the need to draw the N-well implantation layout in the piezoresistive sensitive cell region. For the pattern on the P-type high-voltage, low-doped source-drain implantation mask, it is generated through mathematical operations using the layouts of P-type source-drain implantation, polysilicon gate, and other processes. In other words, the P-type high-voltage, low-doped source-drain implantation process in the CMOS circuit region does not require drawing the layout of this layer separately to generate the corresponding pattern on the mask. However, in the piezoresistive sensitive cell region, if the P-type high-voltage, low-doped source-drain implantation process is required, the drawn P-type high-voltage, low-doped source-drain implantation layout must be added to the mathematical operations to generate the corresponding pattern on the P-type high-voltage, low-doped source-drain implantation mask, completing the ion implantation.

[0167] This concludes the description of the relevant process steps in the manufacturing method of the piezoresistive chip for monolithic integrated CMOS circuits in this embodiment of the invention. In addition to the steps described above, the manufacturing method of this embodiment can also add other process steps unrelated to the fabrication of the piezoresistive sensing unit between or within each step. These steps can be implemented using processes commonly used in current production lines, and specific details will not be elaborated here. Furthermore, based on different standard CMOS process nodes (such as 0.35μm, 0.25μm, 0.13μm, 0.11μm, etc.), the types of ion implantation processes will differ, thus affecting the ion implantation combinations of the piezoresistive sensing units that can be formed, and consequently leading to changes in the specific process steps of the above method. However, by utilizing or modifying the layout generation rules, it is still possible to manufacture piezoresistive sensing units, and specific details will also not be elaborated here.

[0168] This invention proposes a method for manufacturing a monolithically integrated CMOS piezoresistive chip. Based on a standard CMOS process production line, it effectively utilizes or appropriately modifies the layout generation rules of some ion implantation processes to form the mask pattern required for fabricating piezoresistive sensitive units. By combining multiple ion implantation processes, piezoresistive sensitive units with different performance indicators can be manufactured, thereby meeting the needs of piezoresistive chips in different application scenarios. This method has low R&D costs and can be widely applied to the production of piezoresistive chips, meeting the year-on-year growth in market demand.

[0169] The above embodiments are merely illustrative of the technical solutions of the present invention and are not intended to limit the scope of the invention. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A method for manufacturing a piezoresistive chip for a monolithic integrated CMOS circuit, characterized in that, Includes the following steps: 1)Perform performance simulation of piezoresistive sensitive units fabricated by different ion implantation process combinations, analyze the temperature coefficient of resistance, temperature coefficient of sensitivity, sensitivity and noise parameters, and select the ion implantation process combination that meets the application requirements. 2) Select a silicon wafer as the substrate; 3) A silicon dioxide oxide layer is grown on the surface of a silicon wafer, silicon nitride is deposited, and trenches are formed by photolithography and etching. After filling the trenches, planarization is performed to form an STI structure. 4) A sacrificial oxide layer of silicon dioxide is grown on the surface of the silicon wafer. After photolithography, N-well implantation, P-well implantation and deep N-well implantation are performed to form N-well, P-well and deep N-well. If the selected ion implantation process combination includes one or more of N-well implantation, P-well implantation, and deep N-well implantation, the selected ion implantation process is used simultaneously to implant the region forming the piezoresistive sensitive cell; after all processes are completed, rapid thermal annealing is performed. 5) Remove the sacrificial oxide layer from the silicon wafer surface, grow the gate oxide layer and deposit polysilicon, and form the polysilicon gate through photolithography and etching; after photolithography, perform N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, P-type low-voltage lightly doped source / drain implantation, and P-type high-voltage lightly doped source / drain implantation to form the lightly doped source / drain region of the MOS device, as well as the lightly doped connection region for connecting the piezoresistive sensitive cell to the metal interconnect layer; if the selected ion implantation process combination includes one or more of N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, P-type low-voltage lightly doped source / drain implantation, and P-type high-voltage lightly doped source / drain implantation, the selected ion implantation process is also used to implant the region forming the piezoresistive sensitive cell; after all are completed, perform rapid thermal annealing; 6) A composite dielectric layer is deposited on the silicon wafer surface, and sidewalls surrounding the polysilicon gate are etched. After photolithography, N-type source / drain, P-type source / drain, trap contact region, and heavily doped connection region are formed by N-type source / drain implantation and P-type source / drain implantation. If the selected ion implantation process combination includes one or both of N-type and P-type source / drain implantation, the selected ion implantation process is also used to implant the region forming the piezoresistive sensitive cell. After all is completed, rapid thermal annealing is performed. 7) Perform photolithography and implant high-resistance polysilicon resistors through high-resistance polysilicon resistors to form high-impedance polysilicon resistors; Photolithography is performed, and electrostatic discharge (ESD) injection is used to form an ESD NMOS transistor. If the selected ion implantation process combination includes one or both of high-resistivity polysilicon resistive implantation and electrostatic discharge implantation, the selected ion implantation process is used simultaneously to implant the region forming the piezoresistive sensitive cell. 8) A metal silicide barrier layer is deposited on the silicon wafer surface. The protected area is then masked by photolithography and etching. A layer of cobalt metal is then deposited on the silicon wafer surface. After two rapid annealing processes, cobalt silicide is formed in the areas not protected by the metal silicide barrier layer. A dielectric layer and a passivation layer are deposited on the silicon wafer surface and planarized. Vias are formed by photolithography and etching. Tungsten metal is then filled into the vias and planarized. A metal interconnect layer is then deposited on the silicon wafer surface and photolithography and etching are performed. The dielectric layer and passivation layer are then deposited again. This process is repeated to form multiple layers of metal interconnect layers, dielectric layers, and passivation layers, ultimately completing the fabrication of a monolithic integrated CMOS piezoresistive chip.

2. The manufacturing method as described in claim 1, characterized in that, Step 1) includes one or more of the following ion implantation processes: P-type ion implantation and N-type ion implantation. P-type ion implantation includes P-well implantation, P-type low-voltage lightly doped source / drain implantation, P-type high-voltage lightly doped source / drain implantation, P-type source / drain implantation, electrostatic discharge implantation, and high-resistance polysilicon resistor implantation. N-type ion implantation includes N-well implantation, deep N-well implantation, N-type low-voltage lightly doped source / drain implantation, N-type high-voltage lightly doped source / drain implantation, and N-type source / drain implantation.

3. The manufacturing method as described in claim 1, characterized in that, Step 1) involves analyzing the temperature coefficient of resistance, temperature coefficient of sensitivity, sensitivity, and noise parameters, including: The doping concentration distribution of piezoresistive sensitive cells under different combinations of ion implantation processes was simulated using process simulation tools. The average longitudinal and transverse stress difference distribution on the surface of the piezoresistive sensitive element was simulated and calculated using finite element analysis tools. Substituting the doping concentration distribution and the average longitudinal and transverse stress difference distribution into the resistance temperature coefficient model, sensitivity temperature coefficient model, sensitivity model, and noise model, the resistance temperature coefficient, sensitivity temperature coefficient, sensitivity, and noise parameters are calculated.

4. The manufacturing method as described in claim 1, characterized in that, Step 3) involves forming trenches through photolithography and etching, including: setting a mask on the silicon wafer surface for fabricating the active region; retaining the areas for fabricating the source / drain / channel, well contact, and piezoresistive sensitive cell of the MOS transistor through photolithography; and etching the silicon nitride, silicon dioxide, and silicon substrate in the non-active region to form trenches. High-density plasma chemical vapor deposition technology is used to deposit silicon oxide to fill the trenches; then, a chemical mechanical polishing process is used to remove excess silicon oxide and silicon nitride from the surface, achieving global planarization.

5. The manufacturing method as described in claim 1, characterized in that, In step 4), a PMOS device is fabricated in the N-well, and an NMOS device is fabricated in the P-well to form a PN junction for isolation. During N-well implantation, impurities phosphorus, phosphorus, and arsenic are implanted sequentially, with implantation energies and doses as follows: Phosphorus: Injection energy 400-450 keV, injection dose 10 13 ~10 14 cm -2 ; Phosphorus: Injection energy 150-200 keV, injection dose 10 12 ~10 13 cm -2 ; Arsenic: Injection energy 150-200 keV, injection dose 10 13 ~10 14 cm -2 ; During deep N-well implantation, impurity phosphorus is injected twice, with the following injection energies and doses: Phosphorus: Injection energy 1500-2000 keV, injection dose 10 13 ~10 14 cm -2 ; Phosphorus: Injection energy 500-1000 keV, injection dose 10 12 ~10 13 cm -2 ; During P-well implantation, impurities boron, indium, and boron are implanted sequentially, with implantation energies and doses as follows: Boron: Implantation energy 150-200 keV, implantation dose 10 13 ~10 14 cm -2 ; Indium: Implantation energy 150–200 keV, implantation dose 10 12 ~10 13 cm -2 ; Boron: Injection energy 20-50 keV, injection dose 10 12 ~10 13 cm -2 .

6. The manufacturing method as described in claim 1, characterized in that, In step 5), wet etching is used to remove the sacrificial oxide layer on the surface; a first oxidation process is performed on the silicon wafer surface, followed by photolithography and etching to define the thin gate oxide region, and then a second oxidation process is performed to grow the thick gate oxide layer of the high voltage MOS transistor and the thin gate oxide layer of the low voltage MOS transistor. The steps of forming a polysilicon gate by photolithography and etching include: setting a mask for the polysilicon gate on the surface of a silicon wafer, performing photolithography, and etching away the polysilicon of the non-CMOS device gate and the polysilicon resistor region; After etching to remove the resist, the silicon wafer and polysilicon are re-oxidized to form a thin oxide layer, which ultimately forms the polysilicon gate.

7. The manufacturing method as described in claim 1, characterized in that, In step 5), during the N-type low-voltage lightly doped source / drain implantation, indium and arsenic impurities are implanted sequentially, with implantation energies and doses as follows: Indium: Implantation energy 150–200 keV, implantation dose 10 13 ~10 14 cm -2 ; Arsenic: Injection energy 5-20 keV, injection dose 10 14 ~10 15 cm -2 ; During N-type high-voltage, lightly doped source / drain implantation, phosphorus impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 13 ~10 14 cm -2 ; During P-type low-voltage lightly doped source-drain implantation, arsenic impurities and boron fluoride are implanted sequentially, with implantation energies and doses as follows: Arsenic: Injection energy 150-200 keV, injection dose 10 13 ~10 14 cm -2 ; Boron fluoride: Implantation energy 5–20 keV, implantation dose 10 14 ~10 15 cm -2 ; During P-type high-voltage, lightly doped source-drain implantation, boron fluoride impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 13 ~10 14 cm -2 .

8. The manufacturing method as described in claim 1, characterized in that, In step 6), a low-pressure chemical vapor deposition process is used to sequentially deposit silicon oxide, silicon nitride, and silicon oxide to form a composite dielectric layer; During N-type source / drain injection, impurities arsenic and phosphorus are injected sequentially, with the injection energy and dosage as follows: Arsenic: Injection energy 20-100 keV, injection dose 10 15 ~10 16 cm -2 ; Phosphorus: Injection energy 20-50 keV, injection dose 10 13 ~10 14 cm -2 ; During P-type source / drain implantation, impurity boron is injected twice, with the following injection energies and doses: Arsenic: Injection energy 5-20 keV, injection dose 10 15 ~10 16 cm -2 ; Phosphorus: Injection energy 20-50 keV, injection dose 10 13 ~10 14 cm -2 .

9. The manufacturing method as described in claim 1, characterized in that, Step 7) During high-resistance polycrystalline silicon resistor implantation, boron fluoride impurity is implanted at an implantation energy of 20–50 keV and an implantation dose of 10. 14 ~10 15 cm -2 During electrostatic discharge injection, the injected impurity is boron, the injection energy is 20–50 keV, and the injection dose is 10 times the injection dose. 13 ~10 14 cm -2 .

10. The manufacturing method as described in claim 1, characterized in that, In step 8), a silicon-rich oxide layer is deposited on the silicon wafer surface using plasma chemical vapor deposition as a metal silicide barrier layer; a layer of cobalt metal is deposited on the silicon wafer surface using physical vapor deposition; and the silicon wafer surface is subjected to dry etching and wet etching to remove areas not protected by the metal silicide barrier layer. Using one or more of the following processes: plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, and high-density plasma chemical vapor deposition, various materials such as silicon oxynitride, borosilicate glass, silicon dioxide, fluorosilicon glass, undoped silicon glass, and silicon nitride are deposited to form a dielectric layer and a passivation layer; the tungsten surface is planarized by chemical mechanical polishing. An aluminum-copper alloy is deposited on the surface of a silicon wafer as a metal interconnect layer material, and the metal interconnect layer is planarized by a chemical mechanical polishing process. The number of metal interconnect layers is 3, 4, 5 or 6.

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