Etching method of passivation layer

Abstract

The invention discloses an etching method of a passivation layer, and the method comprises the steps: forming the passivation layer on a metal layer, the metal layer being formed in an interlayer dielectric layer, the interlayer dielectric layer being formed on a substrate, and the substrate being used for forming a semiconductor device; covering the passivation layer with a light resistor, and removing the light resistor in the target region through exposure and development in sequence to expose the passivation layer in the target region; wet etching is carried out, so that the passivation layer of the target area is thinned; and performing dry etching until the metal layer of the target area is exposed. After the passivation layer on the metal layer is covered with the light resistor, the target area is exposed through exposure and development in sequence, the passivation layer of the target area is removed through wet etching and dry etching in sequence, the metal layer of the target area is exposed, and therefore the appearance of the edge of the junction area of the exposed metal layer and the passivation layer is steeper, and the light resistance of the metal layer is improved. And the residue of the passivation layer is reduced, so that the phenomena of skip plating and falling of the subsequent electroplating metal layer are avoided.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for etching a passivation layer. Background Art

[0002] In the semiconductor integrated circuit manufacturing industry, the passivation layer is mainly used to electrically isolate between devices and wiring, and to isolate the device from the surrounding environment, so as to enhance the device's ability to block external pollution, to protect the interconnection inside the device, and to prevent mechanical and chemical damage. Taking the passivation layer of polyimide as an example, after the passivation layer of polyimide is formed on the top metal layer, a wet etching process is usually used to etch to open the top metal layer, and then chemical electroplating is performed on the exposed top metal layer to form a surface metal layer.

[0003] refer to Figure 1 , which shows a cross-sectional schematic diagram after a surface metal layer is formed on the top metal layer. Figure 1 As shown, a passivation layer 120 including polyimide is formed on the top metal layer 110 (which may include an aluminum (Al) layer), and the passivation layer 120 in the target area is removed by wet etching, so that chemical electroplating is performed on the exposed area to form a surface metal layer (which includes a nickel (Ni) layer 131, a palladium (Pd) layer 132 and a gold (Au) layer 133 in sequence from bottom to top), and polyimide residues (such as Figure 1 The area indicated by the dotted line in the middle will directly affect the deposition of the surface metal layer, causing local skipping of the plating (cracking of the plating). In more serious cases, the surface metal layer in the skipping area has low adhesion strength, which will eventually cause the plating to fall off, thereby affecting the reliability and yield of the product. Summary of the invention

[0004] The present application provides a passivation layer etching method, which can solve the problem that the edge morphology of the passivation layer after etching is relatively flat, which leads to the subsequent electroplating layer being prone to skip plating and falling off in the edge area. The method comprises:

[0005] forming a passivation layer on a metal layer, wherein the metal layer is formed in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a substrate, and wherein the substrate is used to form a semiconductor device;

[0006] Covering the passivation layer with a photoresist, and removing the photoresist in a target area by sequentially exposing and developing, so that the passivation layer in the target area is exposed;

[0007] Performing wet etching to thin the passivation layer in the target area;

[0008] Dry etching is performed until the metal layer in the target area is exposed.

[0009] In some embodiments, the passivation layer includes a polyimide layer.

[0010] In some embodiments, the metal layer includes an aluminum layer.

[0011] In some embodiments, after wet etching, the thickness of the passivation layer is 3 micrometers to 5 micrometers.

[0012] In some embodiments, after the dry etching, the method further includes:

[0013] A surface metal layer is formed on the exposed metal layer by a chemical plating process.

[0014] In some embodiments, the surface metal layer includes, from bottom to top, a nickel layer, a palladium layer, and a gold layer.

[0015] The technical solution of this application has at least the following advantages:

[0016] After covering the passivation layer on the metal layer with photoresist, the target area is exposed by exposure and development in sequence, and the passivation layer in the target area is removed by wet etching and dry etching in sequence to expose the metal layer in the target area. This makes the edge of the junction area between the exposed metal layer and the passivation layer steeper, reduces the residual passivation layer, and avoids the subsequent electroplating metal layer from skipping and falling off, thereby improving the reliability and yield of the product to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a cross-sectional schematic diagram of a passivation layer formed by etching using an etching method provided by related technologies;

[0019] Figure 2 is a flow chart of a method for etching a passivation layer provided by an exemplary embodiment of the present application;

[0020] Figures 3 to 7 is a schematic diagram of etching a passivation layer according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0025] refer to Figure 2 , which shows a flow chart of a method for etching a passivation layer provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes:

[0026] Step S1, forming a passivation layer on a metal layer, wherein the metal layer is formed in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a substrate, and the substrate is used to form a semiconductor device.

[0027] Step S2, covering the passivation layer with a photoresist, and removing the photoresist in the target area by sequentially performing exposure and development to expose the passivation layer in the target area.

[0028] refer to Figure 3 , which shows a cross-sectional schematic diagram after covering the passivation layer with photoresist; Figure 4 , which shows a cross-sectional schematic diagram after sequential exposure and development. Figure 3 and Figure 4 As shown, the metal layer 210 is formed in the inter-layer dielectric (ILD) layer ( Figure 3 ), an interlayer dielectric layer is formed on the substrate ( Figure 3 The substrate is used to form a semiconductor device. The metal layer 210 is a top metal pad for leading out the electrode of the semiconductor device, which may include an aluminum (Al) layer. The passivation layer 220 can be covered on the metal layer 210 by coating, and the photoresist 300 is covered on the passivation layer 220. After exposure and development in sequence, the photoresist 300 in the target area 301 is removed to expose the metal layer 210 in the target area 301.

[0029] Step S3, performing wet etching to thin the passivation layer in the target area.

[0030] refer to Figure 5 , which shows a cross-sectional schematic diagram after wet etching. Figure 5 As shown, after wet etching, since wet etching is isotropic etching, the morphology of the passivation layer 220 at the edge of the target area 301 is relatively flat. After the etching step, the thickness of the passivation layer 220 in the target area 301 is 3 microns (μm) to 5 microns (this thickness is the average thickness or general thickness of the passivation layer 220 in the target area 301, and the area with a flat edge morphology accounts for a small proportion in the target area).

[0031] Step S4, performing dry etching until the metal layer in the target area is exposed.

[0032] refer to Figure 6 , which shows a cross-sectional schematic diagram after dry etching; refer to Figure 7 , which shows a cross-sectional schematic diagram after the photoresist is removed. For example, Figure 6 and Figure 7 As shown in FIG, since dry etching is anisotropic etching, the etching rate can be concentrated in the normal direction of the substrate by controlling the etching conditions, making the morphology of the edge area steeper (such as Figure 7 After removing the photoresist, the wafer may be baked, and a surface metal layer may be formed on the exposed metal layer through a chemical plating process. The surface metal layer may include a nickel layer, a palladium layer, and a gold layer from bottom to top.

[0033] To summarize, in the embodiments of the present application, after covering the passivation layer on the metal layer with a photoresist, the target area is exposed by exposure and development in sequence, and the passivation layer of the target area is removed by wet etching and dry etching in sequence to expose the metal layer of the target area, thereby making the edge morphology of the junction area between the exposed metal layer and the passivation layer steeper, reducing the residual passivation layer, and thus avoiding the subsequent electroplating metal layer skipping and falling off phenomenon, thereby improving the reliability and yield of the product to a certain extent.

[0034] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for etching a passivation layer, characterized in that: include: forming a passivation layer on a metal layer, wherein the metal layer is formed in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a substrate, and wherein the substrate is used to form a semiconductor device; Covering the passivation layer with a photoresist, and removing the photoresist in a target area by sequentially exposing and developing, so that the passivation layer in the target area is exposed; Performing wet etching to thin the passivation layer in the target area; Dry etching is performed until the metal layer in the target area is exposed.

2. The method according to claim 1, characterized in that The passivation layer includes a polyimide layer.

3. The method according to claim 2, characterized in that The metal layer includes an aluminum layer.

4. The method according to claim 3, characterized in that After wet etching, the thickness of the passivation layer is 3 micrometers to 5 micrometers.

5. The method according to any one of claims 1 to 4, characterized in that: After the dry etching, the method further comprises: A surface metal layer is formed on the exposed metal layer by a chemical plating process.

6. The method according to claim 5, characterized in that The surface metal layer includes a nickel layer, a palladium layer and a gold layer in sequence from bottom to top.

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