Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, a silicon cap layer rich in impurity ions for inhibiting diffusion of cobalt, germanium and silicon is formed on a germanium-silicon source drain, and the silicon cap layer not only can react with subsequently deposited cobalt to form cobalt silicide, but also can be used as a barrier isolation layer, so that the performance of the semiconductor device is improved. Wherein the impurity ions can block diffusion channels among cobalt atoms, germanium atoms and silicon atoms, so that mutual excessive diffusion among the cobalt atoms, the germanium atoms and the silicon atoms under a high-temperature condition can be prevented, the formation of low-resistance-phase cobalt silicide is facilitated, the occurrence of cobalt silicide clusters on the germanium-silicon source drain can be inhibited in a subsequent high-temperature process, and the quality of the germanium-silicon source drain is improved. According to the manufacturing method, the thermal stability and resistance of the cobalt silicide in the high-temperature manufacturing process are guaranteed, the cobalt silicide is compatible with the germanium-silicon source drain, therefore, the cobalt silicide can replace nickel silicide to be suitable for manufacturing devices with technical nodes below 65 nm, the technical prejudice of application of the cobalt silicide is overcome, and finally the performance of the devices is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] The complementary metal oxide semiconductor (CMOS) process introduces SiGe (silicon germanium, a type of strained silicon) and adds a certain amount of germanium (Ge) to the source and drain silicon of the PMOS transistor to form silicon germanium to generate strain, which lengthens the bonds between silicon (Si) atoms, reduces the resistance to electron movement, and greatly improves the speed, power consumption and characteristic frequency of the PMOS transistor.

[0003] In addition, the CMOS process also introduces metal silicide onto the polysilicon gate, source region and drain region to simultaneously improve the equivalent series resistance of the gate, source and drain active regions of the transistor and the contact resistance of the contact hole. Usually, at process nodes with a feature size of 0.5μm to 0.25μm, titanium silicide (Ti-Salicide, the second annealing temperature is higher than 800°C) process technology is mostly used. At process nodes with a feature size of 0.18μm to 65nm, cobalt silicide (Co-Salicide) is mostly used to replace titanium silicide to effectively avoid the direct clustering of titanium silicide as the thickness decreases or the line width decreases, the large edge resistance, the bridging caused by the diffusion of silicon to the metal, and other problems; at process nodes with a feature size of 65nm and below, nickel silicide (Ni-Salicide, also including nickel platinum silicide) with an annealing temperature usually lower than 600°C is mostly used to replace cobalt silicide to avoid the line width effect of cobalt silicide, the need for a thermal budget of more than 700°C when forming silicide, and the poor compatibility of Co and SiGe.

[0004] However, some products with feature sizes of 65nm and below (such as MEMS products) require further high-temperature processes (such as high-temperature processes in metal interconnection processes) after nickel silicide is formed. Although nickel silicide has lower resistance, it is easy to diffuse (NiSi piping) under high-temperature processes and has poor thermal stability, which cannot meet manufacturing requirements.

[0005] Therefore, a new solution is needed to avoid the above disadvantages. Summary of the invention

[0006] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can enable cobalt silicide to be applied to a CMOS process that introduces germanium-silicon source and drain, and improve the problem of cobalt silicide clusters on the germanium-silicon source and drain, so that cobalt silicide is compatible with the germanium-silicon source and drain, and ensure the thermal stability and resistance of cobalt silicide in a high-temperature process.

[0007] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] providing a substrate, and forming a gate on the substrate;

[0009] Etching the substrate on both sides of the gate to form source and drain trenches;

[0010] epitaxially growing a silicon germanium source and drain in the source and drain trench;

[0011] Epitaxially growing a silicon cap layer on the germanium silicon source and drain, wherein the silicon cap layer is rich in impurity ions for inhibiting diffusion of cobalt, germanium and silicon;

[0012] Cobalt is deposited on the silicon cap layer, and a first rapid thermal annealing at a lower temperature and a second rapid thermal annealing at a higher temperature are performed, so that the silicon cap layer reacts with the deposited cobalt and undergoes a crystal phase transformation to form a desired cobalt silicide.

[0013] Optionally, the impurity ions include at least one of B, C, and As.

[0014] Optionally, the step of forming the silicon capping layer rich in the impurity ions on the silicon germanium source and drain comprises: epitaxially growing a silicon capping layer on the silicon germanium source and drain; and implanting the impurity ions into the silicon capping layer;

[0015] Alternatively, the step of forming the silicon capping layer rich in the impurity ions on the silicon germanium source and drain comprises: epitaxially growing the silicon capping layer on the silicon germanium source and drain, and in-situ doping the impurity ions during the epitaxial growth of the silicon capping layer.

[0016] Optionally, the implantation angle of the impurity ions is 15° to 30°; and / or the implantation depth of the impurity ions is half of the thickness of the formed cobalt silicide.

[0017] Optionally, before the impurity ions are injected into the silicon cap layer, a protective layer is first formed on the silicon cap layer; and / or a gate sidewall is also formed on the side wall of the gate; during the process of injecting the impurity ions into the silicon cap layer, the injection of the impurity ions also etches the surface of the gate sidewall to trim the surface morphology of the gate sidewall or thin the gate sidewall.

[0018] Optionally, while the silicon capping layer rich in the impurity ions is formed on the silicon germanium source and drain, a gate capping layer rich in the impurity ions is also synchronously formed on the top of the gate, wherein the gate capping layer is a film layer epitaxially grown on the top of the gate or is formed by doping the upper part of the gate with the impurity ions.

[0019] Optionally, the doping concentration of the impurity ions is 1E8 atoms / cm2 to 1E18 atoms / cm2; and / or the thickness of the silicon cap layer is

[0020] Optionally, the doping concentration of the impurity ions is 1E14 atoms / cm2 to 1E16 atoms / cm2, and / or the thickness of the silicon cap layer is

[0021] Optionally, the content of the impurity ions in the upper portion of the silicon capping layer is less than the content of the impurity ions in the lower portion of the silicon capping layer.

[0022] Optionally, there is no germanium in the upper portion of the silicon capping layer.

[0023] Compared with the prior art, the technical solution of the present invention forms a silicon cap layer rich in impurity ions for inhibiting the diffusion of cobalt, germanium and silicon on the germanium silicon source and drain. The silicon cap layer can not only react with the subsequently deposited cobalt to form cobalt silicide, but also serve as a blocking isolation layer to use the impurity ions doped therein to block and cut off the diffusion channels between the three atoms of cobalt, germanium and silicon, thereby preventing the excessive diffusion of the three atoms of cobalt, germanium and silicon under high temperature conditions, thereby facilitating the formation of low-resistance cobalt silicide and inhibiting the diffusion of cobalt, germanium and silicon in the subsequent high-temperature process. The occurrence of cobalt silicide clusters on the germanium silicon source and drain is improved and avoided, the line width effect of cobalt silicide is avoided, the thermal stability and resistance of cobalt silicide in high-temperature processes are guaranteed, and cobalt silicide is made compatible with germanium silicon source and drain. As a result, it can replace nickel silicide and be suitable for device manufacturing at technology nodes below 65nm, solving the problem that nickel silicide cannot meet manufacturing needs due to its easy diffusion and poor thermal stability under high-temperature processes, and overcomes the technical prejudice that cobalt silicide cannot be used in device manufacturing at technology nodes below 65nm, ultimately improving the performance of these devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 The figure is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] FIG. 2A to FIG. 2E It is a schematic cross-sectional view of a device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Figure 3 It is a schematic cross-sectional view of a device in a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0028] Figure 4 It is a schematic cross-sectional view of a device in a method for manufacturing a semiconductor device according to yet another embodiment of the present invention. DETAILED DESCRIPTION

[0029] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0032] S1, providing a substrate, and forming a gate on the substrate;

[0033] S2, etching the substrate on both sides of the gate to form source and drain trenches;

[0034] S3, epitaxially growing a silicon germanium source and drain in the source and drain trench;

[0035] S4, forming a silicon capping layer on the silicon-germanium source and drain, wherein the silicon capping layer is rich in impurity ions for inhibiting diffusion of cobalt, germanium and silicon;

[0036] S5, depositing cobalt on the silicon cap layer, and performing a first rapid thermal annealing at a lower temperature and a second rapid thermal annealing at a higher temperature, so that the silicon cap layer reacts with the deposited cobalt and undergoes a crystal phase transformation to form a desired cobalt silicide.

[0037] In step S1, the steps of providing a substrate 100 and forming a gate 103 on the substrate 100 include:

[0038] First, please refer to Figure 2A The substrate 100 is provided by selecting a substrate material in accordance with the device application requirements, such as single crystal silicon (Si), silicon on insulator (SOI), single crystal germanium (Ge), germanium on insulator (GeOI), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), etc. A shallow trench isolation structure (not shown) is further formed in the substrate 100 through a shallow trench isolation process (including shallow trench lithography, etching, and filling of insulating materials) to define a PMOS region and an NMOS region in the substrate 100, wherein Figures 2A to 3 Only one PMOS region is shown in the figure, but in fact, multiple PMOS regions and multiple NMOS regions can be formed in the substrate according to the layout design requirements. An N-type well region (not shown) can also be formed in the substrate 100 of the PMOS region, and a P-type well region (not shown) can also be formed in the substrate 100 of the NMOS region.

[0039] Next, please refer to Figure 2A , a gate oxide layer 102 is sequentially covered on the entire surface of the substrate 100 including the shallow trench isolation structure, and a gate layer and a hard mask layer 104 are deposited. The gate oxide layer 102 can be formed by a thermal oxidation process or a chemical vapor deposition process, and can be silicon dioxide, silicon oxynitride, silicon nitride, or a high-K material (such as hafnium-based oxide, etc.) with a dielectric constant K higher than that of silicon dioxide, and a combination thereof, and the material of the gate layer can be polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous germanium, and a combination thereof. The hard mask layer 104 can be silicon nitride or silicon oxynitride, and a combination thereof, and the like.

[0040] Then, please refer to Figure 2A , photolithography is performed with the help of a mask (not shown) used to manufacture the gate (including depositing an amorphous carbon layer and a bottom anti-reflective layer BARC, coating a photoresist PR, etc., and exposing and developing, etching the bottom anti-reflective layer BARC and the amorphous carbon layer, etc.), and the hard mask layer 104 is further etched, and then the film layers such as the photoresist are removed, and the gate layer and the gate oxide layer 102 are etched using the hard mask layer 104 remaining after etching as a mask to form a gate 103 on the substrate. At this time, there is a remaining hard mask layer 104 on the top of the gate 103.

[0041] Next, any suitable deposition process such as an atomic layer deposition process or a chemical vapor deposition process can be used to conformally deposit the sidewall material on the gate oxide layer 102, the sidewalls of each gate 103 and the exposed substrate 200, and form gate sidewalls on the sidewalls of each gate 103 through various sidewall etching processes. The gate sidewall can be a single-layer film structure or a multi-layer film structure formed by different sidewall materials. For example, the gate sidewall includes an inner sidewall 105a and an outer sidewall 105b formed by two different sidewall materials. The inner sidewall 105a can be made of silicon oxide or the like, and the outer sidewall 105b can be made of silicon nitride or the like.

[0042] It should be understood that in step S1, before forming the shallow trench isolation structure, a liner oxide layer (not shown) is first formed on the substrate 100 to protect the surface of the corresponding area of ​​the substrate 100 from being damaged in subsequent processes. After forming the gate sidewall, the exposed surface of the substrate 100 may be covered with the remaining liner oxide layer as a protective layer 101. Alternatively, after forming the gate sidewall, the exposed surface of the substrate 100 is oxidized to form the protective layer 101, or, after forming the gate sidewall, the protective layer 101 is formed by a deposition process to protect the surface of the corresponding area of ​​the substrate 100 from being damaged in subsequent processes.

[0043] In step S2, please refer to Figure 2A , an amorphous carbon layer (not shown) and a bottom anti-reflective layer BARC (not shown) can be deposited, a photoresist PR (not shown) can be coated, and photolithography processes such as exposure and development can be performed. The photoresist layer after photolithography is used as a mask to etch the bottom anti-reflective layer BARC, the amorphous carbon layer, and the protective layer 101 and the substrate 100 on both sides of the gate 103 to form source-drain grooves 106 in the substrate 100. At this time, the remaining protective layer 101 on the substrate 100 outside the source-drain grooves 106 is used to prevent silicon germanium from being formed on the substrate surface in these areas when silicon germanium is epitaxially grown later.

[0044] In step S3, please refer to Figure 2B, the patterned photoresist layer, the bottom anti-reflective layer BARC and the amorphous carbon layer (not shown) are removed by any suitable process such as a wet stripping process. Then, any suitable germanium silicon epitaxial growth process is used to epitaxially grow germanium silicon in the source and drain grooves 106 to form the germanium silicon source and drain 107 required for the PMOS transistor. The germanium silicon source and drain 107 can fill the source and drain grooves 106, and the top surface of the germanium silicon source and drain 107 is substantially flush with the top surface of the surrounding substrate 100, or the top surface of the germanium silicon source and drain 107 is slightly lower or slightly higher than the top surface of the surrounding substrate 100. Among them, the higher the germanium content in the germanium silicon source and drain 107, the greater the compressive stress introduced in the device, and the more significant the effect of improving the hole channel mobility of the PMOS device. Optionally, the top of the silicon cap layer 108 is higher than the top of the surrounding substrate 200.

[0045] During this process, since the substrate surface of the NMOS region and the substrate surfaces of other areas of the PMOS region are masked by the remaining protective layer 101 and gate 103 and other film layers, the top of each gate 103 is masked by the hard mask layer 104, and the side walls of each gate 103 are masked by the gate sidewalls, silicon germanium will not grow.

[0046] Optionally, in step S3, while epitaxially growing the silicon germanium source and drain 107 in the source and drain grooves 106, in-situ doping of P-type ions such as boron B, aluminum Al, gallium Ga, and indium In is performed, so that the formed silicon germanium source and drain can serve as the P-type ion-doped source and drain region required by the PMOS region (not shown); or, after executing step S3 and before executing step S4, or after executing step S4 and before executing step S5, P-type ions such as boron B, aluminum Al, gallium Ga, and indium In are used to perform P-type ion implantation on the corresponding thickness of the top of the silicon germanium source and drain 107 to form the P-type ion-doped source and drain region required by the PMOS region (not shown), and the P-type ion-doped source and drain region can effectively reduce the source-drain contact resistance of the PMOS region, and at the same time can also apply stress to the channel of the PMOS region to increase the hole carrier mobility.

[0047] In step S4, please refer to FIG. 2B to FIG. 2D , an epitaxial growth process combined with an ion implantation process can be used to form a silicon cap layer 108b rich in impurity ions such as B for inhibiting the diffusion of cobalt, germanium, and silicon. The specific process includes:

[0048] First, please refer to Figure 2B Any suitable epitaxial growth process can be used to epitaxially grow a silicon cap layer 108 on the top surface of the germanium silicon source and drain 107. The upper part of the silicon cap layer 108 does not contain germanium to prevent clustering problems when cobalt silicide is subsequently formed.

[0049] Then, please continue to refer to Figure 2B, the top surface of the silicon cap layer 108 can be subjected to thermal oxidation or other treatments in an ozone environment to form a protective layer (not shown). The protective layer can ensure that subsequent impurity ion implantation is more uniform, while reducing ion implantation damage on the surface of the silicon cap layer 108. On the other hand, it can also prevent the silicon cap layer 108 of the germanium silicon source and drain from being damaged in the subsequent process of removing the hard mask layer 103 on the top of the gate 103. In other embodiments of the present invention, the protective layer can also be replaced with an amorphous material, or when inclined ion implantation is used, the formation of the protective layer can be omitted.

[0050] Next, please refer to Figure 2C , remove the hard mask layer 104 on the top of the gate 103 by any suitable process such as dry etching or wet etching to expose the top surface of the gate 103, for example, use any suitable etching solution such as phosphoric acid to wet etch and remove the hard mask layer 104 on the top of the gate 103.

[0051] After that, please continue to refer to Figure 2C , at least one impurity ion such as boron (B) is used to inhibit the diffusion of cobalt, germanium, and silicon, and ion implantation is performed on the silicon capping layer 108 and the top of the gate 103, so that a part of the thickness or the entire thickness of the silicon capping layer 108 is converted into a silicon capping layer 108b rich in the injected impurity ions. At this time, since the top of the gate 103 is exposed, the top of the gate 103 is also synchronously converted into a gate capping layer 108a rich in the injected impurity ions. That is to say, at this time, the gate capping layer 108a rich in impurity ions is formed by the top of the gate 103 with a certain thickness being doped with impurity ions.

[0052] The direction of the ion implantation is perpendicular to the top surface of the substrate 100. Figure 2C As shown, it may also have an angle with the top surface of the substrate 100 (that is, the ion implantation direction is tilted), as shown in FIG. Figure 3 As shown, the ion implantation angle is 0° to 90°. Figure 3 The direction of the ion implantation forms an angle with the top surface of the substrate 100 (i.e., the direction of the ion implantation is inclined), for example, the angle of the ion implantation is 15° to 30°. Thus, during the ion implantation process, the energy of the ion implantation can be used to trim or thin the sidewall and the top surface of the gate sidewall, thereby ensuring the isolation and protection effect of the gate sidewall on the gate and providing a larger process window for the subsequent process of forming contact holes on the germanium silicon source and drain, thereby saving subsequent process steps (such as SPT) specifically for expanding the process window and saving costs.

[0053] Optionally, in step S4, a plurality of impurity ions for inhibiting the diffusion of cobalt, germanium and silicon can be implanted into the silicon capping layer 108 and the top layer of the gate 103 by co-implantation or multi-step implantation, thereby forming a silicon capping layer 108a and a gate capping layer 108b rich in the implanted impurity ions.

[0054] Optionally, in step S4, the impurity ions injected to inhibit the diffusion of cobalt, germanium, and silicon include at least one of B (boron), C (carbon), and As (arsenic). For example, the impurity ions used in step S4 to inhibit the diffusion of cobalt, germanium, and silicon include B ions and at least one of C and As.

[0055] Optionally, in step S4, the implantation concentration of impurity ions used to inhibit the diffusion of cobalt, germanium, and silicon is 1E8 atoms / cm 2 ~1E18 atoms / cm 2 The implantation angle is 0° to 90°. Preferably, the implantation concentration of the impurity ions is 1E14 atoms / cm 2 ~1E16 atoms / cm 2 , the injection angle is 15°~30°.

[0056] In this step, the thickness of the gate cap layer 108a and the silicon cap layer 108b rich in corresponding impurity ions is one of the key factors to determine the thickness of the cobalt silicide formed on the top of the germanium silicon source and drain and the gate. Optionally, in step S4, the thickness of the gate cap layer 108a and the silicon cap layer 108b rich in corresponding impurity ions are respectively Preferably, the thicknesses of the gate capping layer 108a and the silicon capping layer 108b rich in corresponding impurity ions are

[0057] Optionally, the implantation depth of the impurity ions is half of the thickness of the cobalt silicide to be formed. That is, according to the characteristic that the implanted ions conform to the Gaussian distribution, the implanted impurity ions can be considered to be mainly distributed at a position extending downward from the top surface of the silicon cap layer 108b to half of the thickness of the cobalt silicide to be formed, thereby forming a blocking isolation interface for the diffusion of cobalt and germanium in the silicon cap layer 108b.

[0058] In other embodiments of the present invention, please combine Figure 2B and Figure 2C When it is not necessary to form the gate cap layer 108 a on the top of the gate 103 , the top of the gate 103 may be masked during the above ion implantation.

[0059] In other embodiments of the present invention, in step S4, please combine Figure 2B and Figure 2C Before epitaxially growing the silicon capping layer 108 on the top surface of the silicon germanium source and drain 107, the hard mask layer 104 on the top surface of the gate 103 can be removed first. Thus, while the silicon capping layer 108 is epitaxially grown on the top surface of the silicon germanium source and drain 107, a gate capping layer (not shown) is also epitaxially grown on the top surface of the gate 103. Furthermore, when the corresponding impurity ions are injected into the silicon capping layer 108, the impurity ions are also injected into the gate capping layer. Thus, while the silicon capping layer 108b rich in the impurity ions is formed, a gate capping layer 108a rich in the impurity ions is also formed on the top of the gate 103.

[0060] In other embodiments of the present invention, in step S4, please refer to Figure 2C and Figure 4 , an epitaxial growth process combined with an in-situ doping process can be used to form a silicon capping layer 108b rich in impurity ions such as B for inhibiting the diffusion of cobalt, germanium, and silicon. Specifically, a silicon capping layer is epitaxially grown on the silicon germanium source and drain 107, and impurity ions such as B are in-situ doped during the epitaxial growth of the silicon capping layer to form a silicon capping layer 108b rich in impurity ions such as B. It should be understood that when the silicon capping layer is epitaxially grown on the silicon germanium source and drain 107, if the top of the gate 103 is covered by the hard mask layer 104, the gate capping layer 108a rich in impurity ions such as B will not be epitaxially grown on the top surface of the gate 103; if the top of the gate 103 is exposed due to the removal of the hard mask layer 104, the gate capping layer 108a rich in impurity ions such as B will be epitaxially grown on the top surface of the gate 103.

[0061] In addition, it should be noted that, whether the silicon capping layer is formed by epitaxial growth combined with ion implantation or epitaxial growth combined with in-situ doping, the doping concentration of impurity ions in the formed silicon capping layer 108b may be uniformly distributed or non-uniformly distributed in the longitudinal direction. Figure 2C And please refer to Figure 4, the silicon capping layer 108b is divided into an upper portion 108b2 and a lower portion 108b1 having different impurity ion contents, and the impurity ion content in the upper portion 108b2 of the silicon capping layer 108b is less than the impurity ion content in the lower portion 108b1 of the silicon capping layer 108b. In addition, since the gate capping layer 108a is formed simultaneously with the silicon capping layer 108b, the gate capping layer 108a is also divided into an upper portion 108a2 and a lower portion 108a1 having different impurity ion contents, and the impurity ion content in the upper portion 108a2 of the gate capping layer 108a is less than the impurity ion content in the lower portion 108a1 of the gate capping layer 108a. In this way, it is ensured that the content of impurity ions in the lower part of the gate cap layer 108a and the silicon cap layer 108b is relatively high, so as to achieve the greatest possible blocking and isolation effect, so that germanium will not diffuse into the upper part of the gate cap layer 108a and the silicon cap layer 108b, thereby avoiding the upper part of the gate cap layer 108a and the silicon cap layer 108b containing germanium, thereby ensuring that the upper part of the gate cap layer 108a and the silicon cap layer 108b reacts with cobalt without generating clustering, thereby forming cobalt silicide with lower resistance.

[0062] In step S5, metal cobalt (Co) is deposited, and a first rapid thermal treatment process such as a first rapid thermal annealing at a relatively low temperature (e.g., 400°C to 600°C) is performed, and the deposited metal Co reacts with silicon in the gate cap layer 108a and the silicon cap layer 108b to form a high-resistance cobalt silicide. Next, a second rapid thermal treatment process such as a second rapid thermal annealing at a relatively high temperature (e.g., 700°C to 900°C) is performed to convert the high-resistance cobalt silicide into a low-resistance cobalt silicide, thereby forming the desired cobalt silicide. Optionally, after the first rapid thermal treatment or after the second rapid thermal treatment, unreacted cobalt is removed.

[0063] In this step, since the silicon cap layer 108b on the silicon germanium source and drain 107 is doped with impurity ions for inhibiting the diffusion of cobalt, germanium and silicon, these impurity ions are dispersed in the grain boundaries between the cobalt silicide and the silicon germanium source and drain or the top surface of the gate below it after forming cobalt silicide (focusing on the interface between the gate and the cobalt silicide on its top, and the interface between the silicon germanium source and drain and the cobalt silicide on its top) to block the diffusion channels between the three atoms of cobalt, germanium and silicon, thereby preventing the excessive diffusion of the three atoms of cobalt, germanium and silicon under high temperature conditions, which is conducive to the formation of low-resistance cobalt silicide.

[0064] In addition, it should be understood that even if the impurity ions doped in the gate cap layer 108a and the silicon cap layer 108b for inhibiting the diffusion of cobalt, germanium, and silicon are the same as the corresponding P-type ions doped in the silicon-germanium source and drain 107, the doping concentration (or dosage) of the impurity ions in the gate cap layer 108a and the silicon cap layer 108b is higher than the doping concentration in the silicon-germanium source and drain 107. At this time, the gate cap layer 108a and the silicon cap layer 108b are layers rich in the impurity ions relative to the silicon-germanium source and drain 107. For example, the silicon-germanium source and drain 107 and the gate cap layer 108a and the silicon cap layer 108b are all doped with B ions, but the B ion doping concentration in the gate cap layer 108a and the silicon cap layer 108b is higher than the B ion doping concentration in the silicon-germanium source and drain 107. The gate cap layer 108a and the silicon cap layer 108b are B ion-rich layers relative to the silicon-germanium source and drain 107.

[0065] It should be understood that if the gate capping layer 108a and the silicon capping layer 108b are thin, they may be completely consumed when forming the cobalt silicide, or only the upper part may be consumed. Therefore, when forming the cobalt silicide, whether the gate capping layer 108a and the silicon capping layer 108b are completely consumed depends on factors such as the thickness of the gate capping layer 108a, the silicon capping layer 108b and the required cobalt silicide.

[0066] Furthermore, after forming the cobalt silicide, the method for manufacturing the semiconductor device of the present invention can further perform a back-end process, including interlayer dielectric layer deposition, contact hole etching and filling, manufacturing of a multi-layer metal interconnect structure, and the like. In the high-temperature process of the back-end process, since the previously doped ions used to inhibit the diffusion of cobalt, germanium, and silicon are dispersed on the top surface of the germanium silicon source and drain and in the grain boundaries of the cobalt silicide, the diffusion channels of cobalt, germanium, and silicon can continue to be blocked in these high-temperature processes, preventing the excessive diffusion of the three atoms of cobalt, germanium, and silicon under the high-temperature conditions of rapid thermal annealing, thereby inhibiting the occurrence of cobalt silicide clusters on the germanium silicon source and drain, ensuring the thermal stability and resistance of the cobalt silicide in the high-temperature process, and ultimately improving the device performance.

[0067] In summary, the manufacturing method of the semiconductor device of the present invention forms a silicon cap layer containing impurity ions for inhibiting the diffusion of cobalt, germanium and silicon on the germanium silicon source and drain after epitaxial growth of the germanium silicon source and drain, and forms a gate cap layer rich in the impurity ions on the top of the gate. The silicon cap layer and the gate cap layer can not only react with the subsequently deposited cobalt to form cobalt silicide, but also serve as a blocking isolation layer to utilize the impurity ions doped therein to block the diffusion channels between the three atoms of cobalt, germanium and silicon, thereby preventing the three atoms of cobalt, germanium and silicon from excessively diffusing each other under high temperature conditions, thereby facilitating the formation of low-resistance cobalt silicon. The invention can not only improve the formation of nickel silicide, but also inhibit the occurrence of cobalt silicide clusters on the germanium silicon source and drain and on the top of the gate in the subsequent high-temperature process, improve and avoid the line width effect of cobalt silicide, ensure the thermal stability and low resistance of cobalt silicide in the high-temperature process, make cobalt silicide compatible with germanium silicon source and drain, and thus can replace nickel silicide and be suitable for device manufacturing at technology nodes below 65nm, solve the problem that nickel silicide cannot meet manufacturing requirements due to its easy diffusion and poor thermal stability in high-temperature process, and overcome the technical prejudice that cobalt silicide cannot be used in device manufacturing at technology nodes below 65nm, and finally improve the performance of these devices.

[0068] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate, and forming a gate on the substrate; Etching the substrate on both sides of the gate to form source and drain trenches; epitaxially growing a silicon germanium source and drain in the source and drain trench; forming a silicon capping layer on the germanium silicon source and drain, wherein the silicon capping layer is rich in impurity ions for inhibiting diffusion of cobalt, germanium and silicon; Cobalt is deposited on the silicon cap layer, and a first rapid thermal annealing at a lower temperature and a second rapid thermal annealing at a higher temperature are performed, so that the silicon cap layer reacts with the deposited cobalt and undergoes a crystal phase transformation to form a desired cobalt silicide.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The impurity ions include at least one of B, C, and As.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the silicon capping layer rich in the impurity ions on the silicon germanium source and drain comprises: epitaxially growing the silicon capping layer on the silicon germanium source and drain; and implanting the impurity ions into the silicon capping layer; Alternatively, the step of forming the silicon capping layer rich in the impurity ions on the silicon germanium source and drain comprises: epitaxially growing the silicon capping layer on the silicon germanium source and drain, and in-situ doping the impurity ions during the epitaxial growth of the silicon capping layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The implantation angle of the impurity ions is 15° to 30°; and / or the implantation depth of the impurity ions is half of the thickness of the cobalt silicide.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: Before the impurity ions are injected into the silicon cap layer, a protective layer is first formed on the silicon cap layer; and / or a gate sidewall is also formed on the side wall of the gate; during the process of injecting the impurity ions into the silicon cap layer, the injection of the impurity ions also etches the surface of the gate sidewall to trim the surface morphology of the gate sidewall or thin the gate sidewall.

6. The method for manufacturing a semiconductor device according to claim 3, wherein: While the silicon capping layer rich in the impurity ions is formed on the silicon germanium source and drain, a gate capping layer rich in the impurity ions is also synchronously formed on the top of the gate, wherein the gate capping layer is a film layer epitaxially grown on the top of the gate or is formed by doping the impurity ions on the upper part of the gate.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that: The doping concentration of the impurity ions is 1E8 atoms / cm 2 ~1E18 atoms / cm 2 ; and / or, the thickness of the silicon capping layer is 8. The method for manufacturing a semiconductor device according to claim 7, wherein: The doping concentration of the impurity ions is 1E14 atoms / cm 2 ~1E16 atoms / cm 2 , and / or, the thickness of the silicon capping layer is 9. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that: A content of the impurity ions in an upper portion of the silicon capping layer is less than a content of the impurity ions in a lower portion of the silicon capping layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: There is no germanium in the upper portion of the silicon capping layer.

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