Low-redundancy cascode bias circuit for cascode current mirror

By designing a cascade bias circuit, the problem of unequal drain-source voltages between the diode-connected transistors and the current source transistors in the current mirror is solved, and a higher current mirror accuracy and low redundancy cascade bias circuit is achieved.

CN120051741APending Publication Date: 2025-05-27QUALCOMM INC
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Patent Information

Application Number
CN202380075571.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2022-11-07
Filing Date
2023-10-25
Publication Date
2025-05-27

AI Technical Summary

Technical Problem

The drain-source voltages of existing current mirrors are not equal between the diode-connected transistors and the current source transistors, resulting in channel length modulation and reducing the accuracy of the current mirror.

Method used

A casubarc bias circuit is designed to bias the casubarc bias current mirror by driving a first current into a first transistor, a second current into a second transistor, and combining the two to form a combined current into a third transistor such that the gate voltage of the first transistor is equal to the sum of its gate source voltage and the drain source voltage of the third transistor.

Benefits of technology

The equality of drain-source voltages between the diode-connected transistor and the current source transistor is achieved, reducing channel length modulation, improving the accuracy of the current mirror, and the designed cassue cassue bias circuit has low redundancy and basically no bulk effect.

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Abstract

The cascode bias circuit biases the grid electrode of the cascode transistor in the cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current, and includes a second transistor configured to conduct a second current. The first transistor and the second transistor are coupled to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor is coupled to a gate of the cascode transistor to bias the cascode transistor.
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