Package of 3D integrated circuit and substrate structure thereof

Abstract

The present disclosure provides a package of a 3D integrated circuit. The package of the 3D integrated circuit includes a substrate structure having a first surface and a second surface opposite the first surface; the high-power bare core is arranged above the substrate structure; the low-power bare core is arranged above the high-power bare core; a first interposer disposed between the first surface of the substrate structure and the high-power die; and a second interposer disposed between the high power die and the low power die. The substrate structure includes a thermal enhancement portion underlying the high power die, and at least one of thermal conductivity or geometry of the thermal enhancement portion differs from other portions of the substrate structure. A substrate structure of a package of a 3D integrated circuit is also provided.

Description

[0001] Priority Claim and Cross - References

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 603,654, filed on November 29, 2023; U.S. Provisional Patent Application No. 63 / 603,650, filed on November 29, 2023; U.S. Provisional Patent Application No. 63 / 603,652, filed on November 29, 2023; and U.S. Provisional Patent Application No. 63 / 635,644, filed on April 18, 2024, the entire contents of each of which are hereby incorporated by reference. Technical Field

[0003] The present disclosure relates to a package and substrate structure for a 3D integrated circuit (3D IC), particularly a package of a 3D IC including structural features for heat dissipation. The substrate structure can implement a heat dissipation mechanism in the package of the 3D IC. Background Art

[0004] The disclosure of the present disclosure aims to alleviate three classic problems in the computing field: (1) the memory wall, (2) the I / O wall, and (3) the lateral power delivery and power wall, while providing unprecedented energy efficiency by stacking memories in a vertical (or package thickness) direction on a processor, combining photon I / O with a vertical power delivery network, using state - of - the - art high - bandwidth memory (HBM) DRAM stacks (such as HBM3) and GPUs (such as the Nvidia H100 that drives ChatGPT or its next - generation equivalents), to illustrate its application prospects in fields such as high - performance computing (HPC), data centers, and artificial intelligence (AI).

[0005] The memory wall may refer to a situation where a performance bottleneck occurs when the speed of the processor exceeds the speed of accessing the memory. This technical problem has emerged in the development of advanced memory structures, where the ability of the processor to execute instructions quickly is hindered by the slow speed of accessing data from the memory. This physical barrier may limit the development of AI technology because the processor may spend a large amount of time waiting to retrieve data from the memory and cannot fully utilize its processing power, resulting in a decline in the overall system performance.

[0006] The transmission speed of input / output (I / O) can also become another bottleneck restricting computing performance. When the transmission speed between the processor and the memory is lower than the computing speed of the processor, the processor will be affected, and its performance will decrease due to the delay in data transmission.

[0007] The power wall refers to the limitation of the processor clock speed, which is caused by the power consumed and the resulting heat dissipation. The switching power (P) dissipated by the chip is proportional to the capacitance (C), the square of the voltage (V2), and the frequency (f). Therefore, the higher the frequency at which the processor operates, the more power it will consume and the more heat it will generate. If the clock frequency of the chip is higher, then it is not just a matter of the chip being too hot. The term "wall" actually refers to a combination of various factors that limit the performance of the processor, including power consumption, heat dissipation, and other technical limitations. These factors make it difficult or impossible to continue increasing the clock speed, resulting in a "wall" that limits the performance of the processor.

[0008] Refer to Figure 1 , in the past approximately twenty years (i.e., from the 1990s to 2023), the expansion of peak hardware floating point operations per second (FLOPS) and memory / interconnect bandwidth has continued without interruption. During this period, the hardware FLOPS has grown by approximately 60,000 times (growing 3 times every two years on average), the bandwidth of DRAM has grown by approximately 100 times (growing 1.6 times every two years on average), and the interconnect bandwidth has grown by approximately 30 times (growing 1.4 times every two years on average) - please refer to the article "The Memory Wall and Its Implications" published by Silicon Matter on March 16, 2024.

[0009] Despite the amazing progress in the development of processors and memories in the past few decades, the operating speed of the processor far exceeds the speed at which the memory chip provides data, and the performance gap between the processor and the memory continues to widen.

[0010] The performance gap caused by the above-mentioned memory wall (referring to the physical barrier that restricts the speed of data movement between the memory and the processor in the system) is constantly expanding, which causes processors such as GPUs and CPUs to spend a lot of time waiting and idling when transferring data in the memory, thereby significantly affecting the system performance, especially for tasks that require simultaneously processing a large amount of data quickly, such as executing complex AI algorithms. In fact, due to AI accelerators (such as those using 2.5D ICs The H100, which is currently the world's most advanced GPU, is designed for efficient and high-speed parallel processing of large amounts of data. Therefore, the memory wall is rapidly becoming a major problem for AI applications.

[0011] As Figure 1 shown, it shows the bandwidth scaling of different generations of memory, interconnects, and CPUs / GPUs. It can be seen that the hardware FLOP, as well as the DRAM bandwidth and interconnect bandwidth, continue to expand. This performance difference, combined with power consumption, seriously impairs the efficiency of the processor. These bottlenecks result in expensive underutilization of the H100 GPU, highlighting the key efficiency issues in executing various AI algorithms and large language models on it.

[0012] By using liquid cooling for heat dissipation management, the disclosure of the present invention proposes packaging 6 HBM3s with the GPU in the vertical or package thickness direction (i.e., the z-direction) to significantly alleviate the memory wall and bandwidth problems. This is because compared with the 2.5D IC counterparts currently packaging H100 and 6 HBM2Es (or 6 HBM3s), vertical stacking can (1) significantly shorten the data transfer distance between the processor and the memory; (2) provide a much higher bus width / interconnect bandwidth (because the number of data paths that can be established between the processor and the memory increases significantly); (3) accelerate the data transfer between the processor and the memory; (4) significantly reduce power consumption and energy consumption; and (5) achieve a much higher processor power (under the same other conditions). Previous studies have shown that each time data is transferred back and forth on the memory bus, accessing each byte of DRAM requires approximately 60 picojoules of energy, which is thousands of times more than the 50-60 femtojoules of energy required for each operation of processing data. Due to the higher bandwidth and shorter data transfer distance, 3D IC stacking helps to minimize the required energy consumption.

[0013] It is worth mentioning in passing that stacking high-power GPUs (e.g., currently the power of the H100 is 700W / chip, and it can be higher than approximately 2,000W / chip in the future) and HBMs vertically will inadvertently cause the high-power GPUs and HBMs to overheat, far exceeding their maximum operating temperature (e.g., approximately 120°C). To address this heat dissipation problem, some companies have tried to use co-design of IC packaging systems, heat vias, heat planes, and / or heat bumps. However, this method has its limitations in terms of the maximum GPU power it can handle. In this configuration, when the GPU power reaches 1,500W / chip, according to some simulation results, even with liquid cooling, the GPU may overheat to above 250°C. Using copper hybrid bonding also cannot alleviate this overheating problem. Summary of the Invention

[0014] In an exemplary aspect of the present disclosure, a package of a 3D IC is provided. The package of the 3D IC includes a substrate structure having a first surface and a second surface opposite to the first surface; a high-power die disposed above the substrate structure; a low-power die disposed above the high-power die; a first interposer disposed between the first surface of the substrate structure and the high-power die; and a second interposer disposed between the high-power die and the low-power die. The substrate structure includes a thermal enhancement portion located below the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure.

[0015] In another exemplary aspect of the present disclosure, a package of a 3D IC is provided. The 3D IC package includes a substrate structure having a first surface and a second surface opposite to the first surface; a low-power die disposed above the substrate structure; a first high-power die disposed above the low-power die; a first interposer disposed between the first surface of the substrate structure and the low-power die; and a second interposer disposed between the first high-power die and the low-power die. The substrate structure includes a thermal enhancement portion located below the first high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure.

[0016] In yet another exemplary aspect of the present disclosure, a substrate structure is provided. The substrate structure includes a plurality of substrate units separated from each other, and a bridging structure for electrically connecting adjacent substrate units. The bridging structure includes a first side and a second side opposite to the first side, and at least one of the first side or the second side is electrically connected to an adjacent substrate unit or an integrated circuit through copper pillar microbumps or an interconnect layer (such as copper hybrid bonding).

[0017] Brief Description of the Drawings

[0018] Various aspects of the present disclosure can be best understood when reading the following embodiments and the accompanying drawings. It should be noted that, according to the standard operating habits in the art, the various features in the drawings are not drawn to scale. In fact, in order to clearly describe, the dimensions of some features may be deliberately enlarged or reduced.

[0019] Figure 1 Illustrates the ratio of peak hardware FLOP and memory / interconnect bandwidth;

[0020] Figure 2 Illustrates a cross-sectional view of a 2.5D IC structure according to some comparative embodiments;

[0021] Figure 3Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0022] Figure 4 Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0023] Figure 5A Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0024] Figure 5B Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0025] Figure 5C Shows a cross-sectional view of a 3D IC structure with a heat sink according to some embodiments of the present disclosure;

[0026] Figure 6 Shows a perspective view of a substrate structure according to some embodiments of the present disclosure;

[0027] Figure 7 Shows the simulation results of a 3D IC structure cooled by liquid immersion according to some embodiments of the present disclosure;

[0028] Figure 8 Shows the simulation results of a 3D IC structure cooled by liquid immersion according to some embodiments of the present disclosure;

[0029] Figure 9 Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0030] Figure 10 Shows a cross-sectional view of a 3D IC structure with a heat spreader according to some embodiments of the present disclosure;

[0031] Figure 11 Shows a cross-sectional view of a 3D IC structure with a heat spreader according to some embodiments of the present disclosure;

[0032] Figure 12 Shows a cross-sectional view of a 3D IC structure with a heat spreader according to some embodiments of the present disclosure;

[0033] Figure 13 Shows a cross-sectional view of a 3D IC structure cooled by liquid immersion according to some embodiments of the present disclosure;

[0034] Figure 14Shows a cross-sectional view of an enhanced 2.5D IC structure with a heat spreader according to some embodiments of the present disclosure;

[0035] Figure 15 Shows a cross-sectional view of an enhanced 2.5D IC structure with a heat spreader according to some embodiments of the present disclosure;

[0036] Figure 16A And 16B Shows a cross-sectional view of a composite interposer according to some embodiments of the present disclosure;

[0037] Figure 16C Shows a cross-sectional view of a 3D IC structure with a composite interposer according to some embodiments of the present disclosure;

[0038] Figures 17A to 17F Shows a cross-sectional view of a process for manufacturing a composite interposer according to some embodiments of the present disclosure;

[0039] Figure 18A Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0040] Figure 18B Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0041] Figure 19A Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0042] Figure 19B Shows a cross-sectional view of a 3D IC structure according to some embodiments of the present disclosure;

[0043] Figure 20A Shows a top view of a portion of a 3D IC structure according to some embodiments of the present disclosure;

[0044] Figure 20B Shows a side view of a portion of a 3D IC structure according to some embodiments of the present disclosure;

[0045] Figure 21A Shows a cross-sectional view of a substrate structure according to some embodiments of the present disclosure;

[0046] Figure 21B Shows a cross-sectional view of a substrate structure according to some embodiments of the present disclosure;

[0047] Figures 22A to 22C Shows a cross-sectional view of a substrate structure with a flexible circuit according to some embodiments of the present disclosure;

[0048] Figure 23 A cross-sectional view of a substrate structure with hybrid bridging, according to some embodiments of the present disclosure;

[0049] Figures 24A to 24C A cross-sectional view of a substrate structure with edge-connected bridging, according to some embodiments of the present disclosure;

[0050] Figures 25A to 25E A cross-sectional view of a process for manufacturing a substrate structure with edge-connected bridging, according to some embodiments of the present disclosure;

[0051] Figure 26A A cross-sectional view of a substrate structure with bilateral bridging, according to some embodiments of the present disclosure;

[0052] Figure 26B A cross-sectional view of a substrate structure with bilateral bridging, according to some embodiments of the present disclosure;

[0053] Figures 27A to 27D A cross-sectional view of the position of an electronic device in a 3D IC structure, according to some embodiments of the present disclosure.

[0054] In the following detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the disclosed embodiments. It will be understood, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form to simplify the drawings. Embodiments

[0056] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first component above a second component or the formation of a first component on top of a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present disclosure may repeat element symbols and / or letters in various instances. This repetition is for purposes of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0057] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", and the like may be used in this disclosure to describe the relationship of one element or component to another element or component, as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0058] As used in this disclosure, terms such as "first", "second", and "third" are used to describe various elements, components, regions, layers, and / or sections, and these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another. When terms such as "first", "second", and "third" are used herein, it does not mean order or sequence, unless specifically indicated by the context.

[0059] Referring to Figure 2 , which illustrates a 2.5D integrated circuit (IC) structure in some comparative embodiments. As shown, the 2.5D IC structure 90 includes a substrate 914 as a carrier. A plurality of ball grid array (BGA) balls 901 may contact one side of the substrate 914. The silicon interposer 902 is bonded to the substrate 914 through a plurality of solder bumps 903. On the silicon interposer 902, a plurality of HBMs 906 and logic ICs (such as GPU 900) may be disposed on the upper side of the silicon interposer 902. The HBM 906 and the GPU 900 may be electrically connected to the silicon interposer 902 through a plurality of micro-bumps 905 or solder bumps. In the comparative embodiment, the GPU 900 may be cooled by attaching a heat spreader (HS, or vapor chamber) to the back side of the GPU and attaching a cooling plate to the HS, that is, direct-to-chip (DtC) liquid cooling is adopted. Alternatively, a fin structure (such as a silicon-based HS containing micro-fins bonded to the back of the GPU) may be used to cool the GPU, and the fin structure is directly cooled by a liquid cooling flow. The heat dissipation capacity of such a cooling mechanism is greater than 6.8 W / mm 2 .

[0060] To achieve more efficient heat dissipation for 3D ICs containing high-power processors and HBMs, some embodiments of the disclosure present 3D IC structures that can include different heat dissipation or heat transfer structures suitable for one or more cooling methods, which have better heat dissipation efficiency than direct liquid cooling of chips. The structures and their parts for 3D ICs disclosed herein can also be applied to next-generation 2.5D ICs and hybrid 2.5D / 3D structures, which involve higher-power processors and memory devices and involve stacking multiple processors and memory devices in the z direction. Some embodiments of the disclosure aim to solve or significantly mitigate the overheating problems in 2.5D and 3D ICs for high-performance computing, data centers, and AI computing for logic devices (such as GPUs, CPUs, neural network processing units (NPUs), tensor processing units (TPUs), etc.) and memory devices (such as HBMs).

[0061] Referring Figure 3 , in some embodiments, the 3D IC structure 10 includes a substrate structure 114 having a first surface 114A and a second surface 114B opposite the first surface 114A. A high-power die 100 is disposed above the substrate structure 114. In some embodiments, the high-power die 100 is a logic device, such as a GPU, CPU, NPU, TPU, etc. The logic device can be an IC chip or a combination of some chiplets. One or more low-power dies 106 are disposed above the high-power die 100. In some embodiments, the low-power die 106 is a memory device, such as HBM. In some embodiments, the low-power die 106 can be a passive device (e.g., deep trench capacitor), an active device (such as an integrated voltage regulator or a low-power processor), or an optical device (such as optical I / O).

[0062] A first interposer 102 is disposed between the first surface 114A of the substrate structure 114 and the high-power die 100. A second interposer 104 is disposed between the high-power die 100 and the low-power die 106. In some embodiments, one or both of the first interposer 102 and the second interposer 104 can be used for heat dissipation, or at least substantially provide a cooling effect. For example, in Figure 3In the 3D IC structure 10 shown, the high-power die 100 is sandwiched between a first interposer 102 and a second interposer 104, and the first interposer 102 and the second interposer 104 can be made of a high-thermal-conductivity (HTC) material, such as diamond with a thermal conductivity (TC) greater than 1,500 W / m·K, which can be used for heat dissipation to ensure that the processors and HBMs in the 3D IC do not overheat. Moreover, and more importantly, the 3D IC can support high-power processors to achieve higher performance. Furthermore, in order to design the first interposer 102 and the second interposer 104 to have appropriate heat dissipation capabilities based on factors such as performance, cost, and time-to-market (TTM), two interposers can be selected from a variety of materials to have appropriate TC, such as from diamond (the TC of polycrystalline diamond is greater than 1,500 W / m·K) to glass (TC is about 1 W / m·K), depending on the specific 2.5D IC, 3D IC, or 2.5D / 3D hybrid structure to be considered, the location of the higher-power processors, and the thermal design power (TDP).

[0063] For example, in some embodiments, the high-power die 100 is cooled under a bilateral cooling topology, where both the first interposer 102 and the second interposer 104 are made of HTC, low-coefficient-of-thermal-expansion (LCTE) interposers. The high HTC materials used to form the two interposers can be the same material or different materials. In some embodiments, the thermal conductivities of the first interposer 102 and the second interposer 104 are generally greater than about 1,500 W / m·K. For example, the thermal conductivity of single-crystal diamond is ≧2,000 W / m·K, which is the highest among all known materials on Earth.

[0064] In some embodiments, the thermal conductivity of the second interposer 104 is less than that of the first interposer 102. For example, the thermal conductivity of the second interposer 104 can be less than about 1,500 W / m·K (e.g., glass can be as low as about 1 W / m·K), while the thermal conductivity of the first interposer 102 is greater than 1,500 W / m·K. In addition to TC, the heat dissipation capabilities of these interposers also depend on the size of the interposer, i.e., its x-y-z dimensional size, where x-y is the plane perpendicular to the thickness of the interposer or the z direction. For example, in some cases, the size of the second interposer 104 is much smaller than that of the first interposer 102 (please refer to Figure 4in the 3D IC structure 11), so assuming that the first interposer 102 and the second interposer 104 are made of the same material, the heat dissipation ability of the second interposer 104 from the high-power die 100 will be less than that of the first interposer 102.

[0065] As Figure 4 shown, the materials of the first interposer 102 and the second interposer 104 can both be diamond, and its TC is greater than or equal to 2,000 W / m·K. Compared with materials such as silicon (TC is about 148 W / m·K) and glass (e.g., the TC of silicon dioxide is about 1 W / m·K), the heat dissipation benefit of the interposer containing diamond is obvious. In addition to diamond, in other embodiments, the high-TC interposer can be made of other HTC materials, including cubic-boron nitride (c-BN), silicon carbide (SiC), or aluminum nitride (AlN), a composite material containing a combination of these HTC materials, or a composite material containing one or more of these HTC materials and a lower TC (LTC) material (such as silicon or glass).

[0066] In some embodiments, the high-power die 100 is cooled under a single-sided cooling topology. In these embodiments, the first interposer 102 is an HTC, LCTE interposer. In some embodiments, the first interposer 102 is an HTC interposer, and its heat dissipation ability can be improved by introducing a thermal enhancement portion (TEP) 116 below the first interposer 102, and its characteristics will be described later. Although not shown in the figure, the TEP can be thermally coupled to the heat path and planar in the substrate structure 114 until the perimeter of the substrate. In some embodiments, the second interposer 104 is an LTC interposer. The LTC interposer can be from glass, another LTC material (such as a fan-out structure based on a molding compound (with or without embedded dies)), or a composite material including an LTC material and silicon.

[0067] In some embodiments, in order to improve the heat dissipation ability, materials or composite materials with an effective TC higher than that of silicon (or silicon carbide) can be used to fabricate the high-power die 100 and / or the low-power die 106.

[0068] In some embodiments, as Figure 3As shown, the 3D IC structure 10 may include one or more bridge interconnect dies 107 (hereinafter referred to as "bridge dies"), which are disposed between the first interposer 102 and the second interposer 104. In some embodiments, the bridge die 107 is flush with the high-power die 100. In some embodiments, the bridge die 107 includes a plurality of interconnect structures (such as wires, redistribution layers (RDLs), vias, etc.) for providing signal and / or power transmission functions. The substrate forming the interconnect structures of the bridge die may include silicon, HTC material, LTC material, or a combination thereof.

[0069] The bridge die 107 may have different structures. For example, the bridge die 107 can be formed by stacking interposer-lets made of silicon, glass, HTC material, LTC material, or a combination thereof, so these interposer-lets contain vias and RDLs, similar to die stacking when forming HBM. The bridge die can also be formed by stacking fan-out layers with vias and / or vertical metal lines, stacking package-on-package (PoP) layers with vias and / or vertical metal lines, or a combination of these configurations. In other examples, the bridge die 107 can also be co-packaged with the IC using, for example, a fan-out process.

[0070] Similarly referring to Figure 3 , the substrate structure 114 includes a thermally enhanced portion 116, which is located below the high-power die 100 and is thermally coupled to the HTC first interposer and the high-power die 100. In some examples, the TEP 116 can be directly disposed directly below the high-power die 100 (i.e., below the projected area of the high-power die 100). In other examples, the TEP 116 can partially overlap the high-power die 100 in the vertical direction. In some embodiments, if the low-power die 106 is also an object to be cooled, the TEP 116 can be located below the low-power die 106. The TEP 116 can be an opening so that the lower side of the first interposer contacts the liquid coolant during the liquid immersion cooling process, or an HTC material (such as diamond) can be filled therein. In both cases, the TEP 116 is thermally coupled to the first interposer 102.

[0071] The 3D IC structure 10 can be cooled by directly liquid-cooling the chip. For example, a heat spreader bonded to a cold plate using a thermal interface material (TIM) can use another TIM to directly contact the exposed upper surface of the 3D IC structure 10. The two TIMs here can be metal or polymer-based materials. Since the high-power die 100 is located below the second interposer 104, the cold plate / heat spreader sub-assembly (CHS) can be thermally coupled to the first interposer 102, which transfers heat from the high-power die 100 to the first interposer 102 and then to the CHS through an HTC ring structure integrated with the CHS. Alternatively, liquid immersion cooling can also be used in conjunction with Figure 4 the implementation of the TEP 116 and / or the large interposers (such as the first interposer 102 and the second interposer 104) therein. In some embodiments, the heat dissipation of the high-power die 100 (such as GPU, CPU, NPU, TPU, etc.) and / or the low-power die 106 (such as HBM) can be achieved by immersing the 3D IC structure 10 in a liquid coolant. Specifically, the liquid immersion cooling method can involve using a single-phase dielectric coolant, a two-phase dielectric coolant, or water with a conformal surface passivation layer. The dielectric coolant can include non-conductive fluorocarbons or hydrocarbons. Due to the conductivity of water, a pre-coating operation may be required in some embodiments, in which the 3D IC structure 10 is coated with a conformal, pinhole-free insulating material, such as parylene (see Figure 18B the organic coating 180).

[0072] In some embodiments, the 3D IC structure 10 may further include an optical device disposed on the first interposer 102 or the second interposer 104. The optical device is electrically and optically coupled to the high-power die 100 through the first interposer 102 or the second interposer 104. In some embodiments, the optical device may include a waveguide structure, a photon IC, an electrical IC, and fiber optic interconnect I / O.

[0073] Referring to Figure 5A , in some embodiments, in the 3D IC structure 12, the high-power die 100 can be disposed above the second interposer 104 instead of below the second interposer 104. In some embodiments, the low-power die 106 is disposed above the first interposer 102. In some embodiments, the low-power die 106 is sandwiched between the first interposer 102 and the second interposer 104. The first interposer 102 in the 3D IC structure 12 is a low-TC interposer, while the second interposer 104 is a high-TC, LCTE interposer. And Figure 3In contrast to the 3D IC structure 10 shown, the high-power die 100 is located above the 3D IC structure 12; while the low-power die 106 is located below the second interposer 104, where the low-power die 106 can be electrically connected to both the first interposer 102 and the second interposer 104 by, for example, copper pillar micro-bumps and / or copper hybrid bonding.

[0074] In some alternative embodiments, referring to Figure 5B , after mounting the high-power die 100 and the low-power die 106 on opposite sides of the second interposer 104, the second interposer 104 can be mounted above the first interposer 102 to form a 3D IC structure 12A, and one side 1061 of the low-power die 106 does not have conductive terminals, so there are no micro-bumps or copper hybrid bonds directly connecting the low-power die 106 to the first interposer 102.

[0075] Referring to Figure 5C , this example illustrates the application of direct chip liquid cooling to the high-power die 100 located on top of the 3D IC structure 12 in Figure 5A . In some embodiments, a fin structure such as a silicon heat spreader with micro-fins (not shown) or a heat sink 140A with micro-fins 147 and micro-channels 149 is thermally coupled to the back side of the high-power die 100, which enables the liquid coolant to cool the adjacent high-power die 100 by utilizing the high-speed liquid flow impinging on the fin structure or the liquid flow passing through the micro-fins with micro-channels.

[0076] In an alternative embodiment, the high-power die 100 can be a monolithic IC device, and its back side includes multiple micro-fins for impingement flow cooling. In this case, the second interposer 104 can be an HTC interposer for cooling the high-power die 100 from both sides. Alternatively, the second interposer 104 can also be an LTC interposer, depending on the power of the high-power die 100. In the latter case, the second interposer 104 can be made of a relatively thick LTC material to more effectively block the heat energy from the high-power die 100 from being transmitted to the low-power die 106 below it.

[0077] Moreover, in the case of direct chip liquid cooling, when the second interposer 104 is an LTC interposer, the size of the second interposer 104 can be synchronously adjusted and optimized with the size of the HTC first interposer 102 to avoid overheating of the die. When using liquid immersion cooling, the HTC interposer requires a larger area for heat exchange with the liquid coolant, while the low-TC interposer does not require such a large area.

[0078] In some thermal management strategies, the second interposer 104 is an HTC interposer for heat dissipation, while the first interposer 102 can be an HTC interposer or an interposer with a lower TC (e.g., a silicon interposer), because most of the heat from the high-power die 100 is dissipated upward and laterally through the second interposer 104. When the cost of the HTC interposer is high, the decision of whether to use HTC materials for the first interposer 102 and the second interposer 104 should depend on the power of the high-power die 100 and how to achieve the best balance among cost, heat dissipation of the high-power die 100, and the maximum operating temperatures of both the high-power die 100 and the lower-power die 106. In some cases, the TC of the first interposer 102 can be equal to or lower than the TC of the second interposer 104.

[0079] Referring Figure 6 , in some embodiments, the substrate structure 114 may include a plurality of through-channels 115 that penetrate the substrate structure 114. These through-channels 115 are designed to allow a liquid coolant to pass through the substrate structure 114 during liquid immersion cooling and to be in close contact with the heat sources above the substrate structure 114 (e.g., directly or through the first interposer 102 to contact the high-power die 100 and the low-power die 106). In some embodiments, the width D1 of the through-channels 115 may be approximately 8 mm. In some cases, the width D1 on both sides of the substrate structure 114 may vary due to manufacturing techniques. In some embodiments, the thickness T1 of the substrate structure 114 may be approximately 1,700 μm. Additionally, similar to the through-channels 115 that penetrate the substrate structure 114, one or more open vias may be established in the interposer to provide channels connecting both sides of the interposer. For example, these open vias may be formed in the first interposer 102 and / or the second interposer 104 with a width of approximately 20 μm to approximately 100 μm. In some embodiments, femtosecond lasers or laser-induced deep etching can be used to establish the through-channels 115 in the substrate structure 114 and the open vias in the interposer. For example, the femtosecond laser used to form the through-channels 115 or the open vias may have a wavelength of approximately 1.03 μm, a pulse duration of less than approximately 500 fs, and a repetition rate of approximately 500 kHz. The process of manufacturing a diamond-based interposer is similar to that of a silicon-based interposer, with the main difference being the process of creating holes (i.e., the process of forming open vias).

[0080] Referring Figure 7 , the figure shows the simulation results of a 3D IC structure with liquid immersion cooling. In Figure 7Among them, GPU_1 and GPU_2 are the high-power dies 100 in the 3D IC structure 10 and the 3D IC structure 12 respectively; while HBM_1 and HBM_2 are the low-power dies 106 in the 3D IC structure 10 and the 3D IC structure 12 respectively. The simulation is carried out under the following input simulation conditions: (a) using a diamond interposer as the HTC interposer (i.e., the first interposer 102 and the second interposer 104 in the 3D IC structure 10); (b) using a glass (silica) interposer as the LTC interposer (i.e., the second interposer 104 in the 3D IC structure 12); (c) using a silicon interposer (i.e., the first interposer 102) under the low-power die in the 3D IC structure 12; (d) the power of the GPU is 1,500 W; (e) 6 HBMs (HBM3, each HBM includes 12 DRAM dies and 1 control IC), with a power of 20 W / HBM; (f) using water as the coolant; (g) the ambient temperature is 20 °C; (h) the width of the through-channel in the substrate structure is 8 mm; and (i) using a 2.5D IC package, with the die size and interconnect structure similar to the H100 GPU (2.5D IC structure). Briefly speaking, the main difference between the 3D IC structure 10 and the 3D IC structure 12 for simulation is that the GPU in the 3D IC structure 10 is sandwiched between two diamond interposers, while the GPU in the 3D IC structure 12 is mounted on a silica interposer.

[0081] As Figure 7 shown, the simulation results illustrate the maximum junction temperature (T jmax ) as a function of the flow rate under water immersion cooling. As shown by the simulation results, the temperature of the 3D IC structure 12 can be more than 50 °C lower than the maximum operating temperature (120 °C), indicating that the GPU power may be increased to more than 2,000 W to achieve higher performance. In addition, in the 3D IC structure 12, it is possible to expect that the LTC interposer (such as a silica interposer) may be replaced by an HTC interposer (such as a diamond interposer) to achieve better heat dissipation performance. Regarding the 3D IC structure 10, there may still be operable conditions, such as using a larger diamond interposer and a larger channel width, to keep the temperatures of the GPU and HBM below the maximum operating temperature (120 °C).

[0082] Referring to Figure 8 , which is shown in the 3D IC structure 12, the simulation results when the through-channel 115 passing through the substrate structure 114 (see Figure 6 ) has different diameters. As shown in the figure, by increasing the width of the through-channel 115 in the substrate structure 114 from 0 to about 8 mm, the temperatures of the GPU and HBM can be significantly reduced. After exceeding 8 mm, the effect is not so obvious.

[0083] In traditional 2D flip-chip and 2.5D IC packages, heat dissipates upward along the z-direction, through the backside of the processor to the heat spreader and the heat sink or cold plate, i.e., based on a single-sided cooling topology. In embodiments such as 3D IC structure 10 and 3D IC structure 12, heat dissipation or cooling can occur on one side (single-sided cooling topology) or both sides (double-sided cooling topology). For example, when a high-power die 100 (such as a GPU) is sandwiched between two HTC interposers in 3D IC structure 10, or when a high-power chip 100 is placed between an HTC interposer and a liquid cooling mechanism (the liquid cooling mechanism can include, for example, a cold plate, cooling fins, or an impinging coolant flow).

[0084] Figure 9 Another embodiment is illustrated, where 3D IC structure 13 is a combination of 3D IC structure 10 and 3D IC structure 12 described in the above embodiments. In this example, two or more high-power dies (such as first high-power die 1001 and second high-power die 1002) can be included in 3D IC structure 13 and are disposed on different interposers. These high-power dies can achieve the heat dissipation characteristics derived from 3D IC structure 10 and 3D IC structure 12. For example, at least one of the high-power dies (such as first high-power die 1001) can be sandwiched between two third HTC interposers 152, and the size of these third HTC interposers 152 in the vertical direction can be greater than Figure 9 as shown, so that it can be effectively cooled by means of double-sided cooling. The second high-power die 1002 is located on the top side of 3D IC structure 13 and can be cooled by the liquid cooling method using the method of cooling the high-power die 100 described in the embodiment of 3D IC structure 12 for this second high-power die 1002.

[0085] Referring to Figures 10 to 15 , for illustrative purposes, the disclosure of the present disclosure presents several structural methods to enhance heat dissipation in 3D IC structures (see Figures 10 to 13 ) and several enhanced 2.5D IC structures (see Figure 14 and 15 ). These enhanced heat dissipation structures will provide more die stacking design options, as well as higher-power processors and more processors, which can be integrated with more HBMs and other memory devices without causing die overheating, to improve the performance of HPC, data centers, AI applications, and other high-order applications (such as networking and in-vehicle).

[0086] Referring to Figure 10, in some embodiments, the HTC heat spreader 140 in the 3D IC structure 14 can be disposed on and thermally coupled to the first surface 114A of the substrate structure 114. The heat spreader 140 can also be thermally coupled to the back surface of the low-power die 106 located at the top in the 3D IC structure 14. The heat spreader 140 can include a plurality of HTC support portions 142, the height of which is substantially equal to or approximately equal to the stacked height of the dies in the 3D IC structure 14. In some embodiments, a spacer 144 is disposed between the support portion 142 and the first surface 114A of the substrate structure 114. In the disclosure of the present disclosure, the spacer can be an HTC TIM, and these HTC TIMs can be used interchangeably because those of ordinary skill in the art to which the present disclosure pertains can understand that the HTC TIM is an exemplary implementation of an HTC spacer, and using such a term (i.e., HTC TIM) does not exclude an HTC spacer composed of other suitable materials at the specific position. The spacer 144 can be a non-conductive colloid or film. In some embodiments, the 3D IC structure 14 includes a first interposer 102 on the first surface 114A of the substrate structure 114. The first interposer 102 can be an HTC interposer; for example, it can be a diamond-based interposer, and has a plurality of vias and RDLs on its two opposite sides for electrical connection with adjacent electronic components. In the 3D IC structure 14, the high-power die 100 is disposed on the first interposer 102. In some embodiments, the high-power die 100 can have a back power delivery network (BSPDN) structure 1003, which is electrically connected and thermally coupled to the HTC carrier 1004, and this HTC carrier 1004 is located on the side facing the first interposer 102. Compared with the BSPDN design in some comparative examples, the BSPDN structure 1003 with the carrier 1004 in the disclosure of the present disclosure adopts a diamond-based carrier / interposer, which has vias and RDLs on both the bottom side and the top side, while the BSPDN design in some comparative embodiments uses silicon as the carrier material on the top side of the high-power die 100. Since the thermal conductivity of the diamond-based carrier (≧2,000 W / m.K) is much higher than that of the silicon-based carrier (about 150 W / m.K), this BSPDN design (i.e., the stack of the BSPDN structure 1003 and the carrier 1004) can greatly improve the heat dissipation capacity of the high-power die 100. In some embodiments, the high-power die 100 can further include a front-end-of-line (FEOL) structure 1008, a local interconnect layer and an intermediate interconnect layer 1007 (which can include a redistribution layer on the intermediate interconnect layer) combined with the second interposer 104, and a global interconnect layer 1005 combined with the RDL 1006 of the carrier 1004.A copper hybrid bond or a flip chip (not shown) can be used to electrically connect the local / intermediate interconnect layers 1007 on both sides of the high-power die 100 to the global interconnect layer to adjacent electronic components.

[0087] In other embodiments, a high-power die 100 based on a conventional front-side power delivery network (FSPDN) can also be used to replace the BSPDN-type high-power die 100 in the 3D IC structure 14. In this case, the FEOL side of the high-power die 100 faces down (instead of up as shown in Figure 10 ) and is bonded to the first interposer 102. The high-power die 100 also includes vias that penetrate the die thickness, which connect the BEOL layer between the FEOL layer and the first interposer 102 to the RDL on the opposite side (back side) of the high-power die 100.

[0088] Referring to Figure 11 , in some embodiments, the HTC heat spreader 140 in the 3D IC structure 15 can be disposed on and thermally coupled to the first surface 114A of the substrate structure 114 of the 3D die stack and the back side ( Figure 12 the upper side in Figure 10 ). The 3D IC structure 15 includes a dual-sided power supply structure (having a BSPDN-type high-power die 100 as shown in the embodiments of Figure 11 ), and an upper substrate 146 that is located above and electrically and thermally coupled to the low-power die 106. The upper substrate 146 is electrically connected to the power supply connection line 148, which is then electrically connected to the substrate structure 114 for power transmission and signal transmission. In some embodiments, the upper substrate 146 is an HTC, LCTE diamond-based interposer having vias and RDLs on both sides, or an HTC, LCTE metal-coated (e.g., copper-invar-copper (CIC)) interposer having vias and RDLs on both sides. Additionally, the spacer 144A can be an HTC TIM placed between the heat spreader 140 and the upper substrate 146 to assist in heat dissipation. For example, as shown in Figure 11 , the low-power die 106 can optionally include a plurality of diamond-based interposers 106C that have vias between two adjacent dies 106A or between die 106A and die 106B. Figure 11 The low-power die 106 in can be a combination of a DRAM die (e.g., die 106A) and a control IC (e.g., die 106B). In some embodiments, the BSPDN-type high-power die 100 can also be changed to use an FSPDN-type. Although high-power dies and low-power dies are mentioned here, they can be used interchangeably in the 3D IC structure 15. This also applies to all other 3D IC structures disclosed in this disclosure.

[0089] Referring to Figure 12 , in some embodiments, the HTC heat spreader 140 in the 3D IC structure 16 can be disposed on the first surface 114A of the substrate structure 114 and the back side (upper side) of the high-power die 100 and thermally coupled thereto. The heat spreader 140 can absorb heat from the high-power die 100 by means of the spacer 144B. The spacer 144B can be an HTC TIM. Another spacer 144 can be an HTC TIM at the interface between the substrate structure 114 and the support portion 142 of the heat spreader 140. The 3D IC structure 16 can be liquid immersion cooled through the openings (not shown) in the heat spreader, the open vias in the first interposer 102, and the TEP 116 in the substrate structure 114. In some embodiments, an HTC encapsulant can be used to seal the interconnect structure based on, for example, microbumps, solder bumps, and / or solder balls. In some embodiments, the second interposer 104 is an LTC interposer to prevent heat energy from being transferred from the high-power die 100 to the underlying low-power die 106. The second interposer 104 can also have a plurality of air cavities under some hot spots of the high-power die 100, which helps to minimize the thermal impact on the low-power die 106 during direct liquid cooling of the chip (since the thermal conductivity of air is only about 0.03 W / m.K), or allows the liquid coolant to approach the bottom of the high-power die 100 during liquid immersion cooling. The first interposer 102 can be a silicon interposer with vias and RDL, an LTC interposer, or an HTC interposer. Alternatively, the low-power die 106 can be bonded to the first interposer 102 (or bonded to a laminated substrate, such as if the first interposer 102 is a laminated substrate) and the second interposer 104, or only bonded to the second interposer 104. In some embodiments, the low-power die 106 can also be pre-assembled in a molded fan-out layer before bonding the low-power die 106 to the first interposer 102. In some embodiments, in addition to the heat spreader 140, the 3D IC structure 16 can also be selectively molded and coated with a conformal coating (such as parylene) to prevent short circuits or corrosion during liquid wetting.

[0090] In some low-end applications, it may not be necessary to implement an LTC interposer or a silicon interposer under the low-power die 106. However, when considering both the heat dissipation of the low-power die 106 and the thermal impact from the high-power die 100, a high-TC interposer (such as a diamond-based interposer) can be inserted between the DRAM dies in the low-power die 106 to assist in heat dissipation, while the LTC interposer above the low-power die 106 can minimize the thermal impact.

[0091] In some embodiments, a heat pipe can be used to replace the heat spreader 140, especially the part above the high-power die 100.

[0092] In some embodiments, the heat spreader 140 in the 3D IC structure 16 may include a plurality of liquid channels. The heat spreader has liquid channels and fins inside, and can take away the heat generated by the high-power die 100 through the flow of the liquid coolant. In addition, since the coolant does not directly contact the die of the 3D IC structure 16, there is no need to use a conformal layer to coat the 3D IC structure.

[0093] Referring to Figure 13 , in some embodiments, liquid immersion cooling is used to cool the 3D IC structure 17. As Figure 13 shown, the liquid coolant (which can be water or a dielectric coolant) can enter the built-in channel of the distribution unit 141 for distributing the impinging flow coolant above the high-power die 100 and impinge on the high-power die 100, the second interposer 104, the low-power die 106, the bridging die 107, the first interposer 102, and the substrate structure 114 below. The liquid coolant is restricted and guided by the holes or openings in the support portion 142 provided on the substrate structure 114, and this support portion supports the distribution unit 141. The liquid coolant is then discharged from the opening 143 in the support portion 142 to complete the heat exchange process. In some alternative embodiments, after the liquid coolant enters the built-in channel of the distribution unit 141, it can impinge on the high-power die 100 at a specific flow rate through one or more micro-nozzles 145 to improve the cooling efficiency.

[0094] Generally speaking, as Figures 10 to 13 shown and further referring to Figure 5C , the 3D IC structure is compatible with a variety of cooling technologies, at least including air cooling, liquid cooling directly to the chip, and liquid immersion cooling. In addition, the efficiency of liquid cooling can be improved by using coolant jets / microjets for the high-power die (i.e., the processor) located at the top of the 3D IC structure, and / or by attaching a heat spreader plate to the back of the high-power die 100 using an HTC TIM and cooling the heat spreader plate with coolant jets.

[0095] In addition, referring to Figure 14 and 15 , the above cooling technologies for 3D IC structures can also be applied to 2.5D IC structures to improve the thermal performance. For example, as Figure 14As shown, the high-power die 100 and the low-power die 106 are both disposed on the first interposer 102, and the high-power die 100 and the low-power die 106 are both in contact with and thermally coupled to the inner side of the heat spreader 140 for heat dissipation. In some embodiments, the spacer 144B and the spacer 144C may be HTC TIMs respectively placed between the heat spreader 140 and the upper side of the high-power die 100 or the low-power die 106. Another spacer 144, which can also be an HTC TIM, can be inserted between the heat spreader 140 and the substrate structure 114. In another embodiment, as Figure 15 shown, the interposer (i.e., the first interposer 102) supporting the high-power die 100 and the low-power die 106 is a composite interposer. Since the material combinations forming the interposer substrate are different, its thermal conductivity may be different in different regions. For example, the first interposer 102 may include a first portion 102A made of LTC and LCTE materials and a second portion 102B made of HTC and LCTE materials. The high-power die 100 is disposed on the second portion 102B containing HTC material to enhance heat dissipation, while the low-power die 106 is disposed on the first portion 102A containing LTC material to block the heat from the high-power die 100.

[0096] Figure 16A And 16B illustrates some examples of the composite interposer. As shown, a single composite interposer may have more than one first portion (e.g., labeled 102A) and / or more than one second portion (e.g., labeled 102B). The material distribution with the desired thermal conductivity depends on the position of the die. In some embodiments, more than two materials with different thermal conductivities may be included in a single composite interposer. In Figure 16C the illustrated example, the first interposer 102 and the second interposer 104 are both composite interposers. In the 3D IC structure 20, the high-power die 100 and the low-power die 106 are both disposed on the second portions (labeled 102B and 104B) that may include HTC material, while the first portions (labeled 102A and 104A) of these composite interposers are exposed.

[0097] Figures 17A to 17F illustrates some embodiments of a method for forming a composite interposer according to the disclosure of the present disclosure. Figure 17A shows the provided substrate 500. The substrate 500 can be a silicon substrate or other suitable substrate, depending on the requirements of the composite interposer. As Figure 17B shown, a cavity 502 is formed on the upper side of the substrate 500. Then, as Figure 17CAs shown, a seed layer 504 is formed on the upper side of the substrate 500, covering the surface of the cavity 502. The material of the seed layer 504 may include iridium (Ir). In addition, there are some multi-layer substrates with an iridium buffer layer deposited on metal oxide layers on silicon substrates (SrTiO 3 / Si and YSZ / Si), oxide substrates (such as MgO and more recently sapphire), and KTaO 3 have been developed. Then, referring to Figure 17D , the seed layer 504 on the original surface of the substrate 500 is removed through a patterning process. As Figure 17E shown, a material 506 different from the substrate 500 is deposited on the substrate 500. For example, a CVD diamond deposition operation is performed to fill the cavity 502 with diamond, followed by a planarization operation. Referring to Figure 17F , the substrate 500 is thinned from its lower side to expose the bottom surface of the diamond. Next, other intermediate layer process steps can be performed, such as forming vias 508 in the substrate 500, forming RDL 510 on both sides of the substrate 500, and forming bonding structures 512 such as solder bumps or micro-bumps.

[0098] In some embodiments, Figure 16C the substrate structure 114 in Figure 3 may include a thermally enhanced portion 116 (TEP 116) in the region below the high-power bare die 100, as previously Figure 18A shown. Referring to

[0099] , in some embodiments, the TEP 116 in the 3D IC structure 21 includes a recess 112A that recesses from the second surface 114B of the substrate structure 114. In some embodiments, the depth D2 of the recess 112A is at least 50% of the thickness of the other portion 117 of the substrate structure 114. Above the recess 112A, there are preferably thermal vias and planes, and it can be used as a bottom channel for the fluid coolant 190 to pass through to improve the cooling efficiency. In other embodiments, the recess 112A can be used to embed HTC heat dissipation elements. Figure 18B Referring to Figure 18BAs shown, the 3D IC structure 22 includes an organic coating layer 180 (see the enlarged portion), which can be parylene or other suitable materials, covering multiple exposed surfaces such as the substrate structure 114, the low-power die 106, the high-power die 100, the first interposer 102, the second interposer 104, and the sidewalls of the substrate structure 114 defining the opening 112B.

[0100] In Figure 18A and 18B the illustrated embodiment, the recesses and openings of the TEP 116 in the substrate 114 can result in different geometries from other parts of the substrate structure 114 ( Figure 18A 117 in Figure 18B and Figure 18A 114C in

[0101] Referring to Figure 19A , in some embodiments, the TEP in the 3D IC structure 23 includes an opening 112B, similar to Figure 18B the illustrated embodiment. However, in Figure 19A the embodiment shown in Figure 19A the opening 112B is filled with an HTC material 170. In some embodiments, the upper and lower surfaces of the HTC material 170 are coplanar with the first and second surfaces of the substrate structure 114, respectively. That is,

[0102] Referring to Figure 19B , in some embodiments, the TEP in the 3D IC structure 24 not only includes the HTC material 170 but also has a plurality of conduction vias 172 penetrating the HTC material 170. Figure 19A and Figure 19B One difference between the illustrated embodiments is the ability to form electrical connection structures in the TEP of these 3D IC structures.

[0103] In addition, in some embodiments, the substrate structure 114 can not only include a substrate having a plurality of geometric features (such as recesses and openings), but can also be a tiled substrate composed of multiple pieces connected by an interconnect bridging structure. For example, as Figure 20A the top view in Figure 20BAs shown in the corresponding side view of the encapsulation structure in [reference], the substrate structure 114 may have a plurality of substrate units 120 that are physically separated from each other. The interconnect bridging structure 122 is used to electrically or optically connect adjacent substrate units 120. In some embodiments, the length L1 of the substrate unit 120 is greater than the length L2 of the bridging structure 122, which forms a plurality of tiny or very narrow (width less than 1 mm) channels 124 between adjacent substrate units 120, and these channels may not be completely covered by the bridging structure 122. Therefore, the channels 124 allow the liquid coolant to rise above the first surface 114A of the substrate structure 114 through the channels 124. By using a tiled substrate as the substrate structure 114, the channels 124 can function as fluid channels to improve the liquid immersion cooling efficiency.

[0104] In some embodiments, the bridging structure 122 is a silicon interconnect bridge that can electrically (and / or optically) connect two adjacent substrate units 120. In some embodiments, a plurality of through-silicon vias (TSVs) and RDLs may be included on both sides of the bridging structure 122. In other embodiments, the bridging structure 122 may be installed on the lower side of adjacent substrate units 120, rather than only on the upper side, as Figure 20B shown. The bridging structure 122 may also be partially located under the high-power die 100 and / or the low-power die 106.

[0105] In some embodiments, the tiled substrates can be interconnected through silicon bridges. The processes used include depositing a non-conductive paste (NCP) on the silicon bridge 122, using, for example, thermo-compression bonding (TCB) to bond the bridge to one of the substrate units 120, curing the NCP, and then repeating the above steps to bond the bridge to the second substrate unit 120.

[0106] Figure 21A and 21B illustrate examples of two tiled substrates, which involve an interconnect bridging interposer 123A between two adjacent substrate units 120. The bridging interposer 123A is substantially flush with the two adjacent substrate units 120. In some embodiments, the bridging interposer 123A includes one or more TSVs 172B that traverse the thickness of the bridging substrate 174, and the bridging substrate 174 can be a silicon substrate. In some embodiments, there are two mold through vias (TMVs) 172A that laterally surround the mold compound 173 next to the bridging interposer 123A, but are electrically isolated from the bridging interposer 123A. In some embodiments, one side of the bridging interposer 123A may include RDL 176A. In other embodiments (such as Figure 21BAs shown, two opposite sides of the bridging interposer 123A may include RDL 176A and RDL 176B. The TSV 172B traverses the thickness of the bridging interposer 123A and connects RDL 176A and RDL 176B.

[0107] Referring Figures 22A to 22C to, which illustrates some examples of using a flexible printed circuit (FPC) 123C as an interconnect bridging structure. The FPC 123C may include a film made of polyimide or other types of flexible materials. As Figure 22A shown, the FPC 123C may be mounted on the same side of the adjacent substrate unit 120, while as Figure 22B shown, the FPC 123C may also be mounted on the opposite sides of the adjacent substrate units 120. Therefore, in different embodiments, the FPC 123C is connected to the same side or the opposite sides of the adjacent substrate units. In addition, as Figure 22C shown, the FPC 123C may include a window opening 125 and a bent lead 127 formed by a lead forming operation after forming the window opening 125. The bent lead 127 may extend into the window opening 125 and contact a bonding structure (such as a surface treatment, a gold bump or a micro bump 129 exposed from the window opening 125). In some embodiments, the FPC 123C is electrically connected to the adjacent substrate unit 120 or the IC through, for example, the micro bumps 129. Generally, each micro bump 129 is sealed.

[0108] Referring Figure 23 to, in some embodiments, a hybrid bridge structure 160 (HBS) may be utilized to bridge adjacent substrate units 120. The HBS 160 may be formed by using a combination of a silicon bridge and an FPC. In some embodiments, the Figure 23 bridging structure 122 is mounted on one side of the FPC 123C through a plurality of micro bumps 129 or gold bumps, wherein the FPC 123C further includes a base film 161 (such as polyimide) to achieve finer wiring. A plurality of metal pads 162 (such as copper pads) are provided on the surface of the base film 161 to electrically connect the substrate unit 120 to the hybrid bridge structure 160 through the micro bumps 129. In some embodiments, a solder mask 163 is disposed between the micro bumps 129 and the metal pads 162 on the connection path between the base film 161 and the substrate unit 120. The solder mask 163 may have a desired pattern to define the electrical connection positions between the solder bumps 129 and the metal pads 162. In some embodiments, the bridging structure may also include active functions.

[0109] Referring Figures 24A to 24C, in some embodiments, an edge interconnect bridging structure 123B can be used to connect substrate units 120. The edge interconnect bridging structure 123B includes extended metal leads or extended metal / passivation leads for enhancing structural integrity, both of which include appropriate surface processing for subsequent bonding. In these embodiments, the edge interconnect bridging structure 123B can be in the form of a silicon bridging structure that connects adjacent substrate units 120 through the first surface 114A of the substrate structure 114 (for the first surface 114A, please refer to Figure 3 ). As shown in Figures 24A to 24C , each edge interconnect bridging structure 123B includes a T-shaped profile from a cross-sectional perspective, and the edge interconnect bridging structure 123B further includes two edge pads 164 made of conductive material, which are located on opposite sides of the edge interconnect bridging structure 123B. The edge pads 164 of the edge interconnect structure are electrically connected to the edge pads 165A or extended edge pads 165B of adjacent substrate units 120. Microbumps 129 can be used to bond the edge pads 164 of the edge connection bridging structure 123B and the substrate unit 120, as well as the edge pads 165A (or extended edge pads 165B), respectively. In some embodiments, the microbumps 129 are sealed ( Figures 24A to 24C not shown).

[0110] Figures 25A to 25E illustrates a method for forming an edge interconnect bridging structure according to some embodiments of the disclosure of the present disclosure. As shown in the figure, a substrate 1201 without edge pads is patterned from one of its sides to form one or more cavities 210. Then, a metal layer 212 and a passivation layer 214 can be sequentially formed in the cavities 210 through a deposition operation. The stacked metal layer 212 and passivation layer 214 are patterned to expose a part of the upper surface of the substrate 1201. Refer to Figure 25C , after depositing and patterning the mask 216 and removing a part of the metal layer 212 and the passivation layer 214 to expose the bottom surface of the cavities 210, these cavities 210 are further patterned to form Figure 25D the cavities 210A shown in Figure 25D and 25E . As shown in

[0111] , the mask 216 is removed, and the substrate 1201 is thinned and planarized from the back side. After dicing the die, each substrate 1201 with the metal layer 212 can serve as an edge interconnect bridging structure at its corners. In some other instances, the formation of the passivation layer 214 can be omitted.

[0111] Referring to Figure 26A and 26B , in some embodiments, the bilateral interconnect bridging structure 122 is connected to adjacent substrate units 120, high-power die 100, and / or low-power die 106. As shown in Figure 26AAs shown, one side of the bridging structure 122 is connected to both the substrate unit 120 and the low-power die 106 simultaneously. Among them, the first side 122A of the bridging structure 122 is electrically connected to the low-power die 106 through the micro-bumps 129, and the second side 122B of the bridging structure 122 is electrically connected to the substrate unit 120 through the micro-bumps 129. The low-power die 106 is further electrically connected to the substrate unit 120 through solder bumps or micro-bumps 130. On the other side of the bridging structure 122, the first side 122A of the bridging structure 122 is electrically connected to the high-power die 100 through the micro-bumps 129, and the second side 122B of the bridging structure 122 is electrically connected to another substrate unit 120 through the micro-bumps 129. The high-power die 100 is further electrically connected to another substrate unit 120 through solder bumps or micro-bumps 130. In Figure 26A and Figure 26B In the embodiments shown, some substrate units 120 may have recesses generated by standard substrate processes (see Figure 26A ).

[0112] The substrate structures in these embodiments can be extra-large, ultra-fine pitch hybrid substrates with dimensions exceeding wafer level, which are formed by splicing smaller known good substrates (i.e., substrate units 120) together using interconnect bridges. This is applicable to a wide range of applications, including HPC, data centers, AI, networking, mobile phones, 5G / RF, and power electronic components. By using substrate units and bridging structures, more dies (including high-power die 100 and low-power die 106) can be closely mounted without the need for a single large, high-layer, fine-pitch laminated substrate that is difficult to manufacture with high yield.

[0113] Referring to Figures 27A to 27D , in some embodiments, the 3D IC structure may include at least one electronic device 300 that is fully or partially embedded or mounted on the substrate structure 114, the first interposer 102, the high-power die 100, the second interposer 104, the low-power die 106, and / or the bridging die 107 connecting the first interposer 102 and the second interposer 104. Figure 27A With 27B FIG. shows an example of a 3D IC structure including a substrate structure 114 interconnected by a bridging structure 122. The available positions of the electronic device 300 are marked by dashed lines in these figures. The electronic device 300 may include a fully integrated voltage regulator, a voltage regulator, a voltage driver, a magnetic component, a transformer, an inductor, a capacitor, an integrated passive device, or a combination thereof to achieve vertical power transmission for applications such as HPC, data centers, AI, and other high-performance applications.

[0114] The foregoing describes the structures of several embodiments such that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described in the present disclosure. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A 3D integrated circuit package, comprising: a substrate structure having a first surface and a second surface opposite to the first surface; A high-power bare die disposed above the substrate structure; A low-power bare die disposed above the high-power bare die; A first interposer disposed between the first surface of the substrate structure and the high-power die; as well as A second interposer is provided between the high-power bare core and the low-power bare core, The substrate structure includes a thermal enhancement portion located below the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure.

2. The package of claim 1, wherein the thermally enhanced portion comprises a recessed portion recessed from the second surface of the substrate structure, and a depth of the recessed portion is at least 50% of a thickness of other portions of the substrate structure.

3. The package of claim 1, wherein the thermal enhancement portion includes an opening that allows a fluid to pass through the opening and rise above the first surface of the substrate structure.

4. The package of claim 1, wherein the thermal enhancement portion comprises an opening filled with a high thermal conductivity material, and a top surface and a bottom surface of the high thermal conductivity material are coplanar with the first surface and the second surface of the substrate structure, respectively. 5 . The package of claim 1 , wherein the substrate structure comprises a plurality of substrate units physically separated from each other, and the thermal enhancement portion comprises a bridge structure for electrically or optically connecting adjacent substrate units.

6. The package of claim 5, wherein the bridging structure comprises a bridging interposer that is substantially flush with the adjacent substrate units, a silicon bridging structure that connects surfaces of the adjacent substrate units constituting the first surface of the substrate structure, a flexible printed circuit that connects the same or opposing surfaces of adjacent substrate units, or a combination thereof.

7. The package of claim 5, wherein in a top view, the heat enhancement portion further comprises a channel disposed between adjacent substrate units to allow fluid to rise through the channel to above the first surface of the substrate structure.

8. The package of claim 1, wherein the thermal conductivity of the first interposer and the second interposer is substantially greater than about 1,500 W / mK.

9. The package of claim 1, further comprising: An organic coating covers a plurality of exposed surfaces of the substrate structure, the low-power die, the high-power die, the first interposer, the second interposer, and sidewalls of the substrate structure defining the opening.

10. A 3D integrated circuit package, comprising: a substrate structure having a first surface and a second surface opposite to the first surface; A low-power bare die disposed above the substrate structure; A first high-power bare die disposed above the low-power bare die; A first interposer disposed between the first surface of the substrate structure and the low-power die; as well as A second interposer is provided between the first high-power bare core and the low-power bare core, The substrate structure includes a thermal enhancement portion located below the first high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure.

11. The package of claim 10, wherein the first high-power die is a monolithic integrated circuit device comprising a plurality of cooling fins on a back side of the first high-power die.

12. The package of claim 10, wherein a first portion of the second interposer projected below the first high-power die has a first thermal conductivity greater than a second portion of the second interposer not projected below the first high-power die.

13. The package of claim 10, wherein a thermal conductivity of the first interposer is greater than a thermal conductivity of the second interposer.

14. The package of claim 10, wherein a thermal conductivity of the first interposer is equal to or less than a thermal conductivity of the second interposer.

15. The package of claim 10, wherein a planar area of ​​the second interposer is smaller than a planar area of ​​the first interposer.

16. The package of claim 10, wherein the thermal enhancement portion comprises an opening filled with a high thermal conductivity material, and a top surface and a bottom surface of the high thermal conductivity material are coplanar with the first surface and the second surface of the substrate structure, respectively.

17. The package of claim 10, further comprising: at least one third intermediary layer disposed between the first intermediary layer and the second intermediary layer; at least one second high-power bare die disposed between the third interposer and the second interposer; and At least a plurality of bridge bare cores are arranged beside the second high-power bare core or the low-power bare core.

18. A substrate structure comprising: a plurality of substrate units separated from each other; and A bridge structure is used to electrically connect adjacent substrate units, wherein the bridge structure includes a first side and a second side opposite to the first side, and at least one of the first side or the second side is electrically connected to an adjacent substrate unit or an integrated circuit through a microbump or an interconnection layer.

19. The substrate structure of claim 18, wherein in a top view, a length of the bridge structure is smaller than a length of each of the substrate units.

20. The substrate structure of claim 18, wherein the bridge structure further comprises: interconnect layers on the first side and the second side; and A via extends through the thickness of the bridge structure and connects the interconnect layers.

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