Single-chip FPGA-based signal frequency measurement method and device, FPGA and medium

Abstract

The application discloses a signal frequency measurement method and device based on a single FPGA, an FPGA and a medium, and relates to the technical field of electronic measurement. The method comprises the following steps: when the rising edge of a start signal arrives, the first integer period time and the first residual time are measured; the first residual time represents the time from the first rising edge of the logic signal to the next rising edge of the clock signal; according to the first integer period time and the first residual time, the time parameter in the logic signal is determined; the time parameter represents the time from the rising edge of the start signal to the first rising edge of the logic signal; and according to the time parameter, the frequency of the logic signal is calculated. The method can use a single FPGA to perform all time measurements, realize high-precision frequency measurement, and does not need additional chips, thereby improving the integration of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic measurement technology, in particular to a signal frequency measurement method and device based on a single FPGA, an FPGA and a medium. BACKGROUND

[0002] In many fields of modern technology, accurate frequency measurement is a crucial technology. For communication systems, radio frequency calibration is the key to ensuring stable and accurate information transmission, which directly affects the performance and reliability of the communication system. In the field of audio processing, tone analysis relies on accurate frequency measurement to achieve accurate identification and adjustment of sound signals. In medical devices, such as heart rate detectors, the core function is to provide important physiological indicator data by accurately measuring heart rate, which is crucial for medical diagnosis and treatment. In the industrial control field, motor speed detection requires frequency measurement, which is directly related to the efficiency of the production process and the safe operation of the equipment. As can be seen, accurate frequency measurement is not only the basis for the normal operation of these systems, but also an important support for performance improvement and safety guarantee.

[0003] In related technologies, there are various schemes for measuring frequency. The first scheme is the window period counting method, but the window length is not an integer multiple of the signal period, which will have a measurement period error. The second scheme is to use an analog-to-digital converter (ADC) to collect the signal to be measured, and obtain the frequency signal by performing Fourier transform on the signal, and then obtain the signal frequency. However, to obtain a high frequency resolution, a long time signal needs to be collected, and a large amount of computing resources is required, resulting in poor real-time performance. The third scheme is to combine a field programmable gate array (FPGA) chip, a time-to-digital converter (TDC) chip and a central processing unit (MCU) chip to test the signal period, and then convert it into a frequency signal. However, this method has poor integration, and the precision of ordinary commercial TDC chips is difficult to reach 10ps, making it difficult to measure very low frequency signals and pulse signals. SUMMARY

[0004] Therefore, it is necessary to provide a signal frequency measurement method and device based on a single FPGA with high integration, accurate frequency measurement and wide application scenarios.

[0005] A signal frequency measurement method based on a single FPGA is applied to an FPGA, and the method comprises:

[0006] Obtaining logic signals corresponding to the start signal, clock signal, and measurement signal;

[0007] When the rising edge of the start signal arrives, measure the Integer cycle time and The remaining time; The integer cycle time represents the rising edge of the clock signal including the rising edge of the start signal and the first edge of the logic signal. An integer number of clock cycles of a rising edge; the The residual time characterizes the The time from the first rising edge to the next rising edge of the clock signal;

[0008] According to Integer cycle time and The residual time determines the time parameter of the logic signal ; The time parameter Characterizes the period from the rising edge of the start signal to the first edge of the logic signal The time of the rising edge;

[0009] according to The time parameters , calculate the frequency of the logic signal; wherein, is a positive integer greater than 0, is a positive integer greater than 1.

[0010] In the above scheme, the measurement Residual time, including:

[0011] right Carry chains are used to calibrate the code density, and calibration values ​​of each carry chain are stored in sequence; the delay of the carry chain is greater than the clock period of the clock signal;

[0012] The logic signal A rising edge is input to the first trigger, and when the next rising edge of the clock signal arrives, the Q value of the first trigger is recorded in the link length of the carry chain;

[0013] Calculate the first Remaining time.

[0014] In the above solution, each of the carry chains is configured with a corresponding second flip-flop. When the next rising edge of the clock signal arrives, the second flip-flop is used to store the Q value of the first flip-flop transmitted along the carry chain.

[0015] The method further comprises:

[0016] After determining the first residual time, a reset signal is sent to the first trigger based on the third trigger and the second trigger of the first carry chain.

[0017] In the above solution, the frequency of the logic signal is calculated according to the time parameters, and the calculation comprises:

[0018] The other time parameters are subtracted from the first time parameter respectively, and a time difference value about the logic signal is obtained; the time difference value represents the time from the first rising edge to the second rising edge of the logic signal;

[0019] The time difference value is averaged to obtain the frequency of the logic signal.

[0020] In the above solution, the measurement signal has multiple corresponding logic signals, and the method further comprises:

[0021] The frequency of each of the logic signals is averaged to obtain the frequency of the measurement signal.

[0022] In the above solution, the multiple logic signals corresponding to the measurement signal are converted via a multiple comparator circuit.

[0023] A signal frequency measurement device based on a single FPGA, applied to an FPGA, the device comprising:

[0024] An acquisition module, configured to acquire a start signal, a clock signal, and a logic signal corresponding to a measurement signal;

[0025] A measurement module, configured to measure an integer period time and a residual time when a rising edge of the start signal arrives; the integer period time represents an integer number of clock periods containing the rising edge of the start signal and the first rising edge of the logic signal in the clock signal; the residual time represents the time from the first rising edge of the logic signal to the next rising edge of the clock signal. A determination module, configured to determine the first

[0026] residual time according to the integer period time and the residual time.​​​​​​​​​ Integer cycle time and The residual time determines the time parameter of the logic signal ; The time parameter Characterizes the period from the rising edge of the start signal to the first edge of the logic signal The time of the rising edge;

[0027] Calculation module, used to The time parameters , calculate the frequency of the logic signal; wherein, is a positive integer greater than 0, is a positive integer greater than 1.

[0028] An FPGA includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps of the signal frequency measurement device based on a single-chip FPGA are realized.

[0029] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the above-mentioned signal frequency measurement device based on a single-chip FPGA.

[0030] The above-mentioned signal frequency measurement method, device, FPGA and medium based on single-chip FPGA measure the frequency of the first Integer cycle time and The remaining time, according to Integer cycle time and Residual time, determine the time parameters in the logic signal , and then according to Time parameters The frequency of the logic signal is calculated. This method enables high-precision frequency measurement, effectively handling both integer and non-integer cycles. This significantly reduces the errors that may exist in traditional frequency measurement methods and improves the overall accuracy of the signal frequency. Furthermore, this measurement method eliminates the need for additional chips, improving system integration and simplifying the hardware architecture, making it suitable for a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a flow chart of a signal frequency measurement method based on a single-chip FPGA in one embodiment;

[0032] Figure 2 Schematic diagram of waveforms of a clock signal, a start signal, and a logic signal in one embodiment;

[0033] Figure 3 1 is a flow chart of a residual time measurement process in one embodiment;

[0034] Figure 4 a schematic diagram of a residual time measurement circuit inside an FPGA in an embodiment;

[0035] Figure 5 a structural block diagram of a signal frequency measurement device based on a single-chip FPGA in an embodiment. DETAILED DESCRIPTION

[0036] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0037] The implementation details of the technical solutions of the embodiments of the present application are described in detail below.

[0038] In an embodiment, as shown in Figure 1 a signal frequency measurement method based on a single-chip FPGA is provided, which is applied to an FPGA and can include the following steps:

[0039] Step S101, acquiring a start signal, a clock signal and a logic signal corresponding to a measurement signal.

[0040] Here, there is a signal processing path inside the FPGA, which can acquire a start signal (start signal), a clock signal (clk signal) and a measurement signal (SIGNAL_IN) to be measured.

[0041] The start signal can come from an external trigger input or be generated inside the FPGA, which is used to indicate the starting moment of measurement and instruct the FPGA to perform measurement. The frequency of the clock signal is set to 500MHz, and the clock period is 2ns. The clock source comes from an external phase-locked loop (PLL) or rubidium atomic clock. In actual application, the start signal is latched through the internal register of the FPGA, at which time the start signal is synchronized with the clock signal, which means that when the start signal arrives, the clock inside the FPGA is stable, which can ensure accurate signal capture.

[0042] The measurement signal can be a sinusoidal signal or a TTL (Transistor-Transistor Logic) square wave signal. After conversion by the comparator circuit, the measurement signal is converted into a logic high-low level signal. When the signal amplitude is greater than the preset trigger threshold, the comparator outputs logic 1; when the signal amplitude is less than the preset trigger threshold, the comparator outputs logic 0. The logic signal is used as the input of subsequent frequency measurement, which is convenient for digital circuit processing and measurement.

[0043] Step S102: When the rising edge of the start signal arrives, measure the Integer cycle time and Remaining time.

[0044] like Figure 2 As shown, Figure 2 The waveform diagram of the clock signal, start signal and logic signal is shown below. Figure 2 , the frequency measurement logic is described in detail. When the FPGA detects the rising edge of the start signal ( Figure 2 The measurement logic is triggered when the rising edge of the logic signal is detected (e.g., the c edge in the figure), thus entering the signal period measurement phase. The measurement logic is based on a 500MHz clock signal and records the following two parts of time for each rising edge of the logic signal:

[0045] (1) Integer cycle time By counting the clock signal, we can get the time from the rising edge of the start signal to the first edge of the logic signal. The integer cycle time reflects the integer number of clock cycles between the start signal and each rising edge of the logic signal. Assuming the clock period is period, the integer cycle time Expressed as ,in is the number of complete clock cycles. Figure 2 The second rising edge of the logic signal ( Figure 2 Take the e-edge in the figure as an example, , from the start signal c edge to the logic signal e edge includes 8 complete clock cycles, thus obtaining an integer cycle time .

[0046] (2) Remaining time In the logic signal After a rising edge occurs, measure its time deviation relative to the next rising edge of the clock signal. Figure 2 As shown, Figure 2 The second rising edge in Figure 2 Take the e-edge in the figure as an example, , residual time It refers to the time between the e-edge of the logic signal and the b-edge of the clock signal. This residual time is less than one cycle of the clock signal, reflecting the incomplete part of the rising edge of each logic signal relative to the integer cycle time.

[0047] By repeating the above steps, the integer cycle time and residual time corresponding to multiple rising edges in the logic signal can be recorded.

[0048] In one embodiment, Figure 3 As shown,Figure 3 The residual time measurement process is shown, which may include the following steps:

[0049] Step S201: The code density is calibrated for each carry chain, and the calibration value of each carry chain is stored in sequence.

[0050] like Figure 4 As shown, Figure 4 A schematic diagram of the residual time measurement circuit within an FPGA is shown. This residual time measurement circuit is essentially an adder carry chain, which efficiently implements multi-bit addition operations with only signal transmission. In this embodiment, the carry chain consists of a series of flip-flops and a logic array to accurately measure signal propagation delays. The total delay of the carry chain is greater than the clock period, period, to meet the requirements for residual time measurement. The specific design can be adjusted by adjusting the number of flip-flops and their delay characteristics.

[0051] Before using the carry chain for measurement, it is necessary to calibrate the code density to obtain the delay time of each carry chain node. The calibration method can be to perform a delay test on each trigger with a known input signal and record the calibration value. After the calibration is completed, the calibration value of each carry chain is stored in the memory RAM in sequence. Among these calibration values, the maximum calibration value is , which represents the maximum delay of the entire carry chain.

[0052] In practical applications, the residual time measurement circuit may include carry chains (where N is a positive integer greater than or equal to 1), that is, there are a total of carry chains nodes, and the calibration value of each node is stored in RAM. The RAM address is determined by the node number. Decision. Address One-to-one correspondence with the position of the trigger in the carry chain, the calibration value corresponding to the node can be quickly obtained through a simple address query .

[0053] Step S202: the logic signal A rising edge is input to the first flip-flop, and when the next rising edge of the clock signal arrives, the link length of the Q value of the first flip-flop transmitted in the carry chain is recorded.

[0054] In the logic signal When a rising edge arrives, the signal will be input to Figure 3The first flip-flop in the circuit has data 1 input to its D terminal. The first flip-flop is set to edge-triggered. After triggering, the Q output of the first flip-flop is 1, and this Q value will be transmitted along the carry chain. When the next rising edge of the clock signal arrives, the transmission on the carry chain ends. When the transmission ends, the length of the link in which the Q value of the first flip-flop is transmitted in the carry chain is recorded. The link length actually corresponds to the number of nodes that the Q value passes through in the carry chain. Recording this link length can reflect the overall time it takes for the Q value to propagate in the carry chain, and the propagation of the Q value is determined by the first The link is triggered by a rising edge and ends when the next rising edge of the clock signal arrives, so the link length actually records the residual time.

[0055] In one embodiment, Figure 4 As shown, a row of second flip-flop arrays is set below the carry chain, where each carry chain is configured with a second flip-flop. After the Q output of the first flip-flop is 1, the value will be passed forward along the structure of the carry chain, passing through several pre-configured second flip-flops. When the next rising edge of the clock signal arrives, the second flip-flop array will latch the current state of the carry chain into the corresponding second flip-flop. At this moment, the number of nodes in the carry chain with a state of 1 is is accurately recorded, i.e. The Q value latched by the second flip-flop is 1, so that the link length can be recorded by the second flip-flop.

[0056] Step S203: Calculate the first Remaining time.

[0057] Here, according to the link length , FPGA queries the corresponding node number from RAM Calibration value , Indicates the distance from the start of the carry chain to the node The total delay directly reflects the time it takes for the signal to propagate. Defined as the first logical signal The delay between the rising edge of the first clock signal and the rising edge of the next clock signal is a critical time period, which represents the actual delay experienced by the signal from being triggered to clock synchronization. The calculation formula is:

[0058]

[0059] in, It is the maximum calibration value of the entire carry chain, representing the maximum potential delay in the link and providing a normalized reference value. and The ratio of the link length The delay is converted into the relative time of the clock cycle, that is, Indicates link length The ratio of the maximum delay time can eliminate the absolute difference in delay between different nodes and obtain a standardized relative ratio. Then multiply this ratio by the FPGA clock cycle to calculate The actual time value.

[0060] In one embodiment, Residual time After the calculation is complete, the system generates a reset signal based on the output states of the second and third flip-flops in the first carry chain. This reset signal is used to clear the state of the first flip-flop in preparation for the next measurement cycle. This reset signal is passed to the reset terminal of the first flip-flop. When the reset signal is high, the first flip-flop is reset and the Q output state is cleared, causing the Q output terminal to change from 1 to 0, ensuring that the first flip-flop does not affect the new signal input state in subsequent measurements.

[0061] Specifically, if Figure 4 As shown, the generation of the reset signal depends on the third flip-flop and the second flip-flop of the first carry chain (i.e. Figure 4 The output states of the two series-connected flip-flops (FF2 in the figure). Among them, the D port of the third flip-flop is connected to the Q port of the second flip-flop FF2. Therefore, before the next rising edge of the clock signal arrives, the Q output state of the first flip-flop will be transmitted to the first carry chain. Based on this, when the next rising edge of the clock signal arrives, the second flip-flop FF2 will latch the state of the carry chain, so that the Q of the second flip-flop FF2 is 1. At the same time, since the input connection of the third flip-flop comes from the Q end of the second flip-flop FF2, the third flip-flop has not yet sampled a new input value in the current clock cycle, so the Q output state of the third flip-flop remains in the previous state, that is, Q=0, so its inverted output terminal is 1. In this case, the third flip-flop The Q port of the second flip-flop FF2 is connected to a logic device (such as a logic AND gate). Since the two inputs of the logic AND gate are both high, the reset signal output is valid (1), thereby triggering the reset operation of the first flip-flop. The reset signal lasts for one clock cycle until the next clock rising edge arrives. The third flip-flop samples the Q=1 state of the second flip-flop FF2, and the Q output of the third flip-flop becomes 1. The port becomes 0, causing the logic AND gate to output a low level (ie 0), and the reset signal ends.

[0062] Step S103, according to Integer cycle time and Residual time, determine the time parameters in the logic signal .

[0063] See also Figure 2 As shown, we can see that an integer cycle time is determined by the corresponding time parameter and residual time Synthesis, where this time parameter It refers to the time from the rising edge of the start signal to the first edge of the logic signal. Taking the second rising edge of the logic signal (i.e., edge e) as an example, , the time parameter from the c edge of the start signal to the e edge of the logic signal and residual time Together they form an integer cycle time, i.e. .

[0064] Based on this, the time parameters in the logic signal can be obtained .

[0065] Step S104, according to Time parameters , calculate the frequency of the logic signal.

[0066] Here, by The integer cycle time corresponding to the rising edge measurement and residual time , can get Time parameters In practical applications, The value can be set freely within the range of positive integers greater than 1. Generally, the larger the value, the better the measured time parameter. The more there are, the more accurate the frequency result will be.

[0067] Will Time parameters Conduct statistics and Time parameters Processing can get the cycle of the logic signal , which is the period of the measurement signal , and then according to the cycle and frequency The relationship between the frequencies can be obtained .

[0068] In one embodiment, the detailed description of how to Time parameters , calculate the frequency of the logic signal. Figure 2 As shown, in Figure 2 In the first time parameter The time between one rising edge and the next rising edge of the logic signal is not recorded, while the other time parameters It includes the time from one rising edge to the next rising edge in the logic signal and the time parameters Based on this, the remaining time parameters are calculated With the first time parameter Each time difference represents the time from the first rising edge of the logic signal to the For example, the time parameter With time parameters By subtracting, we can get the time interval between the first rising edge and the second rising edge.

[0069] Among them, the total measurement here is Time parameters , after data processing, we can get In order to calculate the frequency of the logic signal, it is necessary to average the above time differences to obtain the period of the logic signal. , the announcement is as follows:

[0070]

[0071] Here, the denominator Represents the number of periods included in each time difference, ensuring that all period differences are considered when calculating the average period. For example, assuming ,So and The time difference contains the time of one cycle, and and The time difference includes the time of two cycles. Therefore, when averaging is performed, the time of three cycles is averaged. Then the period of the corresponding logic signal is: .

[0072] In one embodiment, the logic signal connected to the FPGA can be multi-channel, that is, the measurement signal is converted into a multi-channel logic signal and then input into the FPGA. For example, the measurement signal is converted into four logic signals, namely SIG_IN1, SIG_IN2, SIG_IN3 and SIG_IN4. Here, the four-channel logic signal is used for illustration. The FPGA processes the four-channel logic signal to obtain the period corresponding to the logic signal SIG_IN1. , the cycle corresponding to the logic signal SIG_IN2 , the cycle corresponding to the logic signal SIG_IN3 , the cycle corresponding to the logic signal SIG_IN4 The average period of each logic signal is averaged to calculate the average period of the signal to be measured. , among which, here 、 、 、 All are in accordance with Calculated.

[0073] It should be noted that if only one logic signal is input to the FPGA for frequency measurement, the period of the logic signal is the period of the measurement signal, that is, If multiple logic signals are input to the FPGA for frequency measurement, the period of the measured signal is obtained by averaging the periods of the multiple logic signals.

[0074] In this embodiment, considering that the low-frequency sinusoidal signal rises slowly and has noise interference, dividing the measurement signal into multiple signals can reduce measurement errors.

[0075] In one embodiment, a measurement signal is input into a multi-channel comparator circuit, which converts the measurement signal into a multi-channel logic signal. In practical applications, the measurement signal may have different edge points when entering the comparator. Therefore, converting the measurement signal into a multi-channel logic signal and then averaging the periods of the multi-channel logic signal is used to reduce errors.

[0076] In the above embodiment, the signal frequency measurement method based on the single-chip FPGA obtains the logic signals corresponding to the start signal, the clock signal and the measurement signal, and measures the first Integer cycle time and Residual time, realizing the logic signal time parameter The accurate acquisition of the period measurement can decompose the period measurement into two parts: integer period and residual time, which can improve the measurement accuracy and significantly improve the system's adaptability to signals of different frequencies. By counting and calculating the time parameters, the frequency of the logic signal can be obtained. Based on this, all time measurements can be performed on a single FPGA, which improves the system integration, simplifies the hardware architecture, and has a wide range of application scenarios.

[0077] In one embodiment, a signal frequency measurement device based on a single-chip FPGA is provided. Figure 5 As shown, the signal frequency measurement device 500 based on a single-chip FPGA may include: an acquisition module 501 , a measurement module 502 , a determination module 503 , a calculation module 504 and a reset module 505 .

[0078] The acquisition module 501 is used to acquire the logic signals corresponding to the start signal, the clock signal and the measurement signal;

[0079] The measurement module 502 is used to measure the first Integer cycle time and Residual time; The integer cycle time represents the rising edge of the clock signal including the start signal and the first edge of the logic signal. An integer number of clock cycles of the rising edge; The residual time characterizes the The time from the first rising edge to the next rising edge of the clock signal;

[0080] The determination module 503 is used to determine the Integer cycle time and Residual time, determine the time parameters in the logic signal ; Time parameters Characterizes the time from the rising edge of the start signal to the first edge of the logic signal The time of the rising edge;

[0081] The calculation module 504 is used to calculate the Time parameters , calculate the frequency of the logic signal; where, is a positive integer greater than 0, is a positive integer greater than 1.

[0082] In one embodiment, the measurement module 502 is specifically configured to: The code density is calibrated for each carry chain, and the calibration value of each carry chain is stored in sequence; the delay of the carry chain is greater than the clock period of the clock signal; the first The first rising edge is input to the first trigger, and when the next rising edge of the clock signal arrives, the link length of the Q value of the first trigger transmitted in the carry chain is recorded; according to the calibration value corresponding to the link length, the maximum calibration value and the clock signal, the first trigger is calculated. a residual time.

[0083] In one embodiment, each carry chain is configured with a corresponding second flip-flop, and the second flip-flop is configured to store the Q value of the first flip-flop transmitted along the carry chain when the next rising edge of the clock signal arrives.

[0084] In one embodiment, the reset module 505 is specifically configured to, after determining the residual time, send a reset signal to the first flip-flop based on the third flip-flop and the second flip-flop of the first carry chain.

[0085] In one embodiment, the calculation module 504 is specifically configured to subtract the first time parameter from other time parameters respectively, to obtain a plurality of time difference values about the logic signal; the time difference values represent the time from the first rising edge to the second rising edge of the logic signal; and average the plurality of time difference values to obtain the frequency of the logic signal.

[0086] In one embodiment, the measurement signal corresponds to a plurality of logic signals, and the calculation module 504 is further configured to average the frequencies of the plurality of logic signals to obtain the frequency of the measurement signal.

[0087] In one embodiment, the plurality of logic signals corresponding to the measurement signal are converted via a plurality of comparator circuits.

[0088] For specific limitations of the signal frequency measurement device based on a single FPGA 500, refer to the limitations of the signal frequency measurement method based on a single FPGA described above, which will not be repeated here. Each module in the above signal frequency measurement device based on a single FPGA 500 can be realized by software, hardware, and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0089] In one embodiment, an FPGA is provided, comprising a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a signal frequency measurement method based on a single FPGA.

[0090] In one embodiment, a computer storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement a signal frequency measurement method based on a single FPGA.

[0091] ​​​​​It is to be appreciated that the above description and the examples that follow are intended to be illustrative only and that changes can be made to the description, either functionally or chronologically, as well as changes being made concerning the order of implementation. The logic and / or steps represented in the flow diagrams and / or described herein can be considered as a sequence of executable instructions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus) or a propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber (optical), and a portable compact disc read-only memory (CDROM). Note that the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example via the optical scanner of a device or device or via an intermediary, such as a facility bureau, then compiled, interpreted, or processed in a suitable manner if necessary, and then stored in a computer storage medium.

[0092] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: a discrete logic circuit having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0093] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.

[0094] Furthermore, the terms "first", "second", etc. are used only for descriptive purposes and do not connote or imply relative importance or a quantity of the indicated technical features. Thus, a feature defined with "first", "second", etc. can include at least one of the features implicitly or explicitly. In the description of the present application, the meaning of "a plurality" is at least two, for example, two, three, etc., unless otherwise specifically defined.

[0095] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. A signal frequency measurement method based on a single-chip FPGA, characterized in that: Applied to FPGA, the method includes: Obtaining logic signals corresponding to the start signal, clock signal, and measurement signal; When the rising edge of the start signal arrives, measure the Integer cycle time and The remaining time; The integer cycle time represents the rising edge of the clock signal including the rising edge of the start signal and the first edge of the logic signal. The integer number of clock cycles of the rising edge reflects the number of complete clock cycles between the start signal and each rising edge of the logic signal; The residual time characterizes the time from the first The start signal is used to indicate the start time of the signal frequency measurement; According to Integer cycle time and The residual time determines the time parameter of the logic signal ; The time parameter Characterizes the period from the rising edge of the start signal to the first edge of the logic signal The time of a rising edge; an integer cycle time is determined by the corresponding time parameter and residual time composition; according to The time parameters , calculate the frequency of the logic signal, including: other time parameters Subtract the first time parameter respectively , get the logic signal The time difference represents the time from the first rising edge of the logic signal to the The time of the rising edge; The time difference is averaged to obtain the frequency of the logic signal; wherein, is a positive integer greater than 0, is a positive integer greater than 1.

2. The signal frequency measurement method based on a single-chip FPGA according to claim 1, characterized in that: The measurement Residual time, including: right Carry chains are used to calibrate the code density, and calibration values ​​of each carry chain are stored in sequence; the delay of the carry chain is greater than the clock period of the clock signal; The logic signal A rising edge is input to the first trigger, and when the next rising edge of the clock signal arrives, the Q value of the first trigger is recorded in the link length of the carry chain; Calculate the first Remaining time.

3. The signal frequency measurement method based on a single-chip FPGA according to claim 2, characterized in that: Each of the carry chains is configured with a corresponding second flip-flop. When the next rising edge of the clock signal arrives, the second flip-flop is used to store the Q value of the first flip-flop transmitted along the carry chain.

4. The signal frequency measurement method based on a single-chip FPGA according to claim 2 or 3, characterized in that: The method further comprises: In determining the After a residual time, a reset signal is sent to the first flip-flop based on the third flip-flop and the second flip-flop of the first carry chain.

5. The signal frequency measurement method based on a single-chip FPGA according to claim 1, characterized in that: The measurement signal has multiple corresponding logic signals, and the method further includes: The frequency of each logic signal is averaged to obtain the frequency of the measurement signal.

6. The signal frequency measurement method based on a single-chip FPGA according to claim 5, characterized in that: The multi-channel logic signals corresponding to the measurement signals are converted via a multi-channel comparator circuit.

7. A signal frequency measurement device based on a single-chip FPGA, characterized in that: Applied to FPGA, the device includes: An acquisition module, used to acquire logic signals corresponding to the start signal, clock signal and measurement signal; The measurement module is used to measure the first Integer cycle time and The remaining time; The integer cycle time represents the rising edge of the clock signal including the rising edge of the start signal and the first edge of the logic signal. The integer number of clock cycles of the rising edge reflects the number of complete clock cycles between the start signal and each rising edge of the logic signal; The residual time characterizes the time from the first The start signal is used to indicate the start time of the signal frequency measurement; Determine module for Integer cycle time and The residual time determines the time parameter of the logic signal ; The time parameter Characterizes the period from the rising edge of the start signal to the first edge of the logic signal The time of a rising edge; an integer cycle time is determined by the corresponding time parameter and residual time composition; Calculation module, used to The time parameters , calculate the frequency of the logic signal, including: other time parameters Subtract the first time parameter respectively , get the logic signal The time difference represents the time from the first rising edge of the logic signal to the The time of the rising edge; The time difference is averaged to obtain the frequency of the logic signal; wherein, is a positive integer greater than 0, is a positive integer greater than 1.

8. An FPGA comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the signal frequency measurement method based on a single-chip FPGA according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the signal frequency measurement method based on a single-chip FPGA according to any one of claims 1 to 6 are implemented.

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