Memory built-in self-test circuit generation method and device and electronic equipment

Abstract

The invention relates to the technical field of circuits, in particular to a memory built-in self-test circuit generation method and device and electronic equipment. The method comprises the following steps: acquiring a parameter configuration file of which the text format is Excel; wherein the parameter configuration file comprises first configuration information of the static random access memory, second configuration information of the joint test behavior organization and an algorithm for detecting a fault in the memory; calculating the matching degree between parameters in each cell in the parameter configuration file and each pre-configured theoretical algorithm; determining a target algorithm based on the matching degree; wherein the target algorithm comprises any one of theoretical algorithms; and inputting the algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written by adopting a SpinalHDL programming language, and generating a memory built-in self-test circuit corresponding to the target algorithm.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technologies, and in particular, to a method, apparatus, and electronic device for generating a memory built-in self-test circuit. Background Art

[0002] With the rapid development of modern semiconductor technologies, system-on-chip (SoC) has been increasingly widely used in the field of automotive electronics. Memories, especially static random-access memories (SRAMs), as key components in SoCs, are widely distributed in SoCs, occupy a large area, and have an important impact on the reliability and performance of chips. Therefore, ensuring the functional correctness and reliability of SRAM memories is crucial for the overall performance and safety of automotive-grade chips. However, SRAMs are vulnerable to various factors during production and use, resulting in faults and affecting the normal operation of automotive electronic systems.

[0003] Therefore, how to test SRAMs to ensure their reliability and stability has become an urgent problem to be solved. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a method, apparatus, and electronic device for generating a memory built-in self-test circuit.

[0005] In a first aspect, the present disclosure provides a method for generating a memory built-in self-test circuit, including: obtaining a parameter configuration file in Excel text format; wherein, the parameter configuration file includes first configuration information of a static random-access memory, second configuration information of a Joint Test Action Group, and an algorithm for detecting faults in the memory; calculating the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm; based on the matching degree, determining a target algorithm; wherein, the target algorithm includes any one of the theoretical algorithms; inputting the algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written in the SpinalHDL programming language to generate a memory built-in self-test circuit corresponding to the target algorithm.

[0006] Second aspect, the present disclosure provides a memory built-in self-test circuit generation device, including: an acquisition unit configured to acquire a parameter configuration file in Excel text format; wherein, the parameter configuration file includes first configuration information of a static random access memory, second configuration information of a joint test action group, and an algorithm for detecting faults in the memory; a processing unit configured to calculate a matching degree between parameters in each cell of the parameter configuration file acquired by the acquisition unit and each pre-configured theoretical algorithm; the processing unit is further configured to determine a target algorithm based on the matching degree; wherein, the target algorithm includes any one of the theoretical algorithms; the processing unit is further configured to input an algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written in SpinalHDL programming language to generate a memory built-in self-test circuit corresponding to the target algorithm.

[0007] Third aspect, the present disclosure provides an electronic device, characterized by including: a memory and a processor, the memory is configured to store a computer program; the processor is configured to, when executing the computer program, enable the electronic device to implement the memory built-in self-test circuit generation method according to any one of the first aspect.

[0008] Fourth aspect, the present disclosure provides a computer-readable storage medium, including: a computer program stored on the computer-readable storage medium, and the computer program is executed by a controller to implement the memory built-in self-test circuit generation method according to any one of the first aspect.

[0009] Fifth aspect, the present disclosure provides a computer program product, when the computer program product runs on a computer, enabling the computer to execute the memory built-in self-test circuit generation method according to any one of the first aspect.

[0010] These aspects or other aspects of the present disclosure will be more clearly understood in the following description.

[0011] The technical solutions provided by the present disclosure have the following advantages compared with the prior art:

[0012] The method for generating an on-chip memory built-in self-test circuit provided by the present disclosure obtains a parameter configuration file in Excel text format, and calculates the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm; based on the matching degree, a target algorithm is determined; then, the algorithm identifier of the target algorithm and the parameter configuration file are input into a circuit generation program written in the SpinalHDL programming language to generate an on-chip memory built-in self-test circuit corresponding to the target algorithm. In this way, users can generate different on-chip memory built-in self-test circuits by configuring different parameter configuration files, and then can perform corresponding tests on the SRAM to be tested based on the on-chip memory built-in self-test circuit, and can determine the reliability and stability of the SRAM based on the test results, thus solving the problem of how to test the SRAM to ensure its reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0015] Figure 1 It is one of the flow diagrams of a method for generating an on-chip memory built-in self-test circuit provided by an embodiment of the present disclosure;

[0016] Figure 2 It is a schematic diagram of an on-chip memory built-in self-test circuit of a method for generating an on-chip memory built-in self-test circuit provided by an embodiment of the present disclosure;

[0017] Figure 3 It is another flow diagram of a method for generating an on-chip memory built-in self-test circuit provided by an embodiment of the present disclosure;

[0018] Figure 4 It is yet another flow diagram of a method for generating an on-chip memory built-in self-test circuit provided by an embodiment of the present disclosure;

[0019] Figure 5 It is still another flow diagram of a method for generating an on-chip memory built-in self-test circuit provided by an embodiment of the present disclosure;

[0020] Figure 6 It is a schematic diagram of the structure of an on-chip memory built-in self-test circuit generation device provided by an embodiment of the present disclosure;

[0021] Figure 7 Schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0022] In order to more clearly understand the above-mentioned objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0023] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0024] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0025] Embodiment 1

[0026] Figure 1 A flow diagram of a method for generating a memory built-in self-test circuit is exemplarily shown. The execution subject of this example may be an electronic device, such as Figure 1 As shown, the method includes:

[0027] S11. Obtain a parameter configuration file in Excel text format; wherein, the parameter configuration file includes first configuration information of a static random access memory, second configuration information of a Joint Test Action Group (JTAG), and an algorithm for detecting faults in the memory.

[0028] In some embodiments, the algorithm for detecting faults in the memory may be a March algorithm, such as: March A, March B, March C, etc., an algorithm for detecting faults in the memory through specific read and write operations.

[0029] In some examples, the parameter configuration files in Excel format are shown in Table 1, Table 2, and Table 3.

[0030] Table 1

[0031]

[0032] Among them, SinglePort represents a single-port random access memory (RAM), SimpleDualPort represents a pseudo-dual-port RAM, TrueDualPort represents a dual-port RAM, and RedundancySupport is used to indicate whether redundant repair space is supported, and TRUE (indicating support for redundant repair space) / FALSE (indicating no support for redundant repair space) can be selected.

[0033] Table 2

[0034]

[0035] Among them, JtagSupport indicates whether JTAG debugging is supported, and TRUE (indicating support for JTAG debugging) / FALSE (indicating no support for JTAG debugging) can be selected.

[0036] Table 3

[0037]

[0038]

[0039] Among them, the custom type (CustomType) includes: existing algorithm (ExistingAlgorithm), custom algorithm (CustomAlgorithm), and algorithm matching scheme (AlgorithmMatching).

[0040] In some examples, the existing algorithms (ExistingAlgorithm) include but are not limited to MarchA, MarchB, MarchC, MarchC-, MarchC+, MarchLR.

[0041] In some examples, for the custom algorithm (CustomAlgorithm): the user must customize the address timing (AddressTiming) of the algorithm test vector: three options of increment (Increment), decrement (Decrement), and bidirectional (Both) can be selected.

[0042] In some examples, OperationCode: The user can configure the test elements in each test vector according to their own needs. For example, the test elements include one or more of r0, r1, w0, w1, nr0, nr1, nw0, nw1, d.

[0043] In some examples, OperationNum: If there are elements of nr0, nr1, nw0, nw1 in the operation code, it is necessary to indicate the number of times the operation must be executed.

[0044] In some examples, AlgorithmMatching: The user can configure the algorithm complexity, fault type, and their weight ratio. The memory built-in self-test circuit generation device automatically calculates 3 sets of algorithms with the highest matching degree for the user to choose. The complexity and complexity weight value (AlgorithmComplexity) of the theoretical algorithms to be selected, fault type and fault type weight value (FaultTypes): The user can configure which SRAM fault types the algorithm must cover according to their own needs. The fault types include, but are not limited to, one or more of SAF, TF, WDF, RDF, CFst, CFtr.

[0045] Note: The sum of the weight ratios of the algorithm complexity and the fault type is 1.

[0046] S12. Calculate the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm.

[0047] In some examples, at this stage, it is necessary to match the parameter data (parameters in each cell) stored in the List with each theoretical algorithm in the algorithm database. The algorithm database is integrated inside the memory built-in self-test circuit generation device, and it stores all information of each existing algorithm, including the test vector content, complexity, detectable fault type data, etc. of each algorithm.

[0048] In some examples, the memory built-in self-test circuit generation device will first judge the algorithm type: For example, when it is determined through the parameters in the cell that the custom type (CustomType) set in the parameter configuration file is an existing algorithm (ExistingAlgorithm), the information of the selected existing algorithm is obtained from the algorithm database. If it is determined that the information of the selected existing algorithm exists, it is determined that the matching degree between the parameters in each cell of the parameter configuration file and the theoretical algorithm is 100%. Then, based on the information of the selected existing algorithm, such as test vector, complexity, detectable fault type, the above content is packaged in the format required by SpinalHDL and waits to be used in the subsequent stage.

[0049] Alternatively, when it is determined through the parameters in the cell that the custom type (CustomType) set in the parameter configuration file is the custom algorithm (CustomAlgorithm), the custom algorithm information is read, and it is determined whether the same content can be found in the algorithm database (for example, the custom algorithm is the same as the MarchC algorithm in the algorithm database; or the custom algorithm is equal to a combination of multiple theoretical algorithms). Subsequently, the built-in self-test circuit generation device in the memory converts the configured parameter data into the format required by SpinalHDL and automatically calculates the complexity. If relevant theoretical algorithms can be found in the algorithm database, the type of detected fault can be determined; if no relevant theoretical algorithms are found, the type of fault that the custom algorithm can detect cannot be confirmed. At this time, the matching degree between the parameters in each cell of the parameter configuration file and the theoretical algorithm is considered to be 100%.

[0050] Alternatively, when it is determined through the parameters in the cell that the custom type (CustomType) set in the parameter configuration file is the algorithm matching scheme (AlgorithmMatching), the algorithm complexity and fault type information are read, and the matching degree between the algorithm complexity and fault type information of each theoretical algorithm in the algorithm database and the algorithm complexity and fault type information in the parameter configuration file is calculated. For example, the algorithm complexity and fault type information of each theoretical algorithm are converted into a theoretical vector, and the algorithm complexity and fault type information in the parameter configuration file are converted into an actual vector. By calculating the similarity between the actual vector and the theoretical vector (such as cosine similarity, Euclidean distance, etc.), and using this similarity as the matching degree between the algorithm complexity and fault type information of the theoretical algorithm and the algorithm complexity and fault type information in the parameter configuration file. Alternatively, by calculating the actual score of each theoretical algorithm in the algorithm database and the parameter configuration file, and using the actual score as the matching degree between the algorithm complexity and fault type information of the theoretical algorithm and the algorithm complexity and fault type information in the parameter configuration file. In this way, N groups of theoretical algorithms can be filtered out based on the matching degree, and a prompt message containing the N groups of theoretical algorithms with the highest matching degree of algorithm complexity and fault type information can be generated. Subsequently, in response to the selection operation of the preset algorithm, the preset algorithm is used as the target algorithm, and the above content is packaged in the format required by SpinalHDL and waits to be used in the subsequent stage.

[0051] In some examples, the algorithm complexity refers to the number of memory accesses in the March algorithm. For example, in the MATS++ algorithm, the number of memory accesses in the M0 stage is 1, the number of memory accesses in the M1 stage is 2, and the number of memory accesses in the M2 stage is 3. Therefore, the complexity is 1 + 2 + 3 = 6n.

[0052] In some examples, the fault types include single - unit faults and dual - unit coupling faults. Among them, common single - unit faults are: state fault (SF), stuck - at fault (SAF), transition fault (TF), write - destruction fault (WDF), read - destruction fault (RDF), incorrect - read fault (IRF), and pseudo - read - destruction fault (DRDF); common dual - unit coupling faults are: state - coupling fault (CFst), disturbance - coupling fault (CFds), transition - coupling fault (CFtr), write - destruction coupling fault (CFwd), pseudo - read - destruction coupling fault (CFdrd), and incorrect - read coupling fault (CFir).

[0053] In some examples, the total number of faults that different theoretical algorithms can detect and the total number of fault types are shown in Tables 4 and 5.

[0054] Table 4

[0055]

[0056] Table 5

[0057]

[0058] Among them, (0 / 2) can be understood as this kind of fault has 2 fault primitives and this algorithm can cover 0 kinds; (2 / 2) can be understood as this kind of fault has 2 fault primitives and this algorithm can cover 2 kinds; (6 / 8) can be understood as this kind of fault has 8 fault primitives and this algorithm can cover 6 kinds; (8 / 8) can be understood as this kind of fault has 8 fault primitives and this algorithm can cover 8 kinds.

[0059] In this way, the memory built - in self - test circuit generation device can obtain the fault coverage rate corresponding to each theoretical algorithm by querying Tables 4 and 5. For example, the calculation process of the fault coverage rate includes:

[0060] Obtain the fault types set in the parameter configuration file, such as SF, SAF, DRDF. At this time, by querying Table 4, for the MATS++ algorithm as the theoretical algorithm, for the fault types SF, SAF, and DRDF, it is determined that the total number of fault types is 6 (2 + 2 + 2), and the total number of faults that the fault types SF, SAF, and DRDF can detect is 4 (2 + 2 + 0). That is, the fault coverage rate of the MATS++ algorithm is 4 / 6 (66.67%).

[0061] Similarly, as can be seen from Table 4, for the MarchC+ algorithm, for fault types SF, SAF, and DRDF, the total number of determined fault types is 6 (2 + 2 + 2), and the total number of faults that can be detected by fault types SF, SAF, and DRDF is 6 (2 + 2 + 2). That is, the fault coverage rate of the theoretical algorithm MarchC+ is 6 / 6 (100%).

[0062] Among them, the core of fault coverage rate calculation lies in extracting the fault types that users care about and calculating the fault coverage rate of each algorithm in the algorithm database for these fault types.

[0063] In some examples, complexity normalization calculation includes:

[0064] Assume that the complexity of the i-th theoretical algorithm is Mi, the complexity configured by the user is M, the difference between the complexity of the i-th theoretical algorithm and the complexity configured by the user is ΔMi, and the complexity normalization value of the i-th theoretical algorithm is Ni. Among them, i ∈ [1, I], and both i and I are integers, and I is the total number of theoretical algorithms in the algorithm database.

[0065] The first step: Subtract the complexity of the i-th theoretical algorithm from the complexity configured by the user to obtain the complexity difference of the i-th theoretical algorithm as:

[0066] ΔMi = M - Mi.

[0067] The second step: Based on the complexity differences of all theoretical algorithms, judge the maximum ΔMi_max and the minimum ΔMi_min of ΔMi.

[0068] The third step: Calculate the complexity normalization value of the i-th theoretical algorithm Among them, Ni is the complexity normalization value of the i-th theoretical algorithm.

[0069] After that, based on the calculation results of the fault coverage rate and the calculation results of the complexity normalization, calculate the actual score; among them,

[0070] The actual score of the i-th theoretical algorithm = Ni × complexity weight value + the fault coverage rate of the i-th theoretical algorithm × fault type weight value. Among them, the sum of the complexity weight value and the fault type weight value is equal to 1.

[0071] It should be noted that in the case of the same fault coverage rate, the lower the complexity, the better; in the case of the same complexity, the higher the fault coverage rate, the better, and the more comprehensive the fault types, the better.

[0072] In some examples, the complexity corresponding to the theoretical algorithm is shown in Table 6.

[0073] Table 6

[0074]

[0075] In this way, the memory built-in self-test circuit generation device can obtain the complexity corresponding to each theoretical algorithm by querying Table 6.

[0076] In some examples, the parameters in each cell of the parameter configuration file and all the pre-configured theoretical algorithms can be input into the matching model for matching degree calculation, so as to obtain the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm.

[0077] Among them, the training process of the matching model includes:

[0078] Obtain the first training sample data and the first labeling result of the first training sample data. Among them, the first training sample data includes the parameters in each cell of the historical parameter configuration file and all the pre-configured theoretical algorithms in history, and the first labeling result includes the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm.

[0079] Input the first training sample data into the first neural network model for learning, and obtain the first prediction result of the first neural network model for the first training sample data.

[0080] Based on the first prediction result and the first labeling result, adjust the network parameters of the first neural network model until the first neural network model converges, so as to obtain the matching model.

[0081] S13. Determine the target algorithm based on the matching degree; among them, the target algorithm includes any one of the theoretical algorithms.

[0082] In some examples, when determining the target algorithm based on the matching degree, if the matching degree is equal to 100%, the theoretical algorithm with a matching degree equal to 100% is used as the target algorithm.

[0083] Alternatively, when the matching degree is not equal to 100%, a prompt message including the theoretical algorithm is displayed; in response to the selection operation of the preset algorithm, the preset algorithm is used as the target algorithm.

[0084] S14. Input the algorithm identifier of the target algorithm and the parameter configuration file into the circuit generation program written in the SpinalHDL programming language to generate the memory built-in self-test circuit corresponding to the target algorithm.

[0085] In some examples, the first configuration information of the SRAM and the second configuration information of the JTAG in the target algorithm and the parameter configuration file are used as inputs, and corresponding Verilog, VHDL, and SystemVerilog codes are generated through a program written in the SpinalHDL language.

[0086] Exemplarily, the memory built-in self-test circuit corresponding to the target algorithm is as Figure 2 shown. The memory built-in self-test circuit includes a JTAG control unit, an execution unit, an SRAM interface unit, and an SRAM for detection. The JTAG control unit includes a JTAG interface logic and a register control unit. The execution unit includes a control unit for the target algorithm, a slave state machine module, and a comparison unit. The SRAM interface unit includes a fault repair unit.

[0087] Among them, the JTAG control unit stores the configuration information of the March algorithm test vector in the form of registers. In addition, the algorithm execution strategy in the JTAG mode can also be selected.

[0088] Algorithm replacement strategy: If this strategy is selected in the JTAG configuration register, the algorithm control unit in the execution unit will no longer execute the algorithm strategy selected by the user, but will execute a new test vector according to the JTAG configuration information. Algorithm superposition strategy: If this strategy is selected in the JTAG configuration register, new test vectors configured by JTAG will be superimposed at any position of the algorithm strategy selected by the user. For example, test vectors such as Mx, My, and Mz are configured through JTAG (one or more can be configured), and it is selected to insert new test vectors at any position of the original M0 - M6. Therefore, the current test elements become Mx - M0 - M1 - My - M2 - M3 - M4 - M5 - Mz. The algorithm control unit in the execution unit instructs the slave state machine module to work according to the order of the new test elements. Exemplarily, the corresponding relationship between the theoretical algorithm and the test elements is shown in Table 7.

[0089] Table 7

[0090]

[0091] In this way, the memory built-in self-test circuit generation device can obtain the test content of the test elements of each theoretical algorithm by querying Table 7.

[0092] In the memory built-in self-test circuit generation method provided by the embodiments of the present disclosure, users can generate different memory built-in self-test circuits by configuring different parameter configuration files, and then can perform corresponding tests on the SRAM to be tested based on the memory built-in self-test circuit, and can determine the reliability and stability of the SRAM based on the test results.

[0093] In some implementable examples, in combination with Figure 1 as Figure 3 shown, the method for generating an on-chip memory built-in self-test circuit provided by the embodiments of the present disclosure further includes S15.

[0094] S15. Convert the parameter configuration file into parameter information in the multi-paradigm programming language Scala, import the parameter information into an open-source Java library, and read the parameters in each cell of the parameter configuration file.

[0095] In some examples, after the user completes the above parameter configuration file, convert the parameter configuration file into parameter information in the multi-paradigm programming language Scala, and import the parameter information into an open-source Java library, so that the data in each row and each cell of the Excel file can be read, and all parameter data is stored in a List. The serial number SerialNumber indicates how many groups of test circuits the on-chip memory built-in self-test circuit generation device needs to generate, and each group of parameters is stored in a List.

[0096] In some examples, the open-source Java library can be apache.poi.

[0097] For the method for generating an on-chip memory built-in self-test circuit provided by the embodiments of the present disclosure, since the parameter configuration file configured by the user cannot be directly recognized by the electronic device, it is necessary to convert the parameter configuration file into parameter information in the multi-paradigm programming language Scala, and import the parameter information into an open-source Java library, so that the parameters in each cell of the parameter configuration file can be read. Furthermore, the electronic device can calculate the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm based on the parameters in each cell; based on the matching degree, determine the target algorithm; then, input the algorithm identifier of the target algorithm and the parameter configuration file into the circuit generation program written in the SpinalHDL programming language to generate the on-chip memory built-in self-test circuit corresponding to the target algorithm. In this way, the user can generate different on-chip memory built-in self-test circuits by configuring different parameter configuration files, and then can perform corresponding tests on the SRAM to be tested based on the on-chip memory built-in self-test circuit, and can determine the reliability and stability of the SRAM based on the test results.

[0098] In some implementable examples, in combination with Figure 1 as Figure 4 shown, the above S13 can be specifically implemented by the following S130.

[0099] S130. When there is only one theoretical algorithm with a matching degree equal to the matching threshold, and the theoretical algorithm with a matching degree equal to the matching threshold is the specified algorithm, the specified algorithm is used as the target algorithm; where the specified algorithm includes any one of the existing algorithms and the custom algorithms.

[0100] In some examples, the matching threshold is equal to 100%.

[0101] For the method for generating the memory built-in self-test circuit provided by the embodiments of the present disclosure, since the parameter configuration file configured by the user cannot be directly recognized by the electronic device, it is necessary to convert the parameter configuration file into parameter information in the multi-paradigm programming language Scala and import the parameter information into the open-source java library, so that the parameters in each cell of the parameter configuration file can be read. Furthermore, the electronic device can calculate the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm based on the parameters in each cell; when there is only one theoretical algorithm with a matching degree equal to the matching threshold, and the theoretical algorithm with a matching degree equal to the matching threshold is the specified algorithm, the specified algorithm is used as the target algorithm; thereafter, the algorithm identifier of the target algorithm and the parameter configuration file are input into the circuit generation program written in the SpinalHDL programming language to generate the memory built-in self-test circuit corresponding to the target algorithm. In this way, the user can generate different memory built-in self-test circuits by configuring different parameter configuration files, and then can perform corresponding tests on the SRAM to be tested based on the memory built-in self-test circuit, and can determine the reliability and stability of the SRAM based on the test results.

[0102] In some feasible examples, in combination with Figure 1 , such as Figure 5 , the above S13 can be specifically implemented by the following S131 and S132.

[0103] S131. When there are multiple theoretical algorithms with a matching degree not equal to the matching threshold, and the theoretical algorithm is an algorithm for determining whether the elements in one set match the elements in another set, a prompt message including the theoretical algorithm is generated.

[0104] S132. In response to a selection operation on a preset algorithm, the preset algorithm is used as the target algorithm; where the preset algorithm includes any one of the theoretical algorithms.

[0105] The method for generating a memory built-in self-test circuit provided by an embodiment of the present disclosure. Since the parameter configuration file configured by the user cannot be directly recognized by the electronic device, it is necessary to convert the parameter configuration file into parameter information of the multi-paradigm programming language Scala and import the parameter information into the open-source Java library, so that the parameters in each cell of the parameter configuration file can be read. Furthermore, the electronic device can calculate the matching degree between the parameters in each cell of the parameter configuration file and each pre-configured theoretical algorithm based on the parameters in each cell. When there are multiple theoretical algorithms with a matching degree not equal to the matching threshold, and the theoretical algorithm is an algorithm for determining whether the elements in one set match the elements in another set, a prompt message including the theoretical algorithm is generated. In response to the selection operation of the preset algorithm, the preset algorithm is used as the target algorithm. Then, the algorithm identifier of the target algorithm and the parameter configuration file are input into the circuit generation program written in the SpinalHDL programming language to generate the memory built-in self-test circuit corresponding to the target algorithm. In this way, the user can generate different memory built-in self-test circuits by configuring different parameter configuration files, and then can perform corresponding tests on the SRAM to be tested based on the memory built-in self-test circuit, and can determine the reliability and stability of the SRAM based on the test results.

[0106] In some feasible examples, the first configuration information includes the data bit width, data depth, and interface type. The interface type includes single-port random access memory, pseudo-dual-port random access memory, dual-port random access memory, and the first indication information for indicating whether redundant repair space is supported.

[0107] In some feasible examples, the second configuration parameter includes the second indication information for indicating whether joint test behavior organization debugging is supported.

[0108] Embodiment 2

[0109] The structural schematic diagram of the memory built-in self-test circuit generation device provided by Embodiment 2 of the present application is as Figure 6 shown. The memory built-in self-test circuit generation device includes: an acquisition unit 201 and a processing unit 202.

[0110] An acquisition unit 201 for acquiring a parameter configuration file in Excel text format; wherein the parameter configuration file includes first configuration information of a static random access memory, second configuration information of a Joint Test Action Group, and an algorithm for detecting faults in the memory; a processing unit 202 for calculating a matching degree between parameters in each cell of the parameter configuration file acquired by the acquisition unit 201 and each pre-configured theoretical algorithm; the processing unit 202 is further configured to determine a target algorithm based on the matching degree; wherein the target algorithm includes any one of the theoretical algorithms; the processing unit 202 is further configured to input an algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written in the SpinalHDL programming language to generate a memory built-in self-test circuit corresponding to the target algorithm.

[0111] In some feasible examples, the processing unit 202 is further configured to convert the parameter configuration file into parameter information in a multi-paradigm programming language, import the parameter information into an open-source Java library, and read the parameters in each cell of the parameter configuration file.

[0112] In some feasible examples, the processing unit 202 is specifically configured to use a specified algorithm as the target algorithm when there is only one theoretical algorithm with a matching degree equal to the matching threshold and the theoretical algorithm with a matching degree equal to the matching threshold is the specified algorithm; wherein the specified algorithm includes any one of an existing algorithm and a custom algorithm.

[0113] In some feasible examples, the processing unit 202 is specifically configured to generate a prompt message including the theoretical algorithm when there are multiple theoretical algorithms with a matching degree not equal to the matching threshold and the theoretical algorithm is an algorithm for determining whether elements in one set match elements in another set; the processing unit 202 is specifically configured to use a preset algorithm as the target algorithm in response to a selection operation on the preset algorithm; wherein the preset algorithm includes any one of the theoretical algorithms.

[0114] In some feasible examples, the first configuration information includes a data bit width, a data depth, and an interface type, and the interface type includes a single-port random access memory, a pseudo-dual-port random access memory, a dual-port random access memory, and a first indication information for indicating whether redundant repair space is supported.

[0115] In some feasible examples, the second configuration parameter includes a second indication information for indicating whether Joint Test Action Group debugging is supported.

[0116] Wherein, all relevant contents of each step involved in the above method embodiment can be cited to the function description of the corresponding functional module, and its function will not be elaborated here.

[0117] Of course, the memory built-in self-test circuit generation device provided by the embodiments of the present invention includes but is not limited to the above modules. For example, the memory built-in self-test circuit generation device may further include a storage unit 203. The storage unit 203 can be used to store the program code of the memory built-in self-test circuit generation device, and can also be used to store the data generated during the operation of the memory built-in self-test circuit generation device, such as diagnostic data and the like.

[0118] Embodiment 3

[0119] Embodiment 3 of the present invention provides a schematic structural diagram of an electronic device. As shown Figure 7 the electronic device may include: at least one processor 51, a memory 52, a communication interface 53, and a communication bus 54.

[0120] The following is a specific introduction to each component of the electronic device:

[0121] Among them, the processor 51 is the control center of the electronic device, which can be a single processor or a collective term for multiple processing elements. For example, the processor 51 is a central processing unit (CPU), or can be an application specific integrated circuit (ASIC), or an integrated circuit configured to implement the embodiments of the present invention, such as: one or more DSPs, or one or more field programmable gate arrays (FPGAs).

[0122] In a specific implementation, as an embodiment, the processor 51 may include one or more CPUs. For example, the CPUs include CPU0 and CPU1. And, as an embodiment, the electronic device may include multiple processors. For example, the CPUs include the processor 51 and the processor 55. Each of these processors can be a single-core processor (Single-CPU) or a multi-core processor (Multi-CPU). Here, the processor may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0123] The memory 52 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or it can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 52 can exist independently and be connected to the processor 51 through the communication bus 54. The memory 52 can also be integrated with the processor 51.

[0124] In a specific implementation, the memory 52 is used to store the data and execute the software program of the present invention. The processor 51 can execute various functions of the built-in self-test circuit generation device of the memory by running or executing the software program stored in the memory 52 and calling the data stored in the memory 52.

[0125] The communication interface 53 uses any device such as a transceiver to communicate with other devices or communication networks, such as a radio access network (RAN), a wireless local area network (WLAN), a terminal, the cloud, etc. The communication interface 53 can include an acquisition unit to implement the acquisition function.

[0126] The communication bus 54 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, only a thick line is used to represent it, but it does not mean that there is only one bus or one type of bus.

[0127] As an example, in combination with Figure 6, the acquisition unit 201 of the memory built-in self-test circuit generation device implements the same functions as the communication interface 53, the processing unit 202 in the memory built-in self-test circuit generation device implements the same functions as the processor 51, and the storage unit 203 in the memory built-in self-test circuit generation device implements the same functions as the memory 54.

[0128] Embodiment 4

[0129] Embodiment 4 of the present invention provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method in any one of the embodiments.

[0130] Embodiment 5

[0131] Embodiment 5 of the present invention provides a computer program product, when the computer program product runs on a computer, it causes the computer to execute the method of any item in any one of the embodiments.

[0132] The above are only specific implementation manners of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for generating a memory built-in self-test circuit, characterized in that: include: Obtaining a parameter configuration file in an Excel text format; wherein the parameter configuration file includes first configuration information of a static random access memory, second configuration information of a joint test behavior organization, and an algorithm for detecting faults in the memory; Calculating the matching degree between the parameters in each cell in the parameter configuration file and each pre-configured theoretical algorithm; Based on the matching degree, determining a target algorithm; wherein the target algorithm includes any one of the theoretical algorithms; The algorithm identifier of the target algorithm and the parameter configuration file are input into a circuit generation program written in the SpinalHDL programming language to generate a memory built-in self-test circuit corresponding to the target algorithm.

2. The method for generating a memory built-in self-test circuit according to claim 1, wherein: Before calculating the matching degree between the parameters in each cell in the parameter configuration file and each pre-configured theoretical algorithm, the method further includes: The parameter configuration file is converted into parameter information of a multi-paradigm programming language, and the parameter information is imported into an open source Java library, and the parameters in each cell in the parameter configuration file are read.

3. The method for generating a memory built-in self-test circuit according to claim 1, wherein: The determining of a target algorithm based on the matching degree includes: When there is only one theoretical algorithm with a matching degree equal to the matching threshold, and the theoretical algorithm with a matching degree equal to the matching threshold is a specified algorithm, the specified algorithm is used as the target algorithm; wherein the specified algorithm includes any one of an existing algorithm and a custom algorithm.

4. The method for generating a memory built-in self-test circuit according to claim 1, wherein: The determining of a target algorithm based on the matching degree includes: When there are multiple theoretical algorithms whose matching degree is not equal to the matching threshold, and the theoretical algorithm is an algorithm for determining whether an element in one set matches an element in another set, generating prompt information including the theoretical algorithm; In response to a selection operation of a preset algorithm, the preset algorithm is used as a target algorithm; wherein the preset algorithm includes any one of the theoretical algorithms.

5. The method for generating a memory built-in self-test circuit according to claim 1, wherein: The first configuration information includes data bit width, data depth and interface type, and the interface type includes single-port random access memory, pseudo-dual-port random access memory, dual-port random access memory, and first indication information for indicating whether redundant repair space is supported.

6. The method for generating a memory built-in self-test circuit according to claim 1, wherein: The second configuration parameter includes second indication information for indicating whether joint test behavior organization debugging is supported.

7. A memory built-in self-test circuit generation device, characterized in that: include: An acquisition unit, configured to acquire a parameter configuration file in an Excel text format; wherein the parameter configuration file includes first configuration information of a static random access memory, second configuration information of a joint test behavior organization, and an algorithm for detecting faults in the memory; A processing unit, configured to calculate a matching degree between a parameter in each cell of the parameter configuration file acquired by the acquisition unit and each pre-configured theoretical algorithm; The processing unit is further used to determine a target algorithm based on the matching degree; wherein the target algorithm includes any one of the theoretical algorithms; The processing unit is further used to input the algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written in the SpinalHDL programming language to generate a memory built-in self-test circuit corresponding to the target algorithm.

8. An electronic device, characterized in that: include: A memory and a processor, wherein the memory is used to store a computer program; and the processor is used to enable the electronic device to implement the memory built-in self-test circuit generation method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method for generating a memory built-in self-test circuit according to any one of claims 1 to 6.

10. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is enabled to implement the memory built-in self-test circuit generation method according to any one of claims 1 to 6.

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