Selective passivation contact structure and preparation method and application thereof

Abstract

The invention relates to the technical field of photovoltaic cells, and discloses a selective passivation contact structure, a preparation method thereof and application of the selective passivation contact structure to preparation of a selective TOPCon cell. The method comprises the steps that a first tunneling oxide layer, first thin intrinsic amorphous silicon with the high crystallization rate and second thick intrinsic amorphous silicon with the low crystallization rate are sequentially prepared on the back face of a silicon wafer; boron diffusion doping is carried out, so that the first boron-doped polycrystalline silicon and the second boron-doped polycrystalline silicon have difference in doping concentration and crystallization rate; in the alkali etching process after laser patterning, first boron-doped polycrystalline silicon and a first tunneling oxide layer in a back non-electrode contact area are reserved by utilizing the etching rate difference of an alkaline solution on BSG and two layers of boron-doped polycrystalline silicon with different doping concentrations and crystallization rates; and the first tunneling oxide layer, the first boron-doped polycrystalline silicon and the second boron-doped polycrystalline silicon in the back electrode contact region are reserved. According to the method, the process steps can be simplified, parasitic absorption and recombination are reduced, passivation and transverse transmission are improved, and the cell efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and particularly relates to a selective passivation contact structure, a preparation method thereof, and an application in preparing a selective TOPCon cell. Background Art

[0002] The double-sided TOPCon (Tunnel Oxide Passivated Contact) cell is an important means to improve the efficiency of traditional TOPCon cells. Among them, the double-sided TOPCon cell refers to a solar cell with TOPCon structures prepared on both the front and back surfaces of a silicon wafer; the TOPCon structure includes a tunneling oxide layer and doped polysilicon sequentially deposited on the surface of the silicon wafer. Based on the double-sided TOPCon cell, by further preparing a double-sided selective TOPCon cell (for example, the tunneling oxide layer and doped polysilicon are only located in local areas on the surface of the silicon wafer, and this local area usually refers to the electrode contact area), the parasitic absorption caused by polysilicon can be further reduced, thus improving the photoelectric conversion efficiency of the cell.

[0003] Compared with the relatively well-studied and mature selective phosphorus-doped polysilicon, the research on selective boron-doped polysilicon is less and the process difficulty is higher. On the one hand, this is attributed to the low solubility of boron atoms in polysilicon, so boron atoms are more likely to segregate towards the interfacial oxide during the doping process. It is more difficult to obtain boron-doped polysilicon with both excellent chemical passivation and high doping; on the other hand, different from selective phosphorus-doped polysilicon, after patterning and removing (also known as selective removal or local removal) the boron-doped polysilicon, it is still necessary to ensure that there is a boron-doped layer with a certain concentration in the non-electrode contact area to improve the lateral transport current of the cell and avoid a sharp drop in the fill factor.

[0004] Currently, there are mainly two common preparation methods for selective boron-doped polysilicon. One common preparation method is as follows: as shown in the publication number CN117334788A, first prepare a boron-doped emitter on the surface of the silicon wafer (such as the front surface); then perform laser local opening on the borosilicate glass; and then sequentially prepare a local tunneling oxide layer and local boron-doped polysilicon in the laser opening area on the surface of the boron-doped emitter. This preparation method requires two high-temperature boron diffusion processes (the boron-doped emitter needs to undergo one boron diffusion process; and the preparation of local boron-doped polysilicon also requires one high-temperature annealing process, and this high-temperature annealing process also involves boron diffusion), the process steps increase, and the two high-temperature boron diffusion processes are likely to cause more surface recombination.

[0005] Another common preparation method is as follows: as shown in the publication number CN117096201A, a tunneling oxide layer and intrinsic polysilicon are directly prepared on the surface of a silicon wafer in sequence; then, boron diffusion is carried out to form boron-doped polysilicon with a high doping concentration in the intrinsic polysilicon, and part of the boron atoms pass through the tunneling oxide layer to form a P+ doped layer with a low doping concentration in the silicon wafer. Although this preparation method has a relatively simple process, the passivation effect of the tunneling oxide layer will be seriously affected by a certain number of boron atoms passing through the tunneling oxide layer.

[0006] In addition, there are also some preparation methods. As shown in the publication number CN116914033B, a tunneling oxide layer and polysilicon are first prepared on the surface of a silicon wafer, and then the polysilicon in only the electrode contact area is retained through patterning, and then boron diffusion is carried out to prepare the emitter; however, due to the difference in the solubility of boron in polysilicon and the silicon wafer (this silicon wafer is a crystalline silicon), if a high boron doping concentration is desired in the polysilicon and at the same time the boron atoms are not allowed to diffuse too deep into the silicon wafer to cause an increase in recombination, the boron diffusion process is difficult.

[0007] In summary, no matter which of the above preparation methods is adopted, the current research methods for preparing selectively boron-doped polysilicon are to fabricate boron-doped polysilicon in the electrode contact area and a boron emitter in the non-electrode contact area; this will result in the passivation effect in the non-electrode contact area not being improved, and even the passivation effect will decrease instead, and the recombination problem will be aggravated. Summary of the Invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a selective passivation contact structure, its preparation method, and its application in the preparation of a selective TOPCon cell (especially in the preparation of a double-sided selective TOPCon cell).

[0009] Based on this, the present invention discloses a preparation method of a selective passivation contact structure, including the following preparation steps:

[0010] S1. Sequentially prepare a first tunneling oxide layer and a first intrinsic amorphous silicon on the back surface of the silicon wafer;

[0011] S2. Prepare a second intrinsic amorphous silicon on the back surface of the first intrinsic amorphous silicon, so that the thickness of the second intrinsic amorphous silicon is greater than that of the first intrinsic amorphous silicon, and the crystallization rate of the second intrinsic amorphous silicon is less than that of the first intrinsic amorphous silicon;

[0012] S3. Perform boron diffusion doping to convert the first intrinsic amorphous silicon and the second intrinsic amorphous silicon into the first boron-doped polysilicon and the second boron-doped polysilicon respectively, and form borosilicate glass on the back of the second boron-doped polysilicon; wherein, the thickness of the first boron-doped polysilicon is less than that of the second boron-doped polysilicon, and the crystallization rate of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon, such that the doping concentration of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon;

[0013] S4. Perform laser patterning to selectively remove the borosilicate glass in the back non-electrode contact area to expose the second boron-doped polysilicon in the back non-electrode contact area, and retain the borosilicate glass in the back electrode contact area;

[0014] S5. Etch using an alkaline solution to remove the second boron-doped polysilicon in the back non-electrode contact area, and utilize the differences in doping concentration and crystallization rate between the first boron-doped polysilicon and the second boron-doped polysilicon to retain the first boron-doped polysilicon and the first tunneling oxide layer in the back non-electrode contact area, while the first tunneling oxide layer, the first boron-doped polysilicon and the second boron-doped polysilicon in the back electrode contact area are protected by the borosilicate glass and are retained.

[0015] Preferably, in step S1, the thickness of the first tunneling oxide layer is 0.5 - 2 nm; the preparation method of the first tunneling oxide layer is one of thermal oxidation method, wet oxidation method, nitric acid oxidation method, ozone oxidation method or vapor deposition method;

[0016] The thickness of the first intrinsic amorphous silicon is 10 - 30 nm and its crystallization rate is 15 - 40%; the preparation method of the first intrinsic amorphous silicon is chemical vapor deposition, and the deposition temperature is 400 - 700 °C.

[0017] Preferably, in step S2, the thickness of the second intrinsic amorphous silicon is 150 - 300 nm and its crystallization rate is 3 - 20%; the preparation method of the second intrinsic amorphous silicon is physical vapor deposition, and its deposition temperature is 100 - 300 °C.

[0018] Preferably, in step S3, the boron diffusion source for the boron diffusion doping is BCl 3 or BBr 3 , the doping push temperature is 850 - 950 °C, the sheet resistance after boron diffusion doping is 250 - 450 Ω / □, the doping concentration of the first boron-doped polysilicon is 1 - 3E20 cm -3 , while the doping concentration of the second boron-doped polysilicon is 6 - 9E19 cm -3 ; the thickness of the borosilicate glass is 30 - 70 nm.

[0019] Further preferably, in step S4, the laser patterning process uses an infrared continuous laser, the wavelength of the laser is 700 - 2500 nm, the equivalent spot diameter is 100 - 400 μm, the power is 50 - 100 W, the scanning speed is 15000 - 50000 mm / s, and the area of the backside laser patterning process accounts for 30 - 60% of the total backside area.

[0020] Further preferably, in step S5, the alkaline solution is a NaOH or KOH solution, the concentration of the alkaline solution is 0.5 - 4 vol%, the etching temperature is 40 - 70 °C, and the etching time is 150 - 450 s.

[0021] Preferably, before step S4, the following steps are further included: first, remove the circumferential plating layer and borosilicate glass formed due to boron diffusion doping on the front side and edge of the silicon wafer, while retaining the borosilicate glass as the backside protective layer; then, sequentially prepare a second tunneling oxide layer, phosphorus-doped polysilicon, and phosphosilicate glass on the front side of the silicon wafer.

[0022] Further preferably, step S4 further includes: during the laser patterning process, selectively remove the phosphosilicate glass in the non-electrode contact area on the front side to expose the phosphorus-doped polysilicon in the non-electrode contact area on the front side, and retain the phosphosilicate glass in the electrode contact area on the front side;

[0023] Step S5 further includes: during the etching process using the alkaline solution, also remove the phosphorus-doped polysilicon and the second tunneling oxide layer in the non-electrode contact area on the front side to expose the front side of the silicon wafer in the non-electrode contact area on the front side, while the second tunneling oxide layer and the phosphorus-doped polysilicon in the electrode contact area on the front side are protected by the phosphosilicate glass and are retained.

[0024] The present invention also discloses a selective passivation contact structure, which is prepared by using the preparation method of a selective passivation contact structure described above in the present invention content.

[0025] The present invention also discloses an application of the preparation method of a selective passivation contact structure. Applying the preparation method of a selective passivation contact structure described above in the present invention content to the preparation of a selective TOPCon battery, the application method includes the following steps:

[0026] Step 1: Prepare a selective passivation contact structure by using the preparation method of a selective passivation contact structure according to any one of claims 1 - 8;

[0027] Step 2: Use an alkaline texturing process to form a pyramidal textured surface on the front side of the silicon wafer exposed in the non-electrode contact area on the front side, and clean and remove the phosphosilicate glass in the electrode contact area on the front side and the borosilicate glass in the electrode contact area on the back side;

[0028] Step 3: Prepare a front passivation film on the silicon wafer surface texture in the front non - electrode contact area and the phosphorus - doped polysilicon in the front electrode contact area, and prepare a back passivation film on the back of the first boron - doped polysilicon in the back non - electrode contact area and the second boron - doped polysilicon in the back electrode contact area;

[0029] Step 4: Prepare a front anti - reflection film on the front of the front passivation film, and prepare a back anti - reflection film on the back of the back passivation film;

[0030] Step 5: Perform metallization to form a front electrode and a back electrode respectively; after passing through the front anti - reflection film and the front passivation film in sequence, the front electrode makes an ohmic contact with the phosphorus - doped polysilicon in the front electrode contact area; after passing through the back anti - reflection film and the back passivation film in sequence, the back electrode makes an ohmic contact with the second boron - doped polysilicon in the back electrode contact area.

[0031] Compared with the prior art, the present invention has at least the following beneficial effects:

[0032] The preparation method of the selective passivation contact structure of the present invention prepares a relatively thin and high - crystallization - rate first intrinsic amorphous silicon and a relatively thick and low - crystallization - rate second intrinsic amorphous silicon in sequence on the back of the first tunneling oxide layer; during boron diffusion doping, the improvement of the back boron doping concentration can be achieved, and there are doping - concentration differences and crystallization - rate differences between the first boron - doped polysilicon and the second boron - doped polysilicon; during the alkaline - solution etching after laser patterning, the etching - rate differences of the alkaline solution for borosilicate glass, two layers of boron - doped polysilicon with different doping concentrations and different crystallization rates can be utilized to retain the first boron - doped polysilicon and the first tunneling oxide layer in the back non - electrode contact area, and retain the first tunneling oxide layer, the first boron - doped polysilicon and the second boron - doped polysilicon in the back electrode contact area; thus, the selective passivation contact structure of the present invention can be prepared. This preparation method simplifies the process steps of the double - sided selective TOPCon cell and is conducive to industrial - scale mass production.

[0033] Moreover, the selective passivation contact structure of the present invention realizes passivation contact by retaining the first tunneling oxide layer on the back surface and the first boron-doped polysilicon which is thinner, has a higher boron doping concentration and a higher crystallization rate (compared with the second boron-doped polysilicon). By using this thinner, higher boron-doped concentration and higher crystallization rate first boron-doped polysilicon layer to replace the boron-doped emitter in the traditional non-electrode contact area, the surface recombination is further reduced, the passivation effect in the non-electrode contact area is improved, and good carrier lateral transport is also achieved. Moreover, the selective second boron-doped polysilicon is prepared in the back electrode contact area of the first boron-doped polysilicon (the thinner selectively phosphorus-doped polysilicon is prepared in the front electrode contact area of the silicon wafer), and the thinner first boron-doped polysilicon in the back non-electrode contact area basically does not cause current loss, minimizing the parasitic absorption of light to the greatest extent. Thus, the open circuit voltage, short circuit current, and fill factor of the selective TOPCon battery (especially the double-sided selective TOPCon battery) prepared by using the preparation method of the selective passivation contact structure of the present invention have been well improved, further enhancing the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. is a schematic cross-sectional structure diagram of a double-sided selective TOPCon battery according to this embodiment.

[0035] Description of the reference numerals in the drawings: silicon wafer 1; first tunneling oxide layer 2; first boron-doped polysilicon 3; second boron-doped polysilicon 4; second tunneling oxide layer 5; phosphorus-doped polysilicon 6; back Al 2 O 3 film 7; front Al 2 O 3 film 8; back silicon nitride film 9; front silicon nitride film 10; back electrode 11; front electrode 12. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Embodiment

[0038] A preparation method of a double-sided selective TOPCon battery according to this embodiment is shown in Figure 1 , and includes the following preparation steps:

[0039] Step 1: Clean and polish the silicon wafer 1.

[0040] In Step 1, the silicon wafer 1 is preferably an N-type single-crystalline silicon wafer. The thickness of the silicon wafer 1 is 130 - 180 μm (such as 130 μm), the resistivity is 0.5 - 1.5 Ω·cm (such as 1 Ω·cm), and the size is 182.2 mm × 183.75 mm. The solution used for cleaning and polishing is a heated alkaline solution, which is a NaOH solution or a KOH solution (such as a NaOH solution). The concentration of the alkaline solution is 0.5 - 4 vol% (such as 1.5 vol%), the heating temperature of the alkaline solution is 40 - 70 °C (such as 60 °C), and the time for cleaning and polishing with the alkaline solution is 150 - 400 s (such as 200 s).

[0041] Step 2: Deposit a first tunneling oxide layer 2 and a first intrinsic amorphous silicon layer that is thinner and has a higher crystallization rate on the back of the silicon wafer 1. (It should be noted that since the first intrinsic amorphous silicon has not undergone crystallization conversion treatment at about 800 °C, even though its crystallization rate is relatively high, it is still amorphous silicon.)

[0042] In Step 2, the preparation method of the first tunneling oxide layer 2 is one of thermal oxidation method, wet oxidation method, nitric acid oxidation method, ozone oxidation method or vapor deposition method (such as vapor deposition method); the thickness of the first tunneling oxide layer 2 is 0.5 - 2 nm (such as 1 nm)

[0043] In Step 2, the deposition method of the first intrinsic amorphous silicon is chemical vapor deposition; preferably at least one of LPCVD (low-pressure chemical vapor deposition) method, PECVD (plasma-enhanced chemical vapor deposition) method or APCVD (atmospheric pressure chemical vapor deposition) method, such as LPCVD method; the deposition temperature of the first intrinsic amorphous silicon is 400 - 700 °C (such as 600 °C); the thickness of the first intrinsic amorphous silicon is 10 - 30 nm (such as 20 nm), and the crystallization rate of the first intrinsic amorphous silicon is 15 - 40% (such as 25%).

[0044] Step 3: Continuously deposit a second intrinsic amorphous silicon layer that is thicker and has a lower crystallization rate on the back of the first intrinsic amorphous silicon. That is, the thickness of the second intrinsic amorphous silicon is greater than that of the first intrinsic amorphous silicon, and the crystallization rate of the second intrinsic amorphous silicon is lower than that of the first intrinsic amorphous silicon.

[0045] In Step 3, the deposition method of the second intrinsic amorphous silicon is preferably PVD (physical vapor deposition method), and its deposition temperature is 100 - 300 °C (such as 300 °C); the thickness of the second intrinsic amorphous silicon is 150 - 300 nm (such as 250 nm), and the crystallization rate of the second intrinsic amorphous silicon is 3 - 20% (such as 10%).

[0046] The second intrinsic amorphous silicon is prepared by PVD, and its preparation temperature is relatively low, so the crystallization rate of the second intrinsic amorphous silicon is lower; while the first intrinsic amorphous silicon is prepared by a chemical vapor deposition method such as LPCVD, and its preparation temperature is relatively high, so the crystallization rate of the first intrinsic amorphous silicon is higher.

[0047] Step 4: Boron diffusion doping is carried out on the back of the silicon wafer 1 processed in Step 3 through a diffusion-push-back oxidation process (that is, the process of this boron diffusion doping includes the following three stages carried out in sequence: diffusion, push, and back oxidation), so that the first intrinsic amorphous silicon and the second intrinsic amorphous silicon are respectively converted into the first boron-doped polysilicon 3 and the second boron-doped polysilicon 4. Thus, after being processed in Step 4, a global passivation contact structure composed of the first tunneling oxide layer 2, the first boron-doped polysilicon 3, and the second boron-doped polysilicon 4 can be formed on the back of the silicon wafer 1, and boron silicate glass (BSG) is formed on the back of the second boron-doped polysilicon 4. In addition, boron diffusion doping will also form a wrap-around coating and BSG in the local areas on the front and edge of the silicon wafer 1.

[0048] Among them, the first boron-doped polysilicon 3 is formed by boron diffusion doping of the first intrinsic amorphous silicon, and the second boron-doped polysilicon 4 is formed by boron diffusion doping of the second intrinsic amorphous silicon. Therefore, the thickness of the first boron-doped polysilicon 3 is still smaller than that of the second boron-doped polysilicon 4 (the thickness of the first boron-doped polysilicon 3 refers to the thickness of the first intrinsic amorphous silicon, and the thickness of the second boron-doped polysilicon 4 refers to the thickness of the second intrinsic amorphous silicon); moreover, because there is a crystallization rate difference between the first intrinsic amorphous silicon and the second intrinsic amorphous silicon, during the process of boron diffusion doping in Step 4, the boron diffusion source is more likely to migrate to the place with a higher crystallization rate (such as the first intrinsic amorphous silicon), so the doping concentration of the first boron-doped polysilicon 3 is greater than that of the second boron-doped polysilicon 4, and the crystallization rate of the first boron-doped polysilicon 3 is still higher than that of the second boron-doped polysilicon 4. After boron diffusion doping, the crystallization rate of the first boron-doped polysilicon 3 is improved compared with that of the first intrinsic amorphous silicon, and the crystallization rate of the first boron-doped polysilicon 3 is 60-80% (such as 75%); and the crystallization rate of the second boron-doped polysilicon 4 is also improved compared with that of the second intrinsic amorphous silicon, and the crystallization rate of the second boron-doped polysilicon 4 is 40-60% (such as 55%).

[0049] In Step 4, the boron diffusion source for boron diffusion doping is BCl 3 or BBr 3 (such as BCl 3 );The diffusion temperature is 800-880 °C (such as 840 °C), the push temperature is 850-950 °C (such as 910 °C), and the back oxidation temperature is 850-900 °C (such as 890 °C). The sheet resistance after boron diffusion doping is 250-450 Ω / square (such as 300 Ω / square), and the doping concentration of the first boron-doped polysilicon 3 is 1-3E20 cm-3 (such as 1.5E20 cm -3 ), the doping concentration of the second boron-doped polysilicon 4 is 6 - 9E19 cm -3 (such as 8E19 cm -3 ); the thickness of the BSG is 30 - 70 nm (such as 50 nm).

[0050] Step 5: Remove the bypass plating layer and BSG formed on the front and edge of the silicon wafer 1 due to boron diffusion doping through chain cleaning, while retaining the BSG on the back as a back protective layer.

[0051] In Step 5, the solution for chain cleaning is an acid solution, preferably an HF solution, and its concentration is 3 - 10 vol% (such as 5 vol%).

[0052] Step 6: Perform alkaline polishing on the front of the silicon wafer 1 to completely remove the bypass plating layer (such as the boron-doped layer) formed on the front due to boron diffusion doping.

[0053] In Step 6, the alkaline solution used for alkaline polishing is a NaOH solution or a KOH solution (such as a NaOH solution), the concentration of the alkaline solution is 0.5 - 4 vol% (such as 1.5 vol%), the reaction temperature for alkaline polishing is 50 - 70 °C (such as 60 °C), and the time for alkaline polishing is 150 - 400 s (such as 250 s).

[0054] Step 7: Deposit a second tunneling oxide layer 5 and phosphorus-doped amorphous silicon on the front of the silicon wafer 1 in sequence.

[0055] In Step 7, the deposition method of the second tunneling oxide layer 5 and phosphorus-doped amorphous silicon is the PECVD method or the PVD method (such as the PVD method), the thickness of the second tunneling oxide layer 5 is 0.5 - 2 nm (such as 0.8 nm), and the thickness of the phosphorus-doped amorphous silicon is 50 - 150 nm (such as 80 nm).

[0056] Step 8: Perform high-temperature annealing on the silicon wafer 1 to activate the phosphorus atoms in the phosphorus-doped amorphous silicon and convert the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon 6.

[0057] In Step 8, the temperature for high-temperature annealing is 800 - 900 °C (such as 850 °C). After annealing, the doping concentration of the phosphorus-doped polysilicon 6 is 3 - 6E20 cm -3 (such as 4.5E20 cm -3 ); the thickness of the phosphorus-doped polysilicon 6 refers to the thickness of the phosphorus-doped amorphous silicon.

[0058] After being processed by Step 8, a global passivation contact structure composed of the second tunneling oxide layer 5 and phosphorus-doped polysilicon 6 can be formed on the front of the silicon wafer 1, and phosphorus-silicon glass (PSG) can be formed on the front of the phosphorus-doped polysilicon 6.

[0059] Step 9: Perform laser patterning (i.e., laser selective processing) on the back and front of the silicon wafer 1 after the treatment in Step 8, and selectively etch away the BSG in the non-electrode contact area on the back and the PSG in the non-electrode contact area on the front using a laser.

[0060] In Step 9, the laser patterning on the front and back is carried out under the same process conditions. Taking the laser patterning on the back as an example, the process conditions are as follows: The laser uses an infrared continuous laser with a laser wavelength of 700 - 2500 nm (such as 1064 nm), the equivalent diameter of the light spot is 100 - 400 μm (such as 100 μm), the laser power is 50 - 100 W (such as 100 W), the laser scanning speed is 15000 - 50000 mm / s (such as 30000 mm / s), and the area of the laser patterning on the back accounts for 30 - 60% of the total back area (such as 58%). Therefore, the area of the second boron-doped polysilicon in the back electrode contact area prepared in the subsequent Step 10 accounts for 40 - 70% of the total back area (such as 42%).

[0061] Step 10: Perform etching treatment using an alkaline solution to etch away the phosphorus-doped polysilicon 6 in the non-electrode contact area on the front and the second tunneling oxide layer 5 in the non-electrode contact area on the front (at this time, the front of the silicon wafer 1 in the non-electrode contact area is exposed), and etch away the relatively thick and low-crystallinity second boron-doped polysilicon 4 in the non-electrode contact area on the back.

[0062] Use the alkaline solution to etch away the phosphorus-doped polysilicon 6 in the non-electrode contact area on the front, the second tunneling oxide layer 5 in the non-electrode contact area on the front, and the second boron-doped polysilicon 4 in the non-electrode contact area on the back (this second boron-doped polysilicon 4 has a low doping concentration, low crystallinity, and is relatively thick), while the first boron-doped polysilicon 3 in the non-electrode contact area on the back and the first tunneling oxide layer 2 in the non-electrode contact area on the back are retained. The second tunneling oxide layer 5 and the phosphorus-doped polysilicon 6 in the front electrode contact area are not etched because they are protected by the PSG (because the etching rate of the alkaline solution for the phosphorus-doped polysilicon 6 is much greater than that for the PSG). Moreover, the first tunneling oxide layer 2, the first boron-doped polysilicon 3, and the second boron-doped polysilicon 4 in the back electrode contact area are not etched because they are protected by the BSG; the relatively thin first boron-doped polysilicon 3 in the non-electrode contact area on the back is not etched by the alkaline solution either because of its high doping concentration and high crystallinity (that is, by using the difference in doping concentration and crystallinity between the second boron-doped polysilicon 4 and the first boron-doped polysilicon 3, the second boron-doped polysilicon 4 in the non-electrode contact area on the back is etched away by the alkaline solution, and the first boron-doped polysilicon 3 in the non-electrode contact area on the back is retained), and the first tunneling oxide layer 2 in the non-electrode contact area on the back is retained because it is protected by the first boron-doped polysilicon 3.

[0063] This is because: the etching rate of the alkaline solution on the second boron-doped polysilicon 4 is much greater than that on the BSG. Therefore, the second boron-doped polysilicon 4 in the back electrode contact area is not etched due to the protection of the BSG. And the etching rate of the alkaline solution on boron-doped polysilicon will decrease as the boron doping concentration increases. When the boron doping concentration is increased to 1E20 cm -3 or above, the etching basically stops; moreover, the crystallization rate is related to the defect density. The higher the crystallization rate, the lower the defect density, which will also cause the etching rate of the alkaline solution to decrease. Therefore, the high doping concentration and high crystallization rate of the thinner first boron-doped polysilicon 3 in the back non-electrode contact area jointly prevent the etching of the alkaline solution, enabling the first boron-doped polysilicon 3 in the back non-electrode contact area and the first tunneling oxide layer 2 in the back non-electrode contact area to be retained, while the second boron-doped polysilicon 4 in the back non-electrode contact area is etched away. In this way, both the parasitic absorption of light is reduced, good lateral transmission is achieved, and an efficient passivation effect is ensured.

[0064] In step 10, the alkaline solution is a NaOH solution or a KOH solution (such as a NaOH solution), the concentration of the alkaline solution is 0.5 - 4 vol% (preferably 1 - 3 vol%, such as 1 vol%), the etching temperature is 40 - 70 °C (such as 60 °C), and the etching time is 150 - 450 s (such as 200 s).

[0065] Among them, the above steps 2 - 4 and steps 9 - 10 are a preparation method of a selective boron-doped polysilicon passivation contact structure in this embodiment. This selective boron-doped polysilicon passivation contact structure, as Figure 1 shown, includes: a silicon wafer 1, a first tunneling oxide layer 2 and a first boron-doped polysilicon 3 provided on the back surface of the silicon wafer 1, and a second boron-doped polysilicon 4 provided in the back electrode contact area of the first boron-doped polysilicon 3.

[0066] Among them, the above steps 2 - 10 are a preparation method of a selective passivation contact structure in this embodiment. This selective passivation contact structure, as Figure 1 shown, includes: a silicon wafer 1, a selective boron-doped polysilicon passivation contact structure provided on the back surface of the silicon wafer 1, and a selective phosphorus-doped polysilicon 6 passivation contact structure provided on the front surface of the silicon wafer 1 (this selective phosphorus-doped polysilicon 6 passivation contact structure includes a second tunneling oxide layer 5 and a phosphorus-doped polysilicon 6 provided in sequence in the front electrode contact area of the silicon wafer 1).

[0067] Step 11: Form a pyramidal texture on the front surface of the silicon wafer 1 exposed in the front non-electrode contact area through an alkaline texturing process, and clean and remove the PSG in the front electrode contact area and the BSG in the back electrode contact area.

[0068] In Step 11, for the alkaline texturing process, a NaOH solution or a KOH solution (such as a KOH solution) is used. The heating temperature is 30 - 70°C (such as 65°C), and the texturing time is 100 - 300 s (such as 200 s).

[0069] In Step 12, by using the ALD (Atomic Layer Deposition) method, an Al 2 O 3 film with a thickness of 2 - 10 nm (such as 6 nm) is deposited on both the front and back surfaces of the silicon wafer 1 processed in Step 11 as a passivation film. At this time, an Al 2 O 3 film 8 is deposited on both the front surface of the silicon wafer 1 exposed in the non - electrode contact area on the front side and the front surface of the phosphorus - doped polysilicon 6 in the front - side electrode contact area; while an Al 2 O 3 film 7 is deposited on both the back surface of the first boron - doped polysilicon 3 exposed in the non - electrode contact area on the back side and the back surface of the second boron - doped polysilicon 4 in the back - side electrode contact area.

[0070] In Step 13, by using the PECVD method, a silicon nitride film with a thickness of 60 - 80 nm (such as 75 nm) is deposited on both the front and back surfaces of the silicon wafer 1 processed in Step 12 as an antireflection film. At this time, a front - side silicon nitride film 10 is deposited on the front surface of the front - side Al 2 O 3 film 8; while a back - side silicon nitride film 9 is deposited on the back surface of the back - side Al 2 O 3 film 7.

[0071] In Step 14, metallization is performed on the front and back surfaces of the silicon wafer 1 processed in Step 13 respectively to form a front - side electrode 12 and a back - side electrode 11. The front - side electrode 12 passes through the front - side silicon nitride film 10 and the front - side Al 2 O 3 film 8 in sequence and then makes an ohmic contact with the phosphorus - doped polysilicon 6 in the front - side electrode contact area. The back - side electrode 11 passes through the back - side silicon nitride film 9 and the back - side Al 2 O 3 film 7 in sequence and then makes an ohmic contact with the second boron - doped polysilicon 4 in the back - side electrode contact area.

[0072] After being processed in Step 14, a double - sided selective TOPCon cell as shown in Figure 1 is obtained.

[0073] The double-sided selective TOPCon cell prepared by the present invention places the thicker second boron-doped polysilicon 4 in the back electrode contact area, and also adopts a selective passivation contact structure on the front side (that is, only the second tunneling oxide layer 5 and phosphorus-doped polysilicon 6 are retained in the front electrode contact area), which can minimize the parasitic absorption of light; and after laser patterning, by using the difference in the etching rates of PSG, BSG, boron-doped polysilicon with different boron doping concentrations and different crystallization rates, etc. in an alkaline solution, the preparation of the selective passivation contact structure on the front and back sides can be achieved by etching with the alkaline solution, and the first tunneling oxide layer 2 on the back and the thinner first boron-doped polysilicon 3 with a higher boron doping concentration and a higher crystallization rate can be retained (using a thinner first boron-doped polysilicon 3 with a higher boron doping concentration and a higher crystallization rate to replace the boron-doped emitter in the traditional non-electrode contact area). Therefore, while reducing parasitic absorption, passivation contact can be achieved, surface recombination can be reduced, the passivation performance of the back non-electrode contact area and the lateral transport performance of carriers can be improved; and then through alkali texturing and the preparation of the back Al 2 O 3 film 7, the preparation of the pyramid structure texture on the front non-electrode contact area and the laser damage repair on the front and back can be completed, further reducing recombination, further improving the passivation performance, and reducing the process steps (for example, in the conventional preparation process of the cell, alkali texturing is placed in the first step; while in this embodiment, the alkali texturing process step is placed in step 11, which can not only complete the preparation of the pyramid structure texture on the front non-electrode contact area, but also repair the laser damage without adding additional process steps), which is beneficial to industrial scale production.

[0074] Comparative example

[0075] A preparation method of a double-sided selective TOPCon cell in this comparative example specifically refers to the above-mentioned embodiment, and the main difference from the above-mentioned embodiment is that:

[0076] This comparative example omits step 2 of the above-mentioned embodiment. Moreover, in step 3 of the above-mentioned embodiment, this comparative example is changed to: directly depositing a first tunneling oxide layer and a layer of intrinsic amorphous silicon on the back of the silicon wafer in sequence. The preparation method and thickness of the first tunneling oxide layer in this comparative example both refer to the first tunneling oxide layer in step 2 of the above-mentioned embodiment. The deposition method of the intrinsic amorphous silicon in this comparative example is PVD, its deposition temperature is 300 °C, and the thickness of the intrinsic amorphous silicon in this comparative example is 250 nm (that is, the deposition method and thickness of the intrinsic amorphous silicon in this comparative example both refer to the second intrinsic amorphous silicon in step 3 of the above-mentioned embodiment); therefore, after the alkaline solution etching treatment in step 10 of the above-mentioned embodiment, the silicon wafer in the back non-electrode contact area of this comparative example is exposed, and the first tunneling oxide layer and boron-doped polysilicon are retained in the back electrode contact area.

[0077] Performance test

[0078] Performance tests were respectively carried out on the double-sided selective TOPCon cells prepared in the above-mentioned examples and comparative examples, and the test results are shown in Table 1 below. In Table 1, Voc is the open-circuit voltage, FF is the fill factor, Isc is the short-circuit current, and Eta is the photoelectric conversion efficiency of the cell.

[0079] Table 1

[0080] Example Voc (mV) FF (%) Isc (A) Eta (%) Example 735.6 85.57 14.25 26.38 Comparative Example 725.1 83.23 14.16 25.64

[0081] It can be seen from the above test results in Table 1 that compared with the double-sided selective TOPCon cells of the above-mentioned comparative examples, the open-circuit voltage, fill factor, short-circuit current and photoelectric conversion efficiency of the double-sided selective TOPCon cells prepared in the above-mentioned examples of the present invention have all been further improved.

[0082] It can be seen that: in the above-mentioned examples of the present invention, by retaining the first tunneling oxide layer and the first boron-doped polysilicon with a relatively thin thickness, a relatively high boron doping concentration and a relatively high crystallization rate on the back surface, the passivated contact is realized, and a relatively thin, boron-doped polysilicon with a relatively high boron doping concentration and a relatively high crystallization rate is used to replace the boron-doped emitter in the traditional non-electrode contact area, further reducing the surface recombination, improving the passivation effect in the non-electrode contact area, and realizing good carrier lateral transport; moreover, by placing the relatively thin selectively phosphorus-doped polysilicon on the light-receiving surface (i.e., the front surface) and the selectively second boron-doped polysilicon on the back surface, the relatively thin first boron-doped polysilicon in the non-electrode contact area on the back surface basically does not cause current loss, and the parasitic absorption of light is minimized to the greatest extent. Thus, the open-circuit voltage, short-circuit current and fill factor of the double-sided selective TOPCon cells prepared in the examples of the present invention have been well improved, and the photoelectric conversion efficiency of the cells has been further enhanced.

[0083] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0084] The technical solutions provided by the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for preparing a selectively passivated contact structure, characterized in that: The method comprises the following preparation steps: S1, sequentially preparing a first tunneling oxide layer and a first intrinsic amorphous silicon on the back side of the silicon wafer; S2, preparing a second intrinsic amorphous silicon on the back side of the first intrinsic amorphous silicon, so that the thickness of the second intrinsic amorphous silicon is greater than that of the first intrinsic amorphous silicon, and the crystallization rate of the second intrinsic amorphous silicon is less than that of the first intrinsic amorphous silicon; S3, performing boron diffusion doping to convert the first intrinsic amorphous silicon and the second intrinsic amorphous silicon into the first boron-doped polysilicon and the second boron-doped polysilicon respectively, and forming borosilicate glass on the back of the second boron-doped polysilicon; wherein the thickness of the first boron-doped polysilicon is less than that of the second boron-doped polysilicon, and the crystallization rate of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon, so that the doping concentration of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon; S4, performing laser patterning to selectively remove the borosilicate glass in the back non-electrode contact area to expose the second boron-doped polysilicon in the back non-electrode contact area, and retaining the borosilicate glass in the back electrode contact area; S5. Use alkaline solution for etching to remove the second boron-doped polysilicon in the back non-electrode contact area, and use the difference in doping concentration and crystallization rate between the first boron-doped polysilicon and the second boron-doped polysilicon to retain the first boron-doped polysilicon and the first tunneling oxide layer in the back non-electrode contact area, while the first tunneling oxide layer, the first boron-doped polysilicon and the second boron-doped polysilicon in the back electrode contact area are protected by borosilicate glass and retained.

2. The method for preparing a selective passivation contact structure according to claim 1, characterized in that: In step S1, the thickness of the first tunneling oxide layer is 0.5-2 nm; the preparation method of the first tunneling oxide layer is one of thermal oxygen oxidation, wet oxygen oxidation, nitric acid oxidation, ozone oxidation or vapor deposition; The thickness of the first intrinsic amorphous silicon is 10-30 nm, and the crystallization rate thereof is 15-40%. The preparation method of the first intrinsic amorphous silicon is chemical vapor deposition, and the deposition temperature is 400-700°C.

3. The method for preparing a selective passivation contact structure according to claim 1, characterized in that: In step S2, the thickness of the second intrinsic amorphous silicon is 150-300 nm, and the crystallization rate thereof is 3-20%. The second intrinsic amorphous silicon is prepared by physical vapor deposition, and the deposition temperature thereof is 100-300°C.

4. The method for preparing a selective passivation contact structure according to claim 1, characterized in that: In step S3, the boron diffusion source of the boron diffusion doping is BCl3 or BBr3, the doping advancement temperature is 850-950°C, and the square resistance after boron diffusion doping is The doping concentration of the first boron-doped polysilicon is 1 to 3E20 cm -3 , and the doping concentration of the second boron-doped polysilicon is 6 to 9E19 cm -3 ; The thickness of the borosilicate glass is 30 to 70 nm.

5. A method for preparing a selective passivation contact structure according to claim 1 or 4, characterized in that: In step S4, the laser patterning process uses an infrared continuous laser with a wavelength of 700 to 2500 nm, a spot equivalent diameter of 100 to 400 μm, a power of 50 to 100 W, a scanning speed of 15,000 to 50,000 mm / s, and the back laser patterning process area accounts for 30 to 60% of the total back area.

6. A method for preparing a selective passivation contact structure according to any one of claims 1 to 4, characterized in that: In step S5, the alkaline solution is a NaOH or KOH solution, the concentration of the alkaline solution is 0.5-4 vol%, the etching temperature is 40-70° C., and the etching time is 150-450 s.

7. The method for preparing a selective passivation contact structure according to claim 1, characterized in that: Before step S4, the following steps are also included: first, the coating layer and borosilicate glass formed on the front and edge of the silicon wafer due to boron diffusion doping are removed, while retaining the borosilicate glass as a back protective layer; and then, a second tunneling oxide layer, phosphorus-doped polysilicon and phosphosilicate glass are sequentially prepared on the front of the silicon wafer.

8. The method for preparing a selective passivation contact structure according to claim 7, characterized in that: The step S4 further comprises: during the laser patterning process, selectively removing the phosphosilicate glass in the front non-electrode contact area to expose the phosphorus-doped polysilicon in the front non-electrode contact area, and retaining the phosphosilicate glass in the front electrode contact area; The step S5 also includes: in the process of etching with the alkaline solution, the phosphorus-doped polysilicon and the second tunneling oxide layer in the front non-electrode contact area are removed to expose the front side of the silicon wafer in the front non-electrode contact area, while the second tunneling oxide layer and the phosphorus-doped polysilicon in the front electrode contact area are protected by the phosphosilicate glass and retained.

9. A selective passivation contact structure, characterized in that: It is prepared by the method for preparing a selective passivation contact structure as described in any one of claims 1 to 8.

10. Application of a method for preparing a selectively passivated contact structure, characterized in that: The method for preparing a selective passivation contact structure according to any one of claims 1 to 8 is applied to preparing a selective TOPCon cell, and the application method comprises the following steps: Step 1: preparing a selective passivation contact structure by using a method for preparing a selective passivation contact structure according to any one of claims 1 to 8; Step 2: using an alkali texturing process to form a pyramid-structured textured surface on the exposed front side of the silicon wafer in the front non-electrode contact area, and cleaning and removing the phosphosilicate glass in the front electrode contact area and the borosilicate glass in the back electrode contact area; Step 3: preparing a front passivation film on the front surface of the silicon wafer velvet in the front non-electrode contact area and the front surface of the phosphorus-doped polysilicon in the front electrode contact area, and preparing a back passivation film on the back surface of the first boron-doped polysilicon in the back non-electrode contact area and the second boron-doped polysilicon in the back electrode contact area; Step 4: preparing a front anti-reflection film on the front side of the front passivation film, and preparing a back anti-reflection film on the back side of the back passivation film; Step 5: Perform metallization treatment to form a front electrode and a back electrode respectively; after the front electrode passes through the front anti-reflection film and the front passivation film in sequence, it makes ohmic contact with the phosphorus-doped polysilicon in the front electrode contact area; after the back electrode passes through the back anti-reflection film and the back passivation film in sequence, it makes ohmic contact with the second boron-doped polysilicon in the back electrode contact area.

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