System and method for communicating over multifunctional pins

Abstract

In an I2C communication system, a dedicated address pin enables a primary device to individually address a plurality of secondary devices. When the first transmission is performed from the primary device, the logic level on each dedicated address pin can be stored in each secondary device. Address decoder circuitry within each secondary device can decode transmissions from the primary device using the saved address pin values. Then, since the logic level on the address pin has been saved, the dedicated address pin can be reused for separate functions.

Description

[0001] Priority

[0002] This application claims priority to co-owned U.S. Patent Application No. 63 / 441,374, filed on January 26, 2023, the entire content of which is hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to pins on an integrated circuit, and more particularly to systems and methods for communicating through multifunctional pins. Background Art

[0004] Integrated circuit components can communicate via one of many communication protocols. To reduce the number of external pins required for communication, communication protocols that require only two pins have been developed, including but not limited to Inter-Integrated Circuit (I2C), System Management Bus (SMBus), and Serial Peripheral Interface (SPI). The term "pin" as used herein is not meant to be limited to a particular structure, but rather means to include any connection, including but not limited to pads, wires, or balls.

[0005] The I2C communication protocol is one such protocol for connecting multiple integrated circuit components in a single system. I2C is a 2-wire serial interface that utilizes a Serial Clock Line (SCL) and a Serial Data Line (SDA). The I2C protocol relies on specific patterns of signals on the SCL line and the SDA line to indicate the start (START) and end (STOP) of a transmission.

[0006] An I2C system can include a master device that can drive voltages of specific patterns on the SCL line and the SDA line, and at least one slave device that can receive the SCL line and the SDA line as inputs and can control the voltage of the SDA line at predetermined times. The voltage of a specific pattern on the SCL line can be referred to as a clock signal, and the voltage of a specific pattern on the SDA line can be referred to as a data signal.

[0007] I2C is a shared bus protocol in which all devices are connected to the SCL line and the SDA line. Pull-up resistors can be connected between the SCL line and the power supply. Pull-up resistors can be connected between the SDA line and the power supply. To allow communication with fewer devices than all devices connected to the SCL line and the SDA line, chip address values are assigned to individual devices. The master device can transmit a clock signal via the SCL line and transmit a data signal via the SDA line, and when a slave device decodes the received clock signal and data signal and the decoded chip address matches the chip address value, the remainder of the data transmission is only acted upon by the slave device that matches the chip address value, and the data transmission is ignored by other slave devices.

[0008] It may be desirable to have multiple instances of the same slave device in a single I2C system. In one example among various examples, a multi-channel audio system may include multiple audio amplifiers, one amplifier per channel. For the purposes of this discussion, there may be 4 audio amplifiers in a multi-channel system. The 4 audio amplifiers may be referred to as left front, right front, left rear, and right rear, respectively. When the chip address value of the audio amplifier is sent via the SCL line and the SDA line, all 4 amplifiers will recognize the chip address value, and all 4 amplifiers will act on the remainder of the data transmission. As one example among various examples, a request to lower the volume may be sent and acted upon by all 4 audio amplifiers via a single data transmission on the I2C bus.

[0009] In one example among various examples, a user may desire to modify the volume at only one of the audio amplifiers. As one example among various examples, in a vehicle implementation, the driver may desire to modify the volume by setting the right front, left rear, and right rear amplifiers to full attenuation to focus the sound on the driver's position. The I2C protocol allows at least one address pin to enable addressing of individual instances of the slave device.

[0010] In operation, the chip address value may include a common chip address value assigned to the most significant bit of the chip address value and at least one least significant bit of the least significant bits of the chip address value, the variable chip address value being set by dedicated address pins on the slave device. In one example among various examples using two dedicated address pins, the common chip address value may be shared by all identical slave devices, and the two least significant bits of the chip address value may be set by the voltage on the dedicated address pins of the respective slave device. The user may use resistor pull-ups and resistor pull-downs to set the variable chip address value for each of the 4 devices. In other examples, a microcontroller or other host device may set the voltage on the dedicated address pins.

[0011] In the above addressing scheme, the dedicated address pins are only used to set the address of the slave device and not for other functions of the slave device. In very small devices, dedicating only two pins for the initial addressing function may limit the functionality of the device.

[0012] There is a need for an I2C addressing scheme that allows the address pins to be reused for other functions. SUMMARY

[0013] Examples herein implement a system where the address pins can be used as multifunctional pins.

[0014] According to one aspect, example implementations herein include a device having a clock input port, a bidirectional data port, and an address port. An address decoder circuit may be coupled to the clock input port, the bidirectional data port, and the address port. The address decoder circuit may receive a clock signal from the clock input port and may receive a data signal from the bidirectional data port, and may decode the clock signal and the data signal to generate a decoded address field. The address decoder circuit may store the value of the address port in a non-transitory storage location and may compare at least one bit of the decoded address field with the stored value of the address port. An internal control circuit may output a control signal to a pull-down circuit based on a predetermined condition, and the pull-down circuit may selectively couple the address port to a ground node based on the value of the control signal.

[0015] According to one aspect, examples herein enable a system having a master device to drive a clock bus and a data bus and be coupled to a control bus. The system may include a plurality of slave devices, the plurality of slave devices including a clock input port coupled to the clock bus, a bidirectional data port coupled to the data bus, and an address port coupled to the control bus. An address decoder circuit may be coupled to the clock input port, the bidirectional data port, and the address port. The address decoder circuit may receive a clock signal from the clock input port and may receive a data signal from the bidirectional data port, and may decode the clock signal and the data signal to generate a decoded address field. The address decoder circuit may store the value of the address port in a non-transitory storage location and may compare at least one bit of the decoded address field with the stored value of the address port. An internal control circuit may output a control signal to a pull-down circuit based on a predetermined condition, and the pull-down circuit may selectively couple the address port to a ground node based on the value of the control signal.

[0016] According to one aspect, examples herein may implement a method that includes the following operations: receiving, at a slave device, a data transmission from a master device; storing the value of the address port to a stored address location in a non-transitory storage device; decoding the data transmission to generate a decoded address field; comparing at least one bit of the decoded address field with the stored address port value; and pulling down the voltage of the address port based on a predetermined condition of the slave device to signal a status condition to the master device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A Illustrates one example among various examples of an addressing scheme.

[0018] Figure 1B Illustrates another example of an addressing scheme.

[0019] Figure 2 Illustrates one example among various examples of an I2C device including a multifunctional address pin.

[0020] Figure 3 An example of one of various examples of a system illustrating two I2C devices, each device including a multifunctional address pin.

[0021] Figure 4 Another example of a system illustrating two I2C devices, each device including a multifunctional address pin.

[0022] Figure 5 A method of configuring and using a multifunctional address pin is illustrated. Detailed Description

[0023] Figure 1A An example of one of various examples of addressing scheme 100 is illustrated. Address field 180 may represent an address used in communication between a master device and one or more slave devices. Address field 180 may include a plurality of bits from the most significant bit 182 to the least significant bit 183. The slave device may include a chip address value. When the address field 180 sent from the master device matches the chip address value of the slave device, the slave device may respond to the communication from the master device. When the address field 180 sent from the master device does not match the chip address value of the slave device, the slave device may ignore the communication.

[0024] In operation, the seven most significant bits 181 of the address field 180 may represent a common address. The common address may be hard-coded in the slave device by a memory component including but not limited to a register or a read-only memory. The least significant bit 183 may represent a variable address. The least significant bit 183 may also be referred to as address bit A0. Address bit A0 may be set by an external pin value. Address bit A0 allows the master device to selectively address two groups of slave devices.

[0025] Figure 1A The example is illustrated with an 8-bit address field, but this is not intended to be limiting. The address field may include more than 8 bits or less than 8 bits.

[0026] Figure 1B An example of one of various examples of addressing scheme 150 is illustrated. Address field 190 may represent an address used in communication between a master device and one or more slave devices. Address field 190 may include a plurality of bits from the most significant bit 192 to the least significant bit 193. The slave device may include a chip address value. When the address field 190 sent from the master device matches the chip address value of the slave device, the slave device may respond to the communication from the master device. When the address field 190 sent from the master device does not match the chip address value of the slave device, the slave device may ignore the communication.

[0027] In operation, the six most significant bits 191 of the address field 190 may represent a common address. The common address may be hard-coded in the slave device by a memory component, which includes but is not limited to registers or read-only memories. The least significant bit 193 may represent the first bit of a variable address. The least significant bit 193 may also be referred to as address bit A0. The address bit A0 may be set by an external pin value. The second least significant bit 194 may represent the second bit of a variable address. The second least significant bit 194 may also be referred to as address bit A1. The address bit A1 may be set by an external pin value. The address bit A0 and the address bit A1 allow the master device to selectively address up to four groups of slave devices.

[0028] Figure 1B The example of illustrates an 8-bit address field, but this is not intended to be restrictive. The address field may include more than 8 bits or fewer than 8 bits.

[0029] Figure 2 Illustrates one example among various examples of system 200 including multifunctional address pins. The master device 250 may include an output clock port 251. The master device 250 may include a bidirectional data port 252. The master device 250 may be an I2C host device capable of communicating with one or more slave devices using the I2C communication protocol. In Figure 2 the example illustrated in Figure 2 , the master device 250 may communicate with the slave device 210.

[0030] The master device 250 may be a microcontroller. A microcontroller is a system-on-chip that typically includes a processor, memory, multiple input / output ports, and various peripheral devices. In particular, various peripheral devices may be provided, such as configurable logic units, complementary waveform / output generators, dedicated arithmetic units, numerically controlled oscillators, and programmable switched-mode controllers. The microcontroller may include a host controller that communicates with the peripheral devices through a communication protocol, which includes but is not limited to I2C. The master device 250 may include a digital processor having memory and multiple programmable input and output ports. The master device 250 may be a host device capable of communicating with multiple slave devices through a shared bus protocol.

[0031] The slave device 210 may include the peripheral devices as described above, including but not limited to sensors, amplifiers, oscillators, battery gauges, data converters, or logic devices. The slave device 210 may communicate with the master device 250 using a communication protocol, which includes but is not limited to I2C.

[0032] The output clock port 251 may be coupled to at least one slave device via the shared bus 253. The shared bus 253 may also be referred to as the SCL bus or the shared SCL bus. The bidirectional data port 252 may be coupled to at least one slave device via the shared bus 254. The shared bus 254 may also be referred to as the SDA bus or the shared SDA bus. InFigure 2 In the example illustrated, system 200 includes one secondary device 210, but this is not intended to be limiting. Other examples may include more than one secondary device. In examples including more than one secondary device, shared bus 253 may be shared among more than one secondary device, and shared bus 254 may be shared among more than one secondary device. Shared bus 253 and shared bus 254 may be coupled to a pull-up resistor or a pull-down resistor as specified by the communication protocol.

[0033] Secondary device 210 may include a clock input port 211. Clock input port 211 may be coupled to shared SCL bus 253. Secondary device 210 may include a bidirectional data port 212. Bidirectional data port 212 may be coupled to shared SDA bus 254. Secondary device 210 may include a first address port 213. First address port 213 may be coupled to a supply voltage through a pull-up resistor 215. The value of first address port 213 may be stored in non-transitory memory location 281, and the value stored in non-transitory memory location 281 may set the value of address bit A0 of the chip address value of secondary device 210. The remaining bits of the chip address value of the secondary device may be stored in the memory in secondary device 210 or otherwise hard-coded in secondary device 210.

[0034] In operation, master device 250 may send a clock signal on shared SCL bus 253 and may send a data signal on shared SDA bus 254. Secondary device 210 may receive the sent data signal on bidirectional data port 212. Secondary device 210 may receive the sent clock signal on clock input port 211. Address decoder circuit 280 in secondary device 210 may receive inputs from clock input port 211, bidirectional data port 212, and non-transitory memory location 281, and decode an address field based on the signals received at clock input port 211 and bidirectional data port 212 and the value stored in non-transitory memory location 281. Secondary device 210 may include a chip address value stored in the memory in secondary device 210 or otherwise hard-coded in secondary device 210. Address decoder circuit 280 may compare the decoded address field with the chip address value.

[0035] Secondary device 210 may respond to the transmission using the decoded address field that matches the chip address value. The chip address value may include a common address and a variable address. In Figure 2 the example illustrated, the variable address of the chip address value may be set by the value stored in non-transitory memory location 281. In Figure 2 the example illustrated, the variable chip address value may be the least significant bit of the chip address value, and the common chip address value may be the most significant bit of the chip address value.

[0036] When making a first transmission from the master device 250, the address decoder circuit 280 may sample the voltage at the first address port 213. The address decoder circuit 280 may store the sampled value of the first address port 213 in a non-transitory storage location 281, including but not limited to a volatile register or latch, which stores the value of the first address port 213 as long as the device is receiving a supply voltage. In Figure 2 In the example illustrated in, the address decoder circuit 280 may store the value of the first address port 213, thereby storing a logic high value in the non-transitory storage location 281.

[0037] The value stored in the non-transitory storage location 281 may be used by the address decoder circuit 280 as a variable part of the chip address value (address bit A0). The address decoder circuit 280 may compare the decoded address field with the chip address value of the slave device 210, where the least significant bit of the chip address value comes from the non-transitory storage location 281.

[0038] Once the value of the first address port 213 is stored in the non-transitory storage location 281, the first address port 213 can be reused for a new function. In Figure 2 In the example illustrated in, the first address port 213 may be reused as an open-drain communication signal. The internal control circuit 275 may assert the gate signal 276. The gate signal 276 may turn on the pull-down device 270, and the pull-down device 270 may pull down the voltage on the bus 265. The pull-up resistor 215 may be selected as a resistor with a high resistance value such that the pull-down device 270 can pull the bus 265 to ground and consume a small amount of current. The bus 265 may be input to the input 260 of the master device 250. The master device 250 may respond to the low level on the input 260.

[0039] In Figure 2 In the example illustrated in, the internal control circuit 275, the gate signal 276, and the pull-down device 270 may implement a system alarm function, where the alarm is asserted by the asserted gate signal 276, thereby pulling the bus 265 to ground, and where the alarm is not asserted when the gate signal 276 is not asserted, thereby allowing the pull-up resistor 215 to pull the bus 265 towards the supply voltage. In one example of various examples, the slave device 210 may be a high-power device that may be vulnerable to high-temperature damage when subjected to conditions such as a short circuit or heavy load. In Figure 2 In the example illustrated in, the slave device 210 may include a temperature sensor. A temperature alarm signal may be transmitted from the slave device 210 to the master device 250. The master device 250 may respond by disabling the slave device 210 to prevent damage to the slave device 210. The master device 250 may respond with other actions to prevent damage to the slave device 210.

[0040] The secondary device 210 may include very few external pins, and there may be no pins available for implementing a temperature alert signal. In the example illustrated in Figure 2 , the bus 265 may implement a temperature alert signal. When the temperature of the secondary device 210 exceeds a predetermined threshold, the internal control circuit 275 may receive an input from a temperature sensor (not shown). The gate signal 276 may be asserted, and the pull-down device 270 may pull down the bus 265. The primary device 250 may receive a low voltage signal at input 260 and interpret it as a temperature alert and respond accordingly.

[0041] This temperature alert example is for illustrative purposes and is not intended to limit the present invention. In one example of the various examples, the internal control circuit 275, the gate signal 276, and the pull-down device 270 may signal an overvoltage condition or an undervoltage condition. In one example of the various examples, the internal control circuit 275, the gate signal 276, and the pull-down device 270 may signal that a data converter in the secondary device 210 has completed a conversion and the data is ready to be read by the primary device 250. In one example of the various examples, the internal control circuit 275, the gate signal 276, and the pull-down device 270 may signal that a timer in the secondary device 210 has timed out. As previously described, the internal control circuit 275, the gate signal 276, and the pull-down device 270 may convey any condition on the secondary device 210 via the bus 265.

[0042] Figure 3 An I2C system 300 is illustrated that includes two secondary devices (secondary devices 310, 320 having respective multifunctional address pins). The primary device 350 may include an output clock port 351. The primary device 350 may include a bidirectional data port 352. The primary device 350 may include an input port 360.

[0043] The primary device 350 may be a microcontroller. A microcontroller is a system-on-chip that typically includes a processor, memory, multiple input / output ports, and various peripheral devices. In particular, various peripheral devices may be provided, such as configurable logic units, complementary waveform / output generators, dedicated arithmetic units, numerically controlled oscillators, and programmable switched-mode controllers. The microcontroller may include a host controller that communicates with the peripheral devices via a communication protocol that includes, but is not limited to, I2C. The primary device 350 may include a digital processor having memory and multiple programmable input and output ports. The primary device 350 may be a host device capable of communicating with multiple secondary devices via a shared bus protocol.

[0044] The secondary device 310 may include peripheral devices as described above, including but not limited to sensors, amplifiers, oscillators, battery gauges, data converters, or logic devices. The secondary device 310 may communicate with the primary device 350 using a communication protocol that includes but is not limited to I2C.

[0045] The secondary device 320 may include peripheral devices as described above, including but not limited to sensors, amplifiers, oscillators, battery gauges, data converters, or logic devices. The secondary device 320 may communicate with the primary device 350 using a communication protocol that includes but is not limited to I2C.

[0046] The output clock port 351 may be coupled to at least one secondary device via the shared bus 353. The shared bus 353 may also be referred to as the SCL bus or the shared SCL bus. The bidirectional data port 352 may be coupled to at least one secondary device via the shared bus 354. The shared bus 354 may also be referred to as the SDA bus or the shared SDA bus. In Figure 3 the example illustrated, the system 300 includes two secondary devices 310 and 320, but this is not intended to be limiting. Other examples may include a single secondary device or may include more than two secondary devices.

[0047] The secondary device 310 may include a clock input port 311. The clock input port 311 may be coupled to the shared SCL bus 353. The secondary device 310 may include a bidirectional data port 312. The bidirectional data port 312 may be connected to the shared SDA bus 354. The secondary device 310 may include a first address port 313 and a second address port 314. As an example in various examples, the first address port 313 may be coupled to a power supply voltage through a pull-up resistor 316, and the second address port 314 may be coupled to a ground voltage through a pull-down resistor 315.

[0048] The secondary device 320 may include a clock input port 361. The clock input port 361 may be coupled to the shared SCL bus 353. The secondary device 320 may include a bidirectional data port 362. The bidirectional data port 362 may be coupled to the shared SDA bus 354. The secondary device 320 may include a first address port 323. The first address port 323 may be coupled to a supply voltage through a pull-up resistor 316. The secondary device 320 may include a second address port 317. The second address port 317 may be coupled to a supply voltage through a pull-up resistor 318.

[0049] In operation, in Figure 3In the example illustrated, the master device 350 may send a clock signal on the shared SCL bus 353 and may send a data signal on the shared SDA bus 354. The slave device 310 may receive the transmitted data signal on the bidirectional data port 312. The slave device 310 may receive the transmitted clock signal on the clock input port 311. The slave device 320 may receive the transmitted data signal on the bidirectional data port 362. The slave device 320 may receive the transmitted clock signal on the clock input port 361.

[0050] The slave device 310 may respond to the transmission using a decoded address field that matches the chip address value. The chip address value may include a common address and a variable address. In Figure 3 the example illustrated, the variable address of the chip address value of the slave device 310 may be set by a value stored in the non-transitory memory location 381. In Figure 3 the example illustrated, the variable address of the chip address value of the slave device 320 may be set by a value stored in the non-transitory memory location 391. The variable chip address value may be the least significant bit of the chip address value, and the common chip address value may be the most significant bit of the chip address value.

[0051] During a first transmission from the master device 350, the address decoder circuit 380 may sample the voltage at the first address port 313. The address decoder circuit 380 may store the sampled value of the first address port 313 in the non-transitory storage location 381, including but not limited to a volatile register or latch that stores the value of the first address port 313 as long as the device is receiving a supply voltage. In Figure 3 the example illustrated, the address decoder circuit 380 may store the value of the first address port 313, thereby storing a logic high value into the non-transitory storage location 381.

[0052] During a first transmission from the master device 350, the address decoder circuit 390 may sample the voltage at the first address port 323. The address decoder circuit 390 may store the sampled value of the first address port 323 in the non-transitory storage location 391, including but not limited to a volatile register or latch that stores the value of the first address port 323 as long as the device is receiving a supply voltage. In Figure 3 the example illustrated, the address decoder circuit 390 may store the value of the first address port 323, thereby storing a logic high value into the non-transitory storage location 391.

[0053] The value stored in the non-transitory storage location 381 can be accessed by the address decoder circuit 380 as a variable part of the chip address value (address bit A0) of the slave device 310. The address decoder circuit 380 can compare the decoded address field with the chip address value of the slave device 310, where the least significant bit of the chip address value comes from the non-transitory storage location 381.

[0054] The value stored in the non-transitory storage location 391 can be accessed by the address decoder circuit 390 as a variable part of the chip address value (address bit A0) of the slave device 320. The address decoder circuit 390 can compare the decoded address field with the chip address value of the slave device 320, where the least significant bit of the chip address value comes from the non-transitory storage location 391.

[0055] In the slave device 310, the address decoder circuit 380 can receive inputs from the clock input port 311, the bidirectional data port 312, the first address port 313, and the second address port 314. The address decoder circuit 380 can decode the address field based on the clock input port 311 and the bidirectional data port 312. In Figure 3 the example of, the non-transitory storage location 381 can set the least significant bit of the chip address value of the slave device 310. The voltage at the second address port 314 can set the value of the address bit A1 (the second least significant bit of the chip address of the slave device 310).

[0056] In the slave device 320, the address decoder circuit 390 can receive inputs from the clock input port 361, the bidirectional data port 362, the first address port 323, and the second address port 317. The address decoder circuit 390 can decode the address field based on the signals received at the clock input port 361 and the bidirectional data port 362. In Figure 3 the example of, the non-transitory storage location 391 can set the value of the address bit A0 (the least significant bit of the chip address value of the slave device 320). The voltage at the second address port 317 can set the value of the address bit A1 (the second least significant bit of the chip address value of the slave device 32). 0

[0057] In Figure 3 the example illustrated in, the slave device 310 and the slave device 320 can have different chip address values. In the slave device 310, the address bit A1 can be set to logic low through the pull-down resistor 315, and the address bit A0 can be set to logic high through the value stored in the non-transitory storage location 381. In the slave device 320, the address bit A1 can be set to logic high through the pull-up resistor 318, and the address bit A0 can be set to logic high through the value stored in the non-transitory storage location 391. The slave device 310 and the slave device 320 can be individually addressed by the master device 350 using the address bit A0 and the address bit A1.

[0058] In operation, the address decoder circuit 380 in the slave device 310 can receive inputs from the clock input port 311, the bidirectional data port 312, and the second address port 314 and compare the decoded address field with the chip address value of the slave device 310, where the chip address value of the slave device 310 includes a common address and a variable address, and the variable address includes the address bit A0 set by the non-transitory storage location 381 and the address bit A1 set by the second address port 314. Since the SCL bus 353 and the SDA bus 354 are shared by the slave device 310 and the slave device 320, the address decoder circuit 390 in the slave device 320 can receive inputs at the clock input port 361, the bidirectional data port 362, the first address port 323, and the second address port 317, and can compare the decoded address field with the chip address value of the slave device 320, where the chip address value of the slave device 320 includes a common address and a variable address, and the variable address includes the address bit A0 set by the non-transitory storage location 391 and the address bit A1 set by the second address port 317.

[0059] When making a first transmission from the master device 350, the address decoder circuit 380 in the slave device 310 can store the value of the first address port 313 into the non-transitory storage location 381. In Figure 3 the example illustrated in, the address decoder circuit 380 can store the value of the first address port 313, thereby storing a logic high value of the address bit A0 into the non-transitory storage location 381. When making a first transmission from the master device 350, the address decoder circuit 390 in the slave device 320 can store the value of the first address port 323 into the non-transitory storage location 391. In Figure 3 the example illustrated in, the address decoder circuit 390 can store the value of the first address port 323, thereby storing a logic high value of the address bit A0 into the non-transitory storage location 391. The first transmission from the master device 350 can be initiated based on a first change in the level of the SCL bus 353 or the SDA bus 354.

[0060] The address decoder circuit 380 in the slave device 310 can use the value of the address bit A0 from the non-transitory storage location 381 and the value of the address bit A1 from the second address port 314 to compare the decoded address field with the chip address value of the slave device 310. The address decoder circuit 390 in the slave device 320 can use the value of the address bit A0 from the non-transitory storage location 391 and the value of the address bit A1 from the second address port 317 to compare the decoded address field with the chip address value of the slave device 320.

[0061] Once the value of address bit A0 has been stored in the non-transitory storage location 381 in the slave device 310, the first address port 313 in the slave device 310 can be reused for a new function. In Figure 3 In the example illustrated in Figure 3 , the internal control circuit 375 can assert the gate signal 376. The gate signal 376 can turn on the pull-down device 370, and the pull-down device 370 can pull down the voltage on the bus 365. The pull-up resistor 316 can be selected as a resistor with a high resistance value such that the pull-down device 370 can pull the bus 365 to ground. The bus 365 can be coupled to the input 360 of the master device 350.

[0062] Once the value of address bit A0 has been stored in the non-transitory storage location 391 in the slave device 320, the first address port 323 in the slave device 320 can be reused for a new function. In Figure 3 In the example illustrated in Figure 3 , the internal control circuit 395 can assert the gate signal 396. The gate signal 396 can turn on the pull-down device 397, and the pull-down device 397 can pull down the voltage on the bus 365. As pointed out above, the pull-up resistor 316 can be selected as a resistor with a high resistance value such that the pull-down device 397 can pull the bus 365 to ground. The bus 365 can be input to the input 360 of the master device 350.

[0063] In Figure 3 In the example illustrated in Figure 3 , the internal control circuit 375, the gate signal 376, and the pull-down device 370 can implement an open-drain communication signal from the slave device 310 to the master device 350. In other examples, the slave device 310 can communicate with other devices (not shown) coupled to the bus 365. The internal control circuit 395, the gate signal 396, and the pull-down device 397 can implement an open-drain communication signal from the slave device 320 to the master device 350. Since the logic high level on the bus 365 is set by the pull-up resistor 316, multiple slave devices with internal pull-down devices can share the bus 365 and communicate with the master device 350 separately.

[0064] In one example of various examples, the slave device 310 can be a high-power device that may be vulnerable to high-temperature damage when subjected to conditions such as short circuits or heavy loads. In this example, the slave device 310 can include a temperature sensor. A temperature alarm signal can be transmitted from the slave device 310 to the master device 350. The master device 350 can respond by disabling the slave device 310 to prevent damage to the slave device 310.

[0065] The slave device 310 can include very few external pins, and there may be no pins available for implementing the temperature alarm signal. In Figure 3In the example illustrated, bus 365 can implement the transmission of a temperature alert signal. When the temperature of slave device 310 exceeds a pre-determined threshold, the internal control circuit 375 can receive an input from a temperature sensor (not shown). The gate signal 376 can be asserted, and the pull-down device 370 can pull down bus 365. The master device 350 can receive a low voltage signal at input 360 and interpret it as a temperature alert and respond accordingly.

[0066] In one example of the various examples, slave device 320 can be a high-power device that may be vulnerable to high-temperature damage when subjected to conditions such as short circuits or heavy loads. In this example, slave device 320 can include a temperature sensor. A temperature alert signal can be transmitted from slave device 320 to master device 350. The master device 350 can respond by disabling the slave device 320 to prevent damage to the slave device 320.

[0067] Slave device 320 can include very few external pins, and there may be no pins available for implementing a temperature alert signal. In Figure 3 the example illustrated, bus 365 can implement the transmission of a temperature alert signal. When the temperature of slave device 320 exceeds a pre-determined threshold, the internal control circuit 395 can receive an input from a temperature sensor (not shown). The gate signal 396 can be asserted, and the pull-down device 397 can pull down bus 365. The master device 350 can receive a low voltage signal at input 360 and interpret it as a temperature alert and respond accordingly.

[0068] In Figure 3 the example illustrated, both slave device 310 and slave device 320 can pull down bus 365 and transmit a system alert signal to master device 350. The master device 350 can transmit further transactions on SCL bus 353 and SCL bus 354 to determine which device issued the system alert and to determine the exact type of condition that caused the system alert.

[0069] This temperature alert example is for illustrative purposes and is not intended to limit the invention. Any other signal can be transmitted over bus 365, including but not limited to system alert signals.

[0070] In one example of the various examples, the internal control circuit 375, gate signal 376, and pull-down device 370 can signal an overvoltage condition or an undervoltage condition. In one example of the various examples, the internal control circuit 375, gate signal 376, and pull-down device 370 can signal that a data converter in slave device 310 has completed a conversion. In one example of the various examples, the internal control circuit 375, gate signal 376, and pull-down device 370 can signal that a timer in slave device 310 has timed out.

[0071] In one example of the various examples, the internal control circuit 395, the gate signal 396, and the pull-down device 397 may signal that the data converter in the secondary device 320 has completed conversion. In one example of the various examples, the internal control circuit 395, the gate signal 396, and the pull-down device 397 may signal that the timer in the secondary device 320 has timed out.

[0072] Figure 3 The specific examples illustrated are for purposes of explanation and are not intended to limit the present invention. Any other signals may be transmitted over the bus 365, including but not limited to system alert signals.

[0073] Figure 4 An I2C system 400 including two secondary devices is illustrated, the two secondary devices having corresponding multifunctional address pins. Figure 4 The examples illustrated do not require external resistors to independently address the secondary devices 410 and 420.

[0074] The master device 450 may include an output clock port 451. The master device 450 may include a bidirectional data port 452. The master device 450 may include a first bidirectional port 458 and a second bidirectional port 448.

[0075] The master device 450 may be a microcontroller. A microcontroller is a system-on-chip that typically includes a processor, a memory, multiple input / output ports, and various peripheral devices. In particular, various peripheral devices may be provided, such as configurable logic units, complementary waveform / output generators, dedicated arithmetic units, numerically controlled oscillators, and programmable switched-mode controllers. The microcontroller may include a host controller that communicates with the peripheral devices via a communication protocol including but not limited to I2C. The master device 450 may include a digital processor having a memory and multiple programmable input and output ports. The master device 450 may be a host device capable of communicating with multiple secondary devices via a shared bus protocol.

[0076] The secondary device 410 may include the peripheral devices as described above, including but not limited to sensors, amplifiers, oscillators, battery gauges, data converters, or logic devices. The secondary device 410 may communicate with the master device 450 using a communication protocol including but not limited to I2C.

[0077] The secondary device 420 may include the peripheral devices as described above, including but not limited to sensors, amplifiers, oscillators, battery gauges, data converters, or logic devices. The secondary device 420 may communicate with the master device 450 using a communication protocol including but not limited to I2C.

[0078] The master device 450 may include a first bidirectional port circuit 455 coupled to a first bidirectional port 458. The first bidirectional port 458 may be a general-purpose input / output (GPIO) port. The first bidirectional port circuit 455 may include a first output stage 456, which may include circuitry for driving the first bidirectional port 458. The first bidirectional port circuit 455 may include a first input stage 457, which may include a comparator or a receiver or other circuitry for detecting an input voltage on bus 465.

[0079] The master device 450 may include a second bidirectional port circuit 445 coupled to a second bidirectional port 448. The second bidirectional port 448 may be a general-purpose input / output (GPIO) port. The second bidirectional port circuit 445 may include a second output stage 446, which may include circuitry for driving the second bidirectional port 448. The second bidirectional port circuit 445 may include a second input stage 447, which may include a comparator or a receiver or other circuitry for detecting an input voltage on bus 466.

[0080] The output clock port 451 may be coupled to at least one slave device via a shared bus 453. The shared bus 453 may also be referred to as an SCL bus or a shared SCL bus. The bidirectional data port 452 may be coupled to at least one slave device via a shared bus 454. The shared bus 454 may also be referred to as an SDA bus or a shared SDA bus. In the example illustrated in Figure 4 system 400 includes two slave devices 410 and 420, but this is not intended to be limiting. Other examples may include a single slave device or may include more than two slave devices.

[0081] The slave device 410 may include a clock input port 411. The clock input port 411 may be coupled to the shared SCL bus 453. The slave device 410 may include a bidirectional data port 412. The bidirectional data port 412 may be coupled to the shared SDA bus 454. The slave device 410 may include a first address port 413 coupled to bus 465. Bus 465 may be driven by the first output stage 456 of the first bidirectional port circuit 455 of the master device 450.

[0082] The slave device 420 may include a clock input port 461. The clock input port 461 may be coupled to the shared SCL bus 453. The slave device 420 may include a bidirectional data port 462. The bidirectional data port 462 may be coupled to the shared SDA bus 454. The slave device 420 may include a first address port 423 coupled to bus 466. Bus 466 may be driven by the second output stage 446 of the second bidirectional port circuit 445 of the master device 450.

[0083] In operation, in Figure 4In the example illustrated, the master device 450 may send a clock signal on the shared SCL bus 453 and may send a data signal on the shared SDA bus 454. The slave device 410 may receive the sent data signal on the bidirectional data port 412. The slave device 410 may receive the sent clock signal on the clock input port 411. The slave device 420 may receive the sent data signal on the bidirectional data port 462. The slave device 420 may receive the sent clock signal on the clock input port 461. Initially, the first output stage 456 of the first bidirectional port circuit 458 may be enabled, and the first input stage 457 of the first bidirectional port circuit 455 may be disabled, thereby configuring the first bidirectional port 455 as an output. Initially, the first output stage 446 of the first bidirectional port circuit 445 may be enabled, and the first input stage 447 of the first bidirectional port circuit 455 may be disabled, thereby configuring the first bidirectional port 448 as an output.

[0084] The address decoder circuit 480 may receive inputs from the clock input port 411, the bidirectional data port 412, and the first address port 413. The address decoder circuit 480 may decode an address field based on the signals received at the clock input port 411 and the bidirectional data port 412. In Figure 4 the example, the non-transitory storage location 381 may set the value of the address bit A0 (the least significant bit of the chip address value of the slave device 410) based on the voltage value at the first address port 413.

[0085] The address decoder circuit 490 may receive inputs from the clock input port 461, the bidirectional data port 462, and the first address port 423. The address decoder circuit 490 may decode an address field based on the signals received at the clock input port 461 and the bidirectional data port 462. In Figure 4 the example, the non-transitory storage location 391 may set the value of the address bit A0 (the least significant bit of the chip address value of the slave device 420) based on the voltage value at the first address port 423.

[0086] In operation, the address decoder circuit 480 in the slave device 410 may receive inputs from the clock input port 411 and the bidirectional data port 412, and may compare the decoded address field with the chip address value of the slave device 410. Since the SCL bus 453 and the SDA bus 454 are shared by the slave device 410 and the slave device 420, the address decoder circuit 490 in the slave device 420 may receive inputs at the clock input port 461, the bidirectional data port 462, and the first address port 423, and may compare the decoded address field with the chip address value of the slave device 420.

[0087] Upon a first transmission from the master device 450, the address decoder circuit 480 in the slave device 410 may store the value of the address port 413 into the non-transitory storage location 481. In Figure 4 In the example illustrated in Figure 4 , the address decoder circuit 480 may store the value of the address bit A0 into the non-transitory storage location 481 in response to a voltage present at the address port 413. The address decoder circuit 490 in the slave device 420 may store the value of the address bit A0 into the non-transitory storage location 491 in response to a voltage present at the address port 423. The first transmission from the master device 450 may be initiated based on a first change in the level of the SCL bus 453 or the SDA bus 454. The first transmission from the master device 450 may be initiated based on a pre-determined sequence of levels on the SCL bus 453 and the SDA bus 454.

[0088] The address decoder circuit 480 in the slave device 410 may compare the decoded address field with the chip address value of the slave device 410, which includes the value of the address bit A0 from the non-transitory storage location 481. The address decoder circuit 490 in the slave device 420 may compare the decoded address field with the chip address value of the slave device 420, which includes the value of the address bit A0 from the non-transitory storage location 491.

[0089] Once the value of the address bit A0 has been stored in the non-transitory storage location 481 in the slave device 410, the first output stage 456 of the first bidirectional port circuit 455 may be disabled, and the first input stage 457 of the first bidirectional port circuit 455 may be enabled. When no other device is driving the bus 465, the first input stage 457 of the first bidirectional port circuit 455 may be enabled with a weak pull-up device to maintain a logic high level on the bus 465. Once the value of the address bit A0 has been stored in the non-transitory storage location 481 in the slave device 410 and the first output stage 456 has been disabled, the first address port 413 in the slave device 410 may be re-purposed for a new function. Once the value of the address bit A0 has been stored in the non-transitory storage location 491 in the slave device 420 and the second output stage 446 has been disabled, the first address port 423 in the slave device 420 may be re-purposed for a new function.

[0090] Once the value of address bit A0 has been stored in the non-transitory storage location 491 in the slave device 420, the first output stage 446 of the first bidirectional port circuit 445 can be disabled, and the first input stage 447 of the first bidirectional port circuit 445 can be enabled. When no other device is driving the bus 466, the first input stage 447 of the first bidirectional port circuit 445 can be enabled with a weak pull-up device to maintain a logic high level on the bus 466. Once the value of address bit A0 has been stored in the non-transitory storage location 491 in the slave device 420 and the first output stage 446 has been disabled, the first address port 423 in the slave device 420 can be repurposed for a new function.

[0091] In Figure 4 the example illustrated in, the internal control circuit 475, the gate signal 476, and the pull-down device 470 can communicate with the master device 450 via the bus 465. In Figure 4 the example illustrated in, the internal control circuit 495, the gate signal 496, and the pull-down device 467 can communicate with the master device 450 via the bus 466.

[0092] In Figure 4 the example illustrated in, the internal control circuit 475 can assert the gate signal 476. The gate signal 476 can turn on the pull-down device 470, and the pull-down device 470 can pull down the voltage on the bus 465. The pull-up device in the input stage 457 of the bidirectional port circuit 455 can be selected as a resistor with a high resistance value such that the pull-down device 470 can pull the bus 465 to ground. The bus 465 can be received by the input stage 457 of the bidirectional port 455 of the master device 450. In this way, the communication signal can be transmitted from the slave device 410 to the master device 450.

[0093] In Figure 4 the example illustrated in, the internal control circuit 495 can assert the gate signal 496. The gate signal 496 can turn on the pull-down device 467, and the pull-down device 467 can pull down the voltage on the bus 466. The pull-up device in the second input stage 447 of the second bidirectional port circuit 445 can be selected as a resistor with a high resistance value such that the pull-down device 467 can pull the bus 466 to ground. The bus 466 can be received by the second input stage 447 of the second bidirectional port circuit 445 of the master device 450. In this way, the communication signal can be transmitted from the slave device 420 to the master device 450. The bus 465 and the bus 466 can be replaced with direct wire connections respectively without going out of scope.

[0094] In one example among various examples, the secondary device 410 can be a high-power device that may be vulnerable to high-temperature damage when subjected to conditions such as short circuits or heavy loads. In this example, the secondary device 410 can include a temperature sensor. A temperature alarm signal can be transmitted from the secondary device 410 to the primary device 450. The primary device 450 can respond by disabling the secondary device 410 to prevent damage to the secondary device 410.

[0095] The secondary device 410 can include few external pins, and there may be no pins available for implementing the temperature alarm signal. In Figure 4 the example illustrated in, the bus 465 can implement the transmission of the temperature alarm signal. When the temperature of the secondary device 410 exceeds a predetermined threshold, the internal control circuit 475 can receive an input from a temperature sensor (not shown). The gate signal 476 can be asserted, and the pull-down device 470 can pull down the bus 465. The primary device 450 can receive a low-voltage signal at the first input stage 457 of the first bidirectional port circuit 455 and interpret it as a temperature alarm and respond accordingly.

[0096] In one example among various examples, the secondary device 420 can be a high-power device that may be vulnerable to high-temperature damage when subjected to conditions such as short circuits or heavy loads. In this example, the secondary device 420 can include a temperature sensor. A temperature alarm signal can be transmitted from the secondary device 420 to the primary device 450. The primary device 450 can respond by disabling the secondary device 420 to prevent damage to the secondary device 420.

[0097] The secondary device 420 can include few external pins, and there may be no pins available for implementing the temperature alarm signal. In Figure 4 the example illustrated in, the bus 466 can implement the transmission of the temperature alarm signal. When the temperature of the secondary device 420 exceeds a predetermined threshold, the internal control circuit 495 can receive an input from a temperature sensor (not shown). The gate signal 496 can be asserted, and the pull-down device 467 can pull down the bus 466. The primary device 450 can receive a low-voltage signal at the second input stage 447 of the second bidirectional input circuit 445 and interpret it as a temperature alarm and respond accordingly.

[0098] This temperature alarm example is for illustrative purposes and is not intended to limit the present invention. Any other signal can be transmitted through the bus 465, including but not limited to system alarm signals. Any other signal can be transmitted through the bus 466, including but not limited to system alarm signals.

[0099] Figure 5 A method of configuring and using multifunctional address pins is illustrated.

[0100] At operation 510, the auxiliary device may receive a first data transmission.

[0101] At operation 520, the auxiliary device may store the values on one or more address pins into a non-transitory storage medium. The stored values may reflect the logic levels on the one or more address pins.

[0102] At operation 530, the auxiliary device may apply the stored address values to the chip address value of the auxiliary device. The chip address value may be compared with the decoded address field received from the master device during a subsequent data transmission.

[0103] At operation 540, the auxiliary device may pull down the voltage on one or more address pins to signal the master device or any other device coupled to the one or more address pins. The auxiliary device may signal the master device of a system alert, a fault event, or other event.

Claims

1. A device, comprising: Clock input port; Bidirectional data port; Address port; an address decoder circuit communicatively coupled to the clock input port, the bidirectional data port, and the address port, the address decoder circuit for receiving a clock signal from the clock input port and for receiving a data signal from the bidirectional data port, and for decoding the clock signal and the data signal to generate a decoded address field, and the address decoder circuit for storing a value of the address port in a non-transitory storage location and for comparing at least one bit of the decoded address field to the stored value of the address port; as well as An internal control circuit is used to output a control signal to a pull-down circuit based on a predetermined condition, and the pull-down circuit is used to selectively couple the address port to a ground node based on a value of the control signal.

2. The apparatus of claim 1 , the pull-down circuit comprising a metal oxide semiconductor (MOS) device having a gate node coupled to the control signal, a source node coupled to a ground connection, and a drain node coupled to the address port.

3. The apparatus of any one of claims 1 to 2, the clock signal comprising an I2CSCL clock signal.

4. The apparatus according to any one of claims 1 to 3, the data signal comprising an I2C SDA data signal.

5. The apparatus of any one of claims 1 to 4, the predetermined condition comprising a system alarm.

6. The apparatus of any one of claims 1 to 5, the predetermined condition comprising a thermal limit.

7. A system, comprising: a master device for driving a clock bus and a data bus and for coupling to a control bus; A plurality of auxiliary devices, wherein the plurality of auxiliary devices include: a clock input port, the clock input port being used to couple to the clock bus; a bidirectional data port for coupling to the data bus; an address port, the address port being configured to be coupled to the control bus; an address decoder circuit coupled to the clock input port, the bidirectional data port and the address port, the address decoder circuit for receiving a clock signal from the clock input port and for receiving a data signal from the bidirectional data port, and for decoding the clock signal and the data signal to generate a decoded address field, and the address decoder circuit for storing a value of the address port in a non-transitory storage location and for comparing at least one bit of the decoded address field with the stored value of the address port; and An internal control circuit is used to output a control signal to a pull-down circuit based on a predetermined condition, and the pull-down circuit is used to selectively couple the address port to a ground node based on a value of the control signal.

8. The system of claim 7, the pull-down circuit comprising a metal oxide semiconductor (MOS) device having a gate node coupled to the control signal, a source node coupled to a ground connection, and a drain node coupled to the address port.

9. The system of any one of claims 7 to 8, the clock signal comprising an I2CSCL clock signal.

10. The system of any one of claims 7 to 9, the data signal comprising an I2CSDA data signal.

11. The system of any one of claims 7 to 10, the predetermined condition comprising a system alarm.

12. The system of any one of claims 7 to 11, the predetermined condition comprising a thermal limit.

13. A method comprising: receiving, at the slave device, data transmission from the master device; storing the value of the address port to a stored address location in a non-transitory storage device; decoding the data transmission to generate a decoded address field; comparing at least one bit of the decoded address field to a stored address port value; as well as The voltage of the address port is pulled down based on a predetermined condition of the slave device to signal a status condition to the master device. The method of claim 13 , wherein the predetermined condition comprises a system alarm.

15. The method of any one of claims 13 to 14, the predetermined condition comprising a thermal limit.

16. The method according to any one of claims 13 to 15, wherein the data transmission comprises an I2C write transmission.

17. The method according to any one of claims 13 to 16, wherein the data transmission comprises an I2C read transmission.

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