On-chip storage multiplexing method

Abstract

The present invention proposes an on-chip storage multiplexing method, comprising: a universal bus control interface, a universal bus control decoder and a protocol converter, a tightly coupled control interface, a tightly coupled control interface address decoder, an SRAM control right hardware allocation module, and a control selector corresponding to each SRAM unit; wherein, an external master device accesses the SRAM unit through the universal bus control interface; when the universal bus initiates an access request, the universal bus control decoder and the protocol converter select the corresponding SRAM unit, convert the access request into an access timing of the SRAM unit, and initiate a read / write request to the corresponding control selector; an external dedicated device directly accesses the SRAM unit through the tightly coupled control interface; the tightly coupled control interface address decoder performs decoding and selects the corresponding SRAM unit; the SRAM control right hardware allocation module allocates the SRAM unit; and the control selector corresponding to the SRAM unit selects access from the universal bus control interface and from the tightly coupled control interface.

Description

Technical Field

[0001] The present invention relates to a storage multiplexing method, in particular to an on-chip storage multiplexing method. Background Art

[0002] In a typical SoC (System on Chip) system, on-chip SRAM (Static Random-Access Memory, SRAM) is typically integrated into the SoC system via an SRAM controller with a bus interface. This approach is relatively simple to use and allows multiple external devices to access the SRAM alternately, but it sacrifices SRAM performance to a certain extent. When an external device wants to access SRAM storage, it must go through the delay of the bus matrix and controller before it can finally access the contents of the SRAM. However, in some cases, on-chip storage is divided into multiple areas, and different areas are used as dedicated storage space for certain external devices. In this way, the access delay caused by the bus can significantly reduce performance.

[0003] Existing SRAM controllers with only a single bus interface can introduce unnecessary latency in certain scenarios. For example, in certain scenarios, a specific area of ​​SRAM is dedicated to a specific module (for example, storing CPU instructions). This results in unnecessary performance loss due to the arbitration required for access on the bus matrix and the potential latency associated with multi-level bus access. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide an on-chip storage multiplexing method in view of the shortcomings of the existing technology.

[0005] In order to solve the above technical problems, the present invention discloses an on-chip storage multiplexing method, comprising: a universal bus control interface, a universal bus control decoder and a protocol converter, a tightly coupled control interface, a tightly coupled control interface address decoder, an SRAM control right hardware allocation module, and a control selector corresponding to each SRAM unit;

[0006] Among them, the external master device accesses the SRAM unit through the universal bus control interface;

[0007] When the universal bus initiates an access request, the universal bus control decoder and protocol converter select the corresponding SRAM unit, convert the access request into the access timing of the SRAM unit, and initiate a read and write request to the control selector corresponding to the corresponding SRAM unit;

[0008] External dedicated devices directly access the SRAM cells through a tightly coupled control interface;

[0009] The tightly coupled control interface address decoder decodes the tightly coupled control interface address and selects the corresponding SRAM unit according to a preset scheme;

[0010] The SRAM control right hardware allocation module allocates the SRAM unit;

[0011] The control selector corresponding to the SRAM unit selects access from the general bus control interface and from the tightly coupled control interface.

[0012] The method for the external dedicated device to directly access the SRAM unit through the tightly coupled control interface includes:

[0013] The tightly coupled control interface timing is the same as the read and write control timing of the SRAM unit. The tightly coupled control interface is directly sent to the corresponding SRAM control selector through the timing and initiates an access request; the tightly coupled control interface is connected to the SRAM tightly coupled control interface in the external device. When the SRAM unit is exclusively used by the external device, the SRAM unit is directly accessed through the tightly coupled control interface.

[0014] After the tightly coupled control interface address decoder selects the corresponding SRAM unit, the access issued by the tightly coupled control interface is sent to the control selector corresponding to the corresponding SRAM unit according to the decoding result, and a read / write request is initiated to the corresponding SRAM unit.

[0015] The number of control selectors corresponding to the SRAM unit is consistent with the number of the SRAM unit, that is, each SRAM unit corresponds to one control selector.

[0016] When the control selector corresponding to the SRAM unit selects access from the universal bus control interface and from the tightly coupled control interface, when the control selector corresponding to the SRAM unit is configured to select one of the above interfaces, the SRAM unit is allowed to be accessed by the selected interface, and when accessed by other interfaces, it is read as 0 and writes are ignored.

[0017] When allocating the SRAM control right hardware allocation module to the SRAM units, the SRAM units are divided according to the application scenarios of the entire system.

[0018] The specific method of allocating the SRAM control right hardware allocation module to the SRAM unit is as follows:

[0019] According to the pre-set sizes of each area, the sizes of the said areas are accumulated in sequence to obtain a first group of node numbers; according to the sizes of each SRAM unit, the sizes are accumulated in sequence to obtain a second group of node numbers, and the two groups of node numbers are compared to obtain a comparison result, which is decoded into the allocation of control rights of the SRAM unit.

[0020] The control selector corresponding to the SRAM unit is configured in two modes:

[0021] For a dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a tightly coupled interface usage mode; for a non-dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a universal bus interface usage mode.

[0022] The universal bus control interface is integrated into the system bus interface of the chip.

[0023] The number of tightly coupled control interfaces is preset according to the specific implementation.

[0024] Beneficial effects:

[0025] 1. The present invention enables on-chip SRAM storage to select different control interfaces according to different usage scenarios, thereby achieving a balance between ease of use and performance.

[0026] 2. When the SRAM control selector is configured as the tightly coupled control interface access mode, the SRAM access efficiency reaches the highest.

[0027] 3. The control rights allocation of SRAM can be automatically completed by hardware according to the pre-set space division. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0029] Figure 1 Schematic diagram of the hardware allocation process for SRAM control rights.

[0030] Figure 2 A schematic diagram showing the relationship between each node in the storage allocation area and each point in the storage unit size section.

[0031] Figure 3 Schematic diagram for node comparison and decoding. DETAILED DESCRIPTION

[0032] An on-chip storage multiplexing method includes: a universal bus control interface, a universal bus control decoder and a protocol converter, a tightly coupled control interface, a tightly coupled control interface address decoder, an SRAM control right hardware allocation module, and a control selector corresponding to each SRAM unit;

[0033] The external host device accesses the SRAM unit through the universal bus control interface; the number of control selectors corresponding to the SRAM unit is consistent with the number of the SRAM unit, that is, each SRAM unit corresponds to one control selector.

[0034] When the universal bus initiates an access request, the universal bus control decoder and protocol converter select the corresponding SRAM unit, convert the access request into the access timing of the SRAM unit, and initiate a read and write request to the control selector corresponding to the corresponding SRAM unit;

[0035] External dedicated devices directly access the SRAM cells through a tightly coupled control interface. The methods include:

[0036] The tightly coupled control interface timing is the same as the read and write control timing of the SRAM unit. The tightly coupled control interface is directly sent to the corresponding SRAM control selector through the timing and initiates an access request; the tightly coupled control interface is connected to the SRAM tightly coupled control interface in the external device. When the SRAM unit is exclusively used by the external device, the SRAM unit is directly accessed through the tightly coupled control interface.

[0037] The tightly coupled control interface address decoder decodes the tightly coupled control interface address and selects the corresponding SRAM unit according to a preset scheme; after the tightly coupled control interface address decoder selects the corresponding SRAM unit, the access issued by the tightly coupled control interface is sent to the control selector corresponding to the corresponding SRAM unit according to the decoding result, and a read / write request is initiated to the corresponding SRAM unit.

[0038] The SRAM control right hardware allocation module allocates SRAM units; when allocating SRAM units, the SRAM control right hardware allocation module divides the SRAM units according to the application scenarios of the entire system. The specific method is:

[0039] According to the pre-set sizes of each area, the sizes of the said areas are accumulated in sequence to obtain a first group of node numbers; according to the sizes of each SRAM unit, the sizes are accumulated in sequence to obtain a second group of node numbers, and the two groups of node numbers are compared to obtain a comparison result, which is decoded into the allocation of control rights of the SRAM unit.

[0040] The control selector corresponding to the SRAM unit selects access from the universal bus control interface and from the tightly coupled control interface. When the control selector corresponding to the SRAM unit is configured to select one of the above interfaces, the SRAM unit is allowed to be accessed by the selected interface. When accessed by other interfaces, it is read as 0 and writes are ignored.

[0041] The control selector corresponding to the SRAM unit is configured in two modes:

[0042] For a dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a tightly coupled interface usage mode; for a non-dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a universal bus interface usage mode.

[0043] The universal bus control interface is integrated into the system bus interface of the chip.

[0044] The number of tightly coupled control interfaces is preset according to the specific implementation.

[0045] Example:

[0046] like Figure 1 As shown, the present invention can be divided into a universal bus control interface, a universal bus control decoder and protocol converter, a tightly coupled control interface, n tightly coupled control interface address decoders, a hardware allocation module, and a control selector corresponding to each SRAM unit. The control selector can be 2-to-1, 4-to-1, ..., 2N, where N is a positive integer.

[0047] i) Universal bus control interface. The universal bus control interface is a common universal bus protocol interface, such as AXI, AHB, or APB. This interface is integrated into the system bus interface, and external master devices can access the SRAM unit through this interface.

[0048] ii) Universal bus control interface address decoder and protocol converter. When a universal bus access request is initiated, the address decoder first selects the corresponding SRAM cell. A protocol converter module then converts the address decoded address into an SRAM interface access sequence. This sequence selects the corresponding SRAM cell based on the address decoded result and initiates a read or write request to the corresponding control selector.

[0049] iii) Tightly coupled control interface. The timing of the tightly coupled control interface is almost identical to the read and write control timing of the SRAM cell. This access timing can be directly transmitted to the corresponding SRAM control selector and initiate an access request. This interface is connected to the SRAM tightly coupled control interface of the external device. When certain SRAM is exclusively used by the device, the device can directly access the SRAM contents through this tightly coupled interface. The number of tightly coupled control interfaces can vary depending on the specific implementation.

[0050] iv) Tightly Coupled Control Interface Address Decoder. This address decoder decodes the address in the TCI and selects the corresponding SRAM cell according to a predefined address allocation scheme. Access requests from the TCI are then sent to the control selector of the corresponding SRAM cell based on the decoded result, initiating read and write requests to the corresponding SRAM cell.

[0051] v) SRAM control selector. Each SRAM cell has a control selector that selects between access from the general bus control interface and the tightly coupled control interface. When the selector is configured to select one of the interfaces, the SRAM cell can only be accessed by that interface; accesses from other interfaces will result in a read-0 and write-ignore effect.

[0052] vi) SRAM control rights hardware allocation module. When using this module, you should first analyze the application scenario of the current system and divide the SRAM units. Here, the SRAM control rights hardware allocation module performs calculations and allocations. The allocation process is as follows: Figure 1 shown.

[0053] Assume that the module implements a universal bus interface, the address space it needs to access is size0: 128K, and the three tightly coupled control interfaces need to access address spaces of size1: 64K, size2: 64K, and size3: 256K. Adding up these sizes in sequence, we get four sizes: 128, 192, 256, and 512 (e.g., 128=128, 192=128+64, 256=192+64, 512=256+256). At the same time, we have 8 controlled SRAM units, unit0-7, each of which is 64K in size. Adding them in sequence and subtracting 1 from the result, we get 63, 127, 191, 255, 319, 383, 447, and 511. These numbers are called storage size node numbers, such as Figure 2 shown.

[0054] like Figure 3 In the comparison module shown, the sizes of the four regions serve as four inputs and are connected to three adders as shown. Specifically, size0 and size1 are connected to the inputs of adder sum0, the output of sum0 and size2 are connected to the input of adder sum1, and the output of sum1 and size3 are connected to the input of sum2. The three size numbers 128, 192, and 256 are connected to the A terminals of the three comparators compare, and the storage size node numbers are simultaneously connected to the B terminals of the three comparators compare. This generates eight sets of comparison results for res0, res1, and res2. A result of 1 indicates that the B terminal of the comparator is greater than or equal to the A terminal, while a result of 0 indicates that the A terminal of the comparator is less than the B terminal. This result is passed through a decoder to obtain the configuration results of each SRAM cell. The comparison module and decoder decoding method are as follows.

[0055]

[0056] As shown in the table, the decoder allocation result will be connected to the control selector corresponding to the SRAM unit and the corresponding control interface will be selected.

[0057] For SRAM cells that need to be dedicated, the data selection corresponding to the SRAM cell should be configured to the tightly coupled interface usage mode. For those SRAM cells that do not need to be dedicated to external devices, the control corresponding to the SRAM cell should be configured to the universal bus interface usage mode. After this configuration, each bus interface can only access the SRAM cell to which it is assigned. When accessing the address corresponding to the unassigned SRAM cell, only a read 0 and write ignore effect will be generated. In this way, for those SRAM interfaces assigned to dedicated devices, the bus access delay can be eliminated, thereby greatly improving the efficiency of SRAM access.

[0058] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium is capable of storing a computer program that, when executed by the data processing unit, can execute the invention content of an on-chip storage multiplexing method provided by the present invention and some or all of the steps in each embodiment. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0059] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a computer program, i.e., a software product. The computer program software product can be stored in a storage medium and includes a number of instructions for enabling a device including a data processing unit (which can be a personal computer, server, single-chip microcomputer, MUU or network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0060] The present invention provides a concept and method for on-chip storage multiplexing. There are numerous methods and approaches for implementing this technical solution. The above is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. An on-chip storage multiplexing method, characterized in that: include: Universal bus control interface, universal bus control decoder and protocol converter, tightly coupled control interface, tightly coupled control interface address decoder, SRAM control right hardware allocation module and control selectors corresponding to each SRAM unit; Among them, the external master device accesses the SRAM unit through the universal bus control interface; When the universal bus initiates an access request, the universal bus control decoder and protocol converter select the corresponding SRAM unit, convert the access request into the access timing of the SRAM unit, and initiate a read and write request to the control selector corresponding to the corresponding SRAM unit; External dedicated devices directly access the SRAM cells through a tightly coupled control interface; The tightly coupled control interface address decoder decodes the tightly coupled control interface address and selects the corresponding SRAM unit according to a preset scheme; The SRAM control right hardware allocation module allocates the SRAM unit; The control selector corresponding to the SRAM unit selects access from the general bus control interface and from the tightly coupled control interface; The specific method of allocating the SRAM control right hardware allocation module to the SRAM unit is as follows: According to the sizes of the pre-set regions, the sizes of the regions are sequentially accumulated to obtain a first set of node numbers; according to the sizes of the SRAM cells, the sizes are sequentially accumulated to obtain a second set of node numbers; the two sets of node numbers are compared to obtain a comparison result, and the comparison result is decoded into an allocation of control rights of the SRAM cells; The control selector corresponding to the SRAM unit is configured in two modes: For a dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a tightly coupled interface usage mode; for a non-dedicated SRAM cell, the control selector corresponding to the SRAM cell is configured to a universal bus interface usage mode; The number of control selectors corresponding to the SRAM unit is consistent with the number of the SRAM unit, that is, each SRAM unit corresponds to one control selector.

2. The on-chip storage multiplexing method according to claim 1, characterized in that: The method for the external dedicated device to directly access the SRAM unit through the tightly coupled control interface includes: The tightly coupled control interface timing is the same as the read and write control timing of the SRAM unit. The tightly coupled control interface is directly sent to the corresponding SRAM control selector through the timing and initiates an access request; the tightly coupled control interface is connected to the SRAM tightly coupled control interface in the external device. When the SRAM unit is exclusively used by the external device, the SRAM unit is directly accessed through the tightly coupled control interface.

3. The on-chip storage multiplexing method according to claim 2, characterized in that: After the tightly coupled control interface address decoder selects the corresponding SRAM unit, the access issued by the tightly coupled control interface is sent to the control selector corresponding to the corresponding SRAM unit according to the decoding result, and a read / write request is initiated to the corresponding SRAM unit.

4. The on-chip storage multiplexing method according to claim 3, characterized in that: When the control selector corresponding to the SRAM unit selects access from the universal bus control interface and from the tightly coupled control interface, when the control selector corresponding to the SRAM unit is configured to select one of the above interfaces, the SRAM unit is allowed to be accessed by the selected interface, and when accessed by other interfaces, it is read as 0 and writes are ignored.

5. The on-chip storage multiplexing method according to claim 4, characterized in that: When allocating the SRAM control right hardware allocation module to the SRAM units, the SRAM units are divided according to the application scenarios of the entire system.

6. The on-chip storage multiplexing method according to claim 5, characterized in that: The universal bus control interface is integrated into the system bus interface of the chip.

7. The on-chip storage multiplexing method according to claim 6, characterized in that: The number of tightly coupled control interfaces is preset according to the specific implementation.

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