Phase change memory with supply voltage regulation circuit

Abstract

Embodiments of the present disclosure relate to a phase change memory with a supply voltage regulation circuit. A voltage regulator and a phase change memory are disclosed. In one embodiment, the phase change memory includes: an array of a plurality of phase change memory cells; an address decoder configured to receive an address signal and select a sub-region in the array of the plurality of memory cells, the selected sub-region having a data signal of a given number of bits and a write circuit including a control circuit, the control circuit configured to receive the data signal and determine, for each memory cell in the selected sub-region, whether a corresponding bit of the data signal indicates that the memory cell is to enter a polycrystalline state from an amorphous state; and one or more drive circuits powered by a regulated voltage and configured to apply a set current to the memory cell to be changed from the amorphous state to the polycrystalline state for a first interval.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102019000011523, filed on July 11, 2019, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a circuit for adjusting a supply voltage of a write circuit for a write unit of a phase change memory. Background Art

[0004] Figure 1 A diagram of a phase change memory (PCM) 20 is shown comprising a memory region 200 comprising a plurality of memory cells CELL. For example, the memory cells CELL are often arranged in a plurality of columns and optionally in a plurality of rows.

[0005] Specifically, in a phase change memory, each memory cell CELL is based on an alloy (eg, a chalcogenide alloy such as Ge x Sb y T z The invention relates to the use of a GST alloy (abbreviated as GST alloy), wherein the alloy undergoes appropriate heat treatment and then reversibly transforms from an amorphous state with low electrical conductivity to a polycrystalline state with high electrical conductivity. For example, in this context, U.S. patent application Nos. US 2019 / 096480 A1, US 2019 / 140175 A1, or US 2019 / 140176 A1 may be cited, and the contents of which are hereby incorporated by reference.

[0006] Typically, the memory 20 receives an address signal ADR at an input, wherein the address signal ADR is used to select a given memory sub-region within the memory region 200. The memory 20 also includes one or more input terminals and / or output terminals for exchanging data signals DATA with the memory 20, wherein the data signals DATA may include data to be written DATA_IN and / or data that has been read DATA_OUT.

[0007] For example, address signal ADR may be provided to column decoder 204 (which in turn typically provides bit line signal BL) and row decoder 202 (which in turn typically provides word line signal WL) to select a given memory sub-region in memory region 200. Typically, the selected sub-region has a number of bits that corresponds to the number of bits of data signal DATA (i.e., signals DATA_IN and DATA_OUT).

[0008] Typically, the address signal ADR is not directly provided to the row decoder and the column decoder. Instead, the address signal ADR is typically stored in the address buffer 208. Similarly, the data signal DATA may also be stored in the data buffer 214.

[0009] Specifically, in the example considered, the memory 20 supports read and write operations that can be selected by means of control signals W / R. To this end, the memory region 200 has associated write and read interfaces 206. For example, the interface 206 may include a write circuit 212 (i.e., a so-called "program driver") for writing data DATA_IN into the selected memory sub-region and a read circuit 210 (e.g., a sense amplifier) ​​for reading data DATA_OUT from the selected memory cell CELL.

[0010] For example, with reference to phase change memory, the (considerable) difference in conductivity between the amorphous state and the polycrystalline state allows binary data to be associated with the state of the material of the cell CELL, which data can be easily detected, for example by measuring a parameter indicating the resistance of the material of the cell CELL with the help of the measurement / reading circuit 210.

[0011] Therefore, in order to write information in the memory cell CELL, the write circuit 212 should be able to write / program the state of the memory cell (whether it is an amorphous state or a polycrystalline state).

[0012] Specifically, if Figure 2A As shown, in order to make the memory cell CELL of the phase change memory 20 in the first low conductivity state (hereinafter referred to as the reset state), the write circuit 212 should set the current I cell =I reset applied to the cell for a brief time interval ΔT1, after which the current I cell becomes zero rapidly. Specifically, the current I cell Should be high enough to allow the material of the cell to reach the melting point T melt , causing the cell material to melt. The subsequent rapid cooling makes the material amorphous.

[0013] On the contrary, Figure 2B As shown, in order to make the memory cell CELL change from the first state (reset) to the second high conductivity state (hereinafter referred to as the set state), the write circuit 212 should set the current I cell =I set applied to the cell for a brief time interval ΔT2, where I set Reset , the current is then reduced during the time interval ΔT3 according to a ramp or step. Specifically, the current I cell =I​set Should be sufficient to reach the crystallization temperature T x , where T x <T melt The gradual cooling achieved in this case allows crystals to form and thus leads to conditions of high electrical conductivity.

[0014] Figure 3A 、 Figure 3B and Figure 3C Some examples of implementations of a single memory cell CELL are shown.

[0015] Specifically, as previously described, the cell CELL of the PCM includes a memory element made of GST (eg, chalcogenide alloy), which is connected between a bit line BL and a word line WL.

[0016] For example, in Figure 3A In the embodiment, the GST memory element is connected to a field effect transistor (FET) T1 (e.g., a metal oxide semiconductor field effect transistor (MOSFET), e.g., an n-channel type NMOS transistor) located between a bit line BL and a reference voltage (e.g., ground GND). In addition, a word line WL drives the gate terminal of the transistor T1.

[0017] On the contrary, Figure 3B In the embodiment, the transistor FET has been replaced by a bipolar junction transistor T2.

[0018] Finally, in Figure 3C In FIG. 1 , a diode D is used; that is, a memory element GST is connected between the lines BL and WL.

[0019] Basically, the common point of these examples is that by applying a given voltage to the word line WL, the selector / electronic switch (T1, T2 or D) is turned on, so that the current I cell Power can flow from the selected bit line BL through the memory element GST.

[0020] For example, Figure 4 One implementation of memory 20 is shown.

[0021] In particular, in the example considered, a single memory cell CELL connected between a bit line BLr and a word line WLq is illustrated.

[0022] As mentioned above, the writing circuit 212 should convert the current I cell To this end, the write circuit 212 includes a driver circuit 2126 (ie, one or more program drivers) configured to generate a current I cell , current I cellThe current is applied to the bit line BLr by means of the multiplexer 204. In general, several driver circuits 2126 may be used, each driver circuit 2126 generating a current for a corresponding cell. For example, the number of driver circuits 2126 may be equal to the number of bits of the data signal DATA_IN.

[0023] Specifically, in the example considered, the driver circuit 2126 receives one or more control signals CTRL, which control the current I provided by the driver circuit 2126. cell For example, using a digital control signal, the driver circuit 2126 essentially implements a current digital-to-analog converter (IDAC).

[0024] In the example considered, the control signal CTRL is controlled by the control circuit 2124 according to the (write / read) signal W / R and the corresponding data bit DATA_IN to be written. <n>To provide.

[0025] Specifically, the writing step is usually divided into two sub-steps:

[0026] During the first step, all bits DIN for which a reset of the corresponding cell CELL is to be performed <n>is programmed, which enables the corresponding current I to be provided in the time interval ΔT1 cell =I reset (For example, W / R = "1", and DATA_IN <n>="0"); and

[0027] During the second step, all bits DIN for which the setting of the corresponding cell CELL is to be performed <n>is programmed, which enables the corresponding current I to be provided in the time interval (ΔT2+ΔT3) cell =I set (For example, W / R = "1", and DATA_IN <n>="1").

[0028] Therefore, in effect, two programming operations are performed, wherein only the current I cell Therefore, the control signal CTRL may include a signal DIN indicating a cell to be written. For example, assuming that the signal DATA_IN = "0011", during the first step, the signal DIN may be set to DIN = "1100", and during the second step, the signal DIN may be set to DIN = "0011".

[0029] In general, the two steps can also be reversed, and the first step is only optional when, for example, a write-once memory is implemented. Alternatively, the reset step can also be performed during a separate erase step, which usually occurs in flash memories.

[0030] For example, Figure 5 One embodiment of a driver circuit 2126 is shown. Specifically, in the example considered, the driver circuit 2120 comprises two circuits 2120 and 2122 .

[0031] Specifically, the circuit 2122 provides a signal MAX, which indicates the current I to be provided to the cell. cell The maximum value (for example, the signal MAX and the current I in FIG2 set or current I reset In particular, in the example considered, the circuit 2122 is configured to adjust the gain of the circuit 2122 according to a signal PG_DAC, preferably a digital signal PG_DAC, indicating the gain. <i:0>(ie, having i+1 bits) to generate the signal MAX.

[0032] Instead, circuit 2120 receives:

[0033] - a signal WRITE_EN, which indicates whether a program / write operation is to be performed; that is, the signal WRITE_EN represents an enable signal of the circuit 2120;

[0034] - a signal DIN indicating whether programming is to be performed on the corresponding selected cell (either a set programming operation or a reset programming operation);

[0035] - a signal MAX indicating a maximum value of a current supplied to a cell to be written (ie, indicating whether it is a set programming operation or a reset programming operation); and

[0036] - Signal PART_NUM indicating a falling ramp.

[0037] Specifically, in the example considered, the circuit 2120 makes it possible to use the digital signal PART_CURR <k:0>(ie, with k+1 bits) to specify the falling slope of the set pulse, the digital signal PART_CURR <k:0>It operates by dividing the current indicated by the signal MAX. Therefore, the signal PART_CURR <k:0>This allows you to specify the current I injected into the cell to be written cell Time diagram.

[0038] Therefore, in the embodiment considered, the signals WRITE_EN, DIN, PG_DAC <i:0>and PART_CURR <k:0>express Figure 4 The control signal CTRL.

[0039] For example, circuits 2120 and 2122 may be implemented with one or more current mirrors having appropriate gains.

[0040] Typically, the driver circuit 2126 (particularly the circuit 2120) requires a supply voltage VPL_REG. The value of this voltage typically depends on the circuit structure and the SOA (safe operating area) of the transistors used. If the external supply voltage Vcc supplied to the memory 20 is too high, so that it exceeds the absolute maximum value, then in this case, a voltage regulator 2128 must be used to reduce the voltage Vcc to within safe limits (see, for example, Figure 5 ).

[0041] Figure 6A and Figure 6B What is shown in FIG. 1 is a typical structure of a general closed-loop voltage regulator capable of generating a voltage VPL_REG starting from a voltage Vcc.

[0042] In particular, in the example considered, the regulator comprises a capacitor Ct, wherein the voltage across the capacitor Ct corresponds to the voltage VPL_REG.

[0043] In either case, the capacitor Ct is charged to a given reference voltage via a feedback loop comprising an operational amplifier O1. Specifically, for this purpose, the voltage VPL_REG is detected, for example, by means of a voltage divider comprising two resistors R1 and R2, and the detected voltage is compared with the reference voltage V BGAP For comparison, the reference voltage corresponds, for example, to a bandgap-type voltage.

[0044] Specifically, in Figure 6A In the middle, the voltage V BGAP The voltage applied to the negative terminal of the operational amplifier O1 and detected via the voltage divider R1 / R2 is applied to the positive terminal of the amplifier. Thus, in this case, the output of the amplifier can drive the gate terminal of the p-channel FET M1 connected between the voltage Vcc and the capacitor Ct.

[0045] On the contrary, Figure 6B In the middle, the voltage V BGAP The voltage applied to the positive terminal of the operational amplifier O1 and detected via the voltage divider R1 / R2 is applied to the negative terminal of the amplifier. Thus, in this case, the output of the amplifier can drive the gate terminal of the n-channel FET M2 connected between the voltage Vcc and the capacitor Ct.

[0046] These solutions are characterized by a feedback loop with feedback of the output voltage VPL_REG, which includes the output stage. This inclusion usually requires the use of heavy compensation to achieve sufficient frequency stability margin at the expense of response speed. This leads to poor stability of the output voltage in the event of rapid changes in the load current, a fact that makes these regulators different from the current I required by the PCM during write operations. cell The regulation and pulse supply characteristics are incompatible. Summary of the Invention

[0047] Embodiments provide a phase change memory including an innovative circuit arrangement for regulating a supply voltage of a driving circuit.

[0048] Various other embodiments provide a phase-change memory configured to store a data signal having a given number of bits. In various embodiments, the phase-change memory includes an array of a plurality of phase-change memory cells, wherein the memory cells can be switched from an amorphous state having a low conductivity to a polycrystalline state having a high conductivity by applying a set current for a (first) set interval. In various embodiments, the phase-change memory further includes an address decoder configured to receive an address signal and select a subregion in the array, wherein the selected subregion has the same number of bits as the data signal.

[0049] In various embodiments, a phase change memory includes a write circuit comprising a control circuit and one or more driver circuits. The control circuit is configured to receive a data signal and determine, for each memory cell in a selected subregion, whether a corresponding bit of the data signal indicates that the memory cell is to enter a polycrystalline state from an amorphous state. In various embodiments, the one or more driver circuits are powered via a regulated voltage and are configured to apply a set current to the memory cell to be entered from the amorphous state to the polycrystalline state for a set interval.

[0050] In various embodiments, the phase change memory therefore further comprises a voltage regulator comprising: positive and negative input terminals for receiving a supply voltage; and positive and negative output terminals for providing a regulated voltage to one or more driver circuits.

[0051] Specifically, in various embodiments, a voltage regulator includes: a capacitor connected between a positive output terminal and a negative output terminal, an output stage, and a regulating circuit.

[0052] In various embodiments, the output stage includes a plurality of branches, wherein each branch includes a voltage generator connected between a positive input terminal and a positive output terminal, wherein each voltage generator is configured to generate a variable current according to a drive signal and a regulated voltage, wherein each voltage generator can be selectively activated according to a corresponding enable signal.

[0053] For example, in various embodiments, each voltage generator includes a first field effect transistor and an electronic switch connected in series between a positive input terminal and a positive output terminal, wherein the gate terminal of the first field effect transistor is driven via a corresponding drive signal, and wherein the electronic switch is driven via a corresponding enable signal.

[0054] In various embodiments, the regulation circuit is configured to generate a drive signal for the voltage generator such that the voltage between the positive output terminal and the negative output terminal is regulated to a desired value.

[0055] For example, in various embodiments, a second field-effect transistor and a first current generator are connected in series between a positive input terminal and a negative input terminal, wherein the second field-effect transistor has the same type of channel as the first field-effect transistor. In this case, a voltage divider can provide a voltage proportional to the voltage on the first current generator, and the operational amplifier can generate a drive signal based on the proportional voltage. Specifically, in various embodiments, a first input terminal of the operational amplifier is connected to a reference voltage, a second input terminal of the operational amplifier is connected to a voltage provided by the voltage divider, and an output terminal of the operational amplifier is connected to a gate terminal of the first field-effect transistor and a gate terminal of the second field-effect transistor.

[0056] In various embodiments, the regulation circuit further includes a second current generator and a third field effect transistor connected in series between the positive input terminal and the negative input terminal, wherein the third field effect transistor has a channel of the same type as the first field effect transistor, wherein the second current generator is configured to provide a current corresponding to the current provided by the first current generator, wherein the output terminal of the operational amplifier is connected to the gate terminal of the third field effect transistor, and wherein an intermediate point between the third field effect transistor and the second current generator is connected to the positive output terminal.

[0057] In various embodiments, the control circuit can thus generate an enable signal based on the expected current sink, thereby reducing the response time of the voltage regulator to load changes. For example, the control circuit can determine the number of memory cells to be transitioned from the amorphous state to the polycrystalline state and generate an enable signal based on this number. For example, typically, the number of branches of the output stage corresponds to a predetermined coefficient multiplied by the number of bits of the data signal.

[0058] In this case, the control circuit may generate an enable signal such that a first number of voltage generators are activated during the set interval, wherein the first number is determined based on a predetermined coefficient and the number of memory cells to be changed from the amorphous state to the polycrystalline state. For example, the first number may correspond to the predetermined coefficient multiplied by the number of memory cells to be changed from the amorphous state to the polycrystalline state (where the result is an integer obtained by rounding (e.g., up or down)).

[0059] In various embodiments, the one or more driver circuits are configured to apply a current to a memory cell to be transitioned from an amorphous state to a polycrystalline state, the current being reduced from a set current to zero during a subsequent second interval in accordance with a division signal. In this case, the control circuit may generate an enable signal such that a second variable number of voltage generators is activated during the second interval, where the second variable number is determined by the first number and the division signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, and in which:

[0061] Figure 1 An example of a memory including a plurality of phase change memory cells is shown;

[0062] Figure 2A and Figure 2B An example for performing a reset and a set of a memory cell is shown;

[0063] Figure 3A 、 Figure 3B and Figure 3C An example of a phase change memory cell is shown;

[0064] Figure 4 Shown Figure 1 A first example of a memory write interface;

[0065] Figure 5 Shown Figure 1 A second example of a write interface of a memory, wherein the write interface is powered by means of a voltage regulator;

[0066] Figure 6A and Figure 6B An example of a voltage regulator is shown;

[0067] Figure 7 An embodiment of a write interface of a phase change memory is shown;

[0068] Figure 8 Shown Figure 7 A first embodiment of a driver circuit for a write interface;

[0069] Figure 9A and Figure 9B Shown Figure 7 A second embodiment of a driver circuit for a write interface;

[0070] Figure 10 Shown Figure 7 An embodiment of a voltage regulator for a write interface;

[0071] Figure 11 Shown is an example Figure 7 Signals for operations on the write interface;

[0072] Figure 12 Shown Figure 10 An example of a control signal for a voltage regulator; and

[0073] Figure 13 One embodiment of a system including a memory according to the present disclosure is shown. DETAILED DESCRIPTION

[0074] In the following description, various specific details are provided to provide a deeper understanding of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or illustrated in detail so as not to obscure aspects of the embodiments.

[0075] References to "an embodiment" or "one embodiment" throughout this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in various locations throughout this specification are not necessarily referring to the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0076] The reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0077] Described below Figures 7 to 12 In, referenced Figure 1 6 are denoted by the same reference numerals used previously in these figures. In order to make this detailed description less cumbersome, the description of these elements previously presented will not be repeated hereinafter.

[0078] Figure 7 A first embodiment of a write circuit 212 a of a phase change memory according to this specification is shown.

[0079] Also in this case, the write circuit 212a includes a control circuit 2124a, a voltage regulator 2128a, and a drive circuit 2126a.

[0080] For an overall description of the drive circuit 2126, please refer to Figure 4 and Figure 5 Description.

[0081] For example, Figure 8 Shown with reference Figure 5 A possible embodiment of a consistent driver circuit 2126a is described.

[0082] Specifically, in the embodiment considered, the driver circuit 2126a comprises a circuit configured to provide a current I max The variable current generator 2132, where the current I max The PG_DAC signal can be <i:0>, (at least) with current I set Proportional current and current I reset For example, in Figure 7 In the embodiment considered, the circuit 2128 is implemented using an IDAC with a given resolution. For example, in the embodiment considered, the current generator 2132 includes i+1 current generators I R0 ,...,I Ri , i+1 current generators I R0 ,...,I Ri The PG_DAC signal can be <i:0>And through the corresponding switches S0,...,S i Therefore, the PG_DAC signal can be selected by <i:0>, enabling a given number of current generators I R0 ,...,I Ri To select the current I max Specifically, in various embodiments, each current generator I R0 ,...,I Ri Provide the same current.

[0083] The current I provided by the current generator 2132 max It also traverses the input of a current mirror (e.g., a p-channel FET) (e.g., implemented with FET Q1 (input of the current mirror) and multiple FETs Q2 (outputs of the current mirror)). Thus, each of the transistors Q2 allows the current I max Proportional current I Q2 By, for example, I Q2 =I max .

[0084] In the embodiment considered, each of the transistors Q2 is also connected in series with an electronic switch S3 which enables the switching of the transistors Q2 according to the signal PART_CURR, the signal WRITE_EN and the corresponding bit DIN. <n>to activate the current provided by means of the corresponding transistor Q2. Thus, in the example considered, the current I cell corresponds to the sum of the currents provided by the transistors Q2 enabled by means of the corresponding switches S3.

[0085] For example, in the example considered, the signal PART_CURR <k:0>has k+1 bits and uses a corresponding number of transistors Q20, ..., Q2 k , and corresponding electronic switches S30,...,S3 k For example, in the example considered, each switch S3 0, ...,S3 k Closed when:

[0086] a) Set the signal PART_CURR <k:0>to a given logic level (eg, a high level); and

[0087] b) signal WRITE_EN enables circuit 2126a; and

[0088] c) The corresponding signal DIN indicates that a programming operation (set or reset) is to be performed.

[0089] For example, to this end, Figure 8 Thus, by closing all switches S30, ..., S3 k , current I cell Corresponding to (k+1)I Q2 On the contrary, when all switches S30,...,S3 k When disconnected, the current I cell = zero. Therefore, the signal PART_CURR <k:0>This allows dividing the supplied current in k+1 steps.

[0090] Thus, in the example considered, the variable current generator 2132 and the input of the current mirror (transistor Q1) implement the circuit 2122. Conversely, the output of the current mirror (transistor Q2), the switch S3 and the logic gate 2130 implement the circuit 2120. Finally, the signal MAX corresponds to the current I max .

[0091] Thus, in the embodiment considered, the driver circuit 2126a comprises:

[0092] The first circuit is configured to generate an indication current I according to a first control signal PG_DAC cell a signal MAX of a maximum value of the control signal PG_DAC, wherein the value of the control signal PG_DAC is determined based on whether a set operation or a reset operation is to be performed; and

[0093] The second circuit is configured to generate a current I according to the signal MAX and the second control signal PART_CURR in case the cell is to be programmed, in particular with reference to the set operation. cell , the second control signal PART_CURR may specify a division of the maximum current indicated via the signal MAX.

[0094] Figure 9A and Figure 9B An alternative embodiment of circuit 2126a is shown.

[0095] As previously mentioned, the current generator 2132 may be a DAC that includes a plurality of current generators I that can be selectively enabled. R0 ,...,I Ri , and wherein the current generators provide the same current.

[0096] In the embodiment considered, the above-mentioned current generator I R0 ,...,I Ri This is achieved by:

[0097] Current generator I that provides reference current REF ;as well as

[0098] For example, a current mirror implemented using p-channel FETs includes an input stage / input transistor Q3 and i+1 output stages / output transistors Q40, ..., Q4 i .

[0099] Therefore, in the embodiment, each output transistor Q40, ..., Q4 i having corresponding electronic switches S0, ..., S connected thereto i (e.g., p-channel FETs), where the electronic switches S0, ..., S i It is driven according to the signal PG_DAC.

[0100] Therefore, as already referred to Figure 8 The current generator 2132 provides the current I according to the signal PG_DAC. max This current is then applied again to a current mirror comprising an input transistor Q1 (in circuit 2122) and a plurality of output transistors Q20, ..., Q2 k (In circuit 2120 .) For example, in the embodiment considered, a current mirror with n-channel transistors is used.

[0101] In the embodiment considered, the role of switch S3 has been divided. Specifically, the circuit 2120 includes a switch connected to each output transistor Q20, ..., Q2 k Corresponding electronic switches S40, ..., S4 connected in series k (e.g., n-channel FETs), where electronic switches S40, ..., S4 k are driven according to the signal PART_CURR so that they provide a current I′ divided according to the signal PART_CURR cell In addition, the circuit 2120 includes an electronic switch S5 (eg, a p-channel FET) that can enable the current I'. cell In the embodiment considered, the switch S5 is therefore switched on and off according to the signals WRITE_EN and DIN <n>, for example driven by the output of a NAND gate 2130' which receives the above signal at its input.

[0102] In the embodiment considered, the current I' cell Instead of providing it directly to the cell, another current mirror is used which includes an input transistor Q5 and an output transistor Q6, wherein the input transistor Q5 receives the current I' cell , and the output transistor Q6 provides current I cell For example, in the embodiment considered, a current mirror with p-channel transistors is used, wherein the source terminals of these transistors are connected to the voltage VPL_REG.

[0103] like Figure 7 As shown, the control circuit 2124a not only generates control signals PG_DAC, PART_CURR, DIN, and WRITE_EN for the driver circuit 2126a, but also generates another control signal OUT_STAGE for the voltage regulator 2128a.

[0104] FIG9 illustrates one embodiment of a voltage regulator 2128 a according to the present disclosure.

[0105] Specifically, similar to the reference Figure 6A and Figure 6B In the manner described, circuit 2128a includes:

[0106] a capacitor Ctank, wherein the voltage across the capacitor Ctank corresponds to the voltage VPL_REG;

[0107] a FET NB connected between a supply voltage Vcc and a capacitor Ctank, wherein transistor NB represents a voltage generator in a source follower configuration; and

[0108] A regulation circuit drives the gate terminal of transistor NB for regulating the voltage VPL_REG to a desired value.

[0109] Thus, generally, the voltage regulator 2128a includes a positive input terminal 30a and a negative input terminal 30b (generally representing ground gnd) for receiving an input voltage Vcc. For example, the aforementioned terminals 30a and 30b can be connected to corresponding pads or pins of an integrated circuit including the memory 20. In addition, the voltage regulator 2128a includes a positive output terminal 32a and a negative output terminal 32b for providing an output voltage VPL_REG, wherein the negative output terminal 32b is connected (e.g., directly) to the negative input terminal 30b (e.g., ground gnd).

[0110] In the embodiment considered, capacitor Ctank is therefore connected (for example directly) between terminals 32a and 32b. Furthermore, terminal 32a is connected to terminal 30a (ie to voltage Vcc) via transistor NB.

[0111] As mentioned above, the voltage regulator 2128a should be based on the current I cell In this context, the inventors have noticed that the response of the voltage regulator 2128a can be improved when the transistor NB provides a current comparable to the current sunk by the driver circuit 2126a.

[0112] Specifically, for a signal DATA_IN having (h+1) bits <h:0>(and thus for the corresponding signal DIN <h:0>), the current absorbed depends on the number of bits y (0≤y≤h+1) effectively written (for example, the signal DIN <h:0>For example, assuming that y=5 bits must be written:

[0113] In the case of a set operation, the current required during the interval ΔT2 corresponds to I max,h =5I set ;and

[0114] In the case of a reset operation, the current required during the interval ΔT1 corresponds to I max,h =5I reset .

[0115] On the contrary, consider dividing into 16 levels and then gradually reducing the above current (for example, I max,h ,14 / 16I max,h ,…,1 / 16I max,h ,0).

[0116] Therefore, in the embodiment considered, not only one transistor NB is used, but (m+1) transistors NB (hereinafter referred to as transistors NB) are used. <m:0>). Specifically, the transistor NB <m:0>Each transistor NB in ​​is connected (eg, directly) to a corresponding switch PB between terminals 30a and 32a, the set of switches being referred to hereinafter as switch PB. <m:0>. Thus, each switch PB enables selective activation of a current flowing through a corresponding FET NB. For example, in the embodiment under consideration, the switch PB is also a FET. For example, in various embodiments, the switch PB is a p-channel FET (e.g., PMOS) and the transistor NB is an n-channel FET (e.g., NMOS). In this case, the source terminal of each transistor PB can be connected (e.g., directly) to the terminal 30a, the drain terminal of each transistor PB can be connected (e.g., directly) to the drain terminal of the corresponding transistor NB, and the source terminal of the corresponding transistor NB can be connected (e.g., directly) to the terminal 32a.

[0117] Specifically, in the embodiment considered, each of the switches PB (eg, the respective gate terminals) is driven by means of the signal OUT_STAGE, and thus the signal OUT_STAGE has a value hereinafter referred to as OUT_STAGE <m:0>Therefore, the signal OUT_STAGE enables the selective activation of the current flowing through the transistor NB. <m:0>Therefore, the control circuit 2124a can use the signal OUT_STAGE <m:0>To configure the characteristics of the current supply.

[0118] In particular, the inventors have noticed that the main variation in the required current is due to the variation in the number of cells to be programmed. In fact, in general, the number of driver circuits corresponds to the number of bits (h+1) of the signal DIN / DATA_IN. Therefore, the required current at the beginning of the interval ΔT1 ranges from 0 to I max,h =I reset y, and the required current range at the beginning of interval ΔT2 is 0 to I max,h =I set ·y, where y corresponds to the number of bits of the signal DIN to be written. Therefore, in various embodiments, the number of branches (m+1) corresponds to the number of bits of the signal DIN (h+1). For example, considering a 32-bit data signal DIN, the regulator 2128a may include 32 branches. Therefore, the number of branches (m+1) depends on the coefficient x and the number of bits of the signal DIN (h+1), that is, (m+1)=x·(h+1). For example, in this case, the number of branches to be activated may correspond to x·y.

[0119] Instead, consider the current (PART_CURR) during the interval ΔT3 of the set operation. <k:0>), the number of activated branches should be gradually reduced during the interval ΔT3. For example, assuming that the current is divided into (k+1)=16 levels (from 15 to 0) and the number of bits to be written y is equal to 32, the control circuit 2124a can set the signal OUT_STAGE so that 32 branches are activated during the interval ΔT2 (x=1), and then gradually reduce the number of activated branches from 30 to 0 (for example, 30, 28, 26, ..., 2, 0); that is, the number of activated branches is reduced in steps corresponding to (x·y) / (k+1).

[0120] For example, in various embodiments, the control circuit 2124a does not directly provide the signal OUT_STAGE <m:0>, but provides a signal OSTAGE having (p+1) bits <p:0>, where (m+1)=2^(p+1). In particular, the signal OSTAGE <p:0>The value of can directly indicate the number of branches to be activated. For example, in Figure 10 In FIG, a decoder circuit 38 is illustrated which receives the signal OSTAGE at input and provides the signal OUT_STAGE at output, such that the number of branches to be activated corresponds to the value encoded with the signal OSTAGE. Figure 10 , where output stage 36 includes 32 branches and the value of signal OSTAGE corresponds to 31 and then gradually decreases (as shown below: 29, 27, 25, ..., 1, 0). Specifically, in this case, the number of branches to be activated can correspond to OSTAGE+1, for example, 32 branches for a value of OSTAGE of 31. In this case, one of the branches of output stage 36 is therefore always activated when signal WRITE_EN enables output stage 36.

[0121] Thus, typically, the control circuit 2124a generates a signal OUT_STAGE (or OSTAGE) such that a given number of branches is activated, which (in addition to the scaling factor x) depends on the number of bits (y) of the data signal DIN to be written and, in the case of a set operation, on the division of the current (k+1 levels).

[0122] Therefore, when the scaling factor x is low, the reduction may not correspond to an integer, and thus the compensation may not be optimal. However, as will be described in more detail below, since transistor NB functions as a source follower and allows more or less current to flow depending on the voltage difference between the gate terminal and the source terminal, the above-mentioned difference can be compensated in any case.

[0123] Typically, the relationship between the number of branches to be activated and the subsequent partitioning may also be stored in a lookup table.

[0124] Instead, the maximum current drawn by an individual cell (given by the signal PG_DAC) must also be considered. <i:0>Indicated I set or I reset ), the regulating circuit should supply each transistor NB <m:0>The gate terminal of each transistor NB applies a voltage so that the current I C Through, the current I C Should be with I set or I reset Basically proportional, that is, I C =I set / x or I C =I reset For example, considering the case where the number of branches (m+1) corresponds to the number of bits (h+1) of the signal DATA_IN, each branch should substantially provide a bit signal according to the signal PG_DAC. <i:0>The selected current IC = I set or IC=I reset .

[0125] Basically, in the embodiment considered, the regulation circuit comprises a first branch comprising a transistor N1 (of the same channel type as transistor NB) and a current generator 2132a connected in series between terminals 30a and 30b. In various embodiments, a transistor P1 (of the same channel type as transistor PB) may also be connected in series with transistor N1 to compensate for the presence of transistor PB. Typically, the gate terminal of transistor P1 may be connected to a voltage that enables transistor P1 to be closed, for example, to the voltage on terminal 30b when using a p-channel FET.

[0126] For example, in the embodiment considered, transistor P1 is a p-channel FET and transistor N1 is a p-channel FET. In this case, the source terminal of transistor P1 can be connected (e.g., directly) to terminal 30a, the drain terminal of transistor P1 can be connected (e.g., directly) to the drain terminal of transistor N1, and the source terminal of transistor N1 can be connected (e.g., directly) to terminal 30b through current generator 2132a.

[0127] In the embodiment under consideration, the voltage VREPLICA at the midpoint between transistor N1 and current generator 2132a is supplied to a first input terminal of operational amplifier O2 via a voltage divider. Specifically, in the embodiment under consideration, the voltage divider comprises two resistors R3 and R4 connected between the midpoint between transistor N1 and current generator 2132a and terminal 30b. Thus, the voltage divider supplies a voltage proportional to voltage VREPLICA. A second input terminal of operational amplifier O2 is connected to a reference voltage V BGAP , and the output of operational amplifier O2 drives the gate terminal of transistor N1. Therefore, operational amplifier O2 changes the voltage on the gate terminal of transistor N1 so that the voltage on the source terminal of transistor N1 corresponds to VREPLICA=V BGAP (1+R3 / R4).

[0128] For example, when transistor N1 (and likewise transistor NB) is an n-channel FET, voltage divider R3 / R4 can be connected to the negative input terminal of operational amplifier O2, and voltage V BGAP Conversely, when transistor N1 (and similarly transistor NB) is a p-channel FET, voltage divider R3 / R4 can be connected to the positive input terminal of operational amplifier O2, and voltage V BGAP Can be connected to the negative input terminal. Preferably, the voltage V BGAP It is a very stable reference voltage that is practically insensitive to process scaling as well as power supply and temperature variations.

[0129] In the embodiment considered, the regulation circuit includes a second branch corresponding to the first branch; that is, the second branch includes a transistor N2 (which has the same channel type as transistor N1) and a current generator 2132b connected in series between terminals 30a and 30b. In various embodiments, a transistor P2 (which has the same channel type as transistor P1) can also be connected in series to transistor N2 to compensate for the presence of transistor PB. Typically, the gate terminal of transistor P2 can be connected to the same voltage as the gate terminal of transistor P1 is connected to (for example, to terminal 30b).

[0130] Basically, transistor N2 is also configured as a source follower and regulates voltage VPL_REG when no branch of stage 36 is activated.

[0131] In the embodiment considered, the gate terminals of transistor N2 and transistor NB are (e.g. directly) connected to the gate terminal of transistor N1; i.e., they are therefore driven by the same voltage. Additionally, terminal 32a is connected to an intermediate point between transistor N2 and current generator 2132b.

[0132] In particular, in the embodiment considered, the generators 2132a and 2132b are configured to provide the same current, wherein the provided current can be selected according to the signal PG_DAC so that it is equal to I set or I reset To this end, the current generator can correspond substantially to the reference Figure 8 Generator 2132 described.

[0133] Therefore, in the embodiment considered, transistors N1, N2 and NB are configured as source followers, and the regulation is not based on feedback of the output voltage VPL_REG, but on feedback of its replica VREPLICA, with benefits in terms of frequency stability and response speed. The circuit is essentially based on the concept of "replicas", where the matching between transistors N1 and N2, which are source followers traversed by the same current (with transistor PD disabled), makes it possible to track process expansion and temperature variations, thus maintaining the output voltage VPL_REG at the desired value.

[0134] Therefore, in various embodiments, the phase change memory includes an array 200 of phase change memory cells CELL, wherein a set current I set For a given time interval ΔT2, the memory cell CELL may enter a polycrystalline state from an amorphous state with low conductivity. Address decoders 202 and 204 enable selection of a subregion in the array 200, where the selected subregion has the same number of bits as the data signal DATA_IN.

[0135] In various embodiments, the control circuit 2124a determines, for each memory cell in the selected sub-region, whether the corresponding bit of the data signal DATA_IN indicates that the memory cell is to enter a polycrystalline state with high conductivity from an amorphous state with low conductivity, or vice versa. Conversely, the one or more driver circuits 2126a set the current I set Applied to the aforementioned memory cells. Thus, the current sunk by the one or more driver circuits 2126a varies based on the number of memory cells to be programmed.

[0136] In various embodiments, the one or more driver circuits 2126a are powered via a regulated voltage VPL_REG, which is provided via a voltage regulator 2128a.

[0137] Specifically, in various embodiments, the voltage regulator 2128a includes a positive input terminal 30a and a negative input terminal 30b for receiving a supply voltage Vcc, and a positive output terminal 32a and a negative output terminal 32b for providing a regulated voltage VPL_REG. Specifically, as shown in FIG9 , the voltage regulator 2128a includes a capacitor Ctank connected between the positive output terminal 32a and the negative output terminal 32b.

[0138] In various embodiments, the output stage 36 of the voltage regulator 2128a includes a plurality of branches. Typically, each branch includes a voltage generator connected between the positive input terminal 30a and the positive output terminal 32a. Specifically, each voltage generator is configured to generate (e.g., via a corresponding transistor NB) a current IC, a current I C Varies according to the drive signal and the voltage VPL_REG (specifically, the difference between the voltage of the drive signal and the voltage VPL_REG). Additionally, each voltage generator can be selectively activated (eg, via a corresponding electronic switch PB) according to a corresponding signal OUT_STAGE, which essentially represents an enable signal.

[0139] Finally, the regulation circuit of the voltage regulator 2128a generates a drive signal for the variable current generator (eg, for the gate terminal of the transistor NB) to regulate the voltage VPL_REG between the output terminals (eg, directly following the VPL_REG voltage). Figure 6A or Figure 6B , for example using output stage 36 instead of transistor M1 or M2, or indirectly as shown in FIG. 9 ) to the desired value.

[0140] In this case, in various embodiments, the control circuit 2124a may therefore determine the number of memory cells to be programmed / set and generate the enable signal OUT_STAGE according to the number.

[0141] 9 , output stage 36 includes a certain number (m+1) of branches, which are the same as the branches that constitute the series transistors P2-N2 and P1-N1 that can be activated by the configuration signal OUT_STAGE. Once the number of cells to be programmed (y) is determined, control circuit 2124a can determine the number (x·y) of branches of output stage 36 to be activated so that the output voltage VPL_REG remains exactly equal to the desired voltage VREPLICA during the write operation.

[0142] The stability of the output voltage VPL_REG is also maintained during transients, when the current drawn by the load can very quickly pass from zero to a steady-state value. For example, for this purpose, the signal OUT_STAGE cannot be applied directly to the switch PB, but the switch PB can be driven by means of a logic gate 34 (e.g., an AND gate) which receives the signal OUT_STAGE and the signal WRITE_EN at its inputs. Thus, in this way, the output stage 36 is activated only when the driver circuit 2126a is drawing current. This synchronization makes it possible to reduce the risk of output oscillations, which are typical of closed-loop regulators according to the prior art, in the presence of rapid changes in the load current.

[0143] In practically any case, unavoidable time offsets may generate slight variations in the output voltage, which can be reduced by using filtering capacitors on the regulator output.

[0144] As previously mentioned, by selecting an appropriate number of branches for the stage 36, the compensation can be substantially perfect when performing a reset of the memory cell. Conversely, in the case of a set pulse (in which the current of the cell is divided according to a staircase pattern), the control circuit 2124a can in any case achieve a continuous adaptation of the drive capability of the output stage 36 to the current effectively required by the load (i.e., the driver circuit 2126a). As previously mentioned, the control circuit 2124a can use a lookup table for this purpose, using the signal PART_CURR <k:0>The bit configuration of the signal OUT_STAGE provided to the output stage 36 is retrieved from the lookup table at the appropriate timing of the synchronization.

[0145] Therefore, if Figure 12 As shown, for the exemplary case of 32 branches of the output stage 36, where the signal OSTAGE selects between 0 and 31 (i.e., a branch is enabled when the signal WRITE_EN is set), such a lookup table typically has a number of rows equal to the maximum number of y and a number of columns equal to the number of steps (k+1) (i.e., in the embodiment considered, equal to the number of columns that make up the signal vector PART_CURR <k:0>For example, Figure 12 Shown in is the corresponding binary value of the signal OSTAGE.

[0146] Figure 13 A portion of an electronic system 130 according to the present disclosure is shown. The electronic system 130 may be used in an electronic device (e.g., a PDA (personal digital assistant); a portable or fixed computer, possibly with wireless data transmission capabilities; a mobile phone; a digital audio player; a camera or video camera; or other device capable of processing, storing, transmitting, and receiving information).

[0147] Specifically, the electronic system 130 includes a (non-volatile) memory 20 having the previously described phase-change memory cell and a processing unit 131 (e.g., equipped with a microprocessor, DSP, or microcontroller), both of which are coupled to a bus 136 designed to exchange data with the memory 20. Therefore, the processing unit 131 can generate the previously described signals ADR and DATA_IN.

[0148] Additionally, the electronic system 130 may optionally include one or more of the following elements coupled to the bus 136:

[0149] Input / output device 132 (e.g., equipped with a keypad and a display) for inputting and displaying data;

[0150] a wireless interface 134 (e.g., an antenna) for transmitting and receiving data via a radio frequency wireless communication network;

[0151] RAM 135;

[0152] a battery 137 , which may be used as a power source in the electronic system 130 ; that is, the battery 137 may provide a supply voltage Vcc; and

[0153] Camera and / or video camera 138 .

[0154] In various embodiments, processing unit 131 may be connected to memory 20 through a dedicated connection distinct from, and possibly in addition to, bus 136 (thus, bus 136 may or may not be present).

[0155] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined in the appended claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A phase change memory, comprising: an array of a plurality of phase change memory cells, wherein the memory cells are capable of changing from an amorphous state having low conductivity to a polycrystalline state having high conductivity by applying a set current for a first interval; an address decoder configured to receive an address signal and select a sub-region in the array of the plurality of phase-change memory cells, the selected sub-region having a data signal of a given number of bits; as well as Writing circuit, including: a control circuit configured to receive the data signal and, for each memory cell in the selected sub-region, determine whether a corresponding bit of the data signal indicates that the memory cell is to change from the amorphous state to the polycrystalline state; one or more driver circuits powered via a regulated voltage and configured to apply the set current to the memory cell that is to change from the amorphous state to the polycrystalline state for the first interval; and Voltage regulator, including: positive and negative input terminals for receiving a supply voltage, and positive and negative output terminals for providing the regulated voltage to the one or more driver circuits; a capacitor connected between the positive output terminal and the negative output terminal; an output stage comprising a plurality of branches, wherein each branch comprises a voltage generator connected between the positive input terminal and the positive output terminal, wherein each voltage generator is configured to generate a variable current according to a drive signal and the regulated voltage, and wherein each voltage generator is selectively activated according to a corresponding enable signal; and a regulating circuit configured to generate a drive signal for the voltage generator in such a manner as to regulate the voltage between the positive output terminal and the negative output terminal to a desired value, The control circuit is configured to: determining a number of the memory cells that will change from the amorphous state to the polycrystalline state; and The enable signal is generated according to the number of the memory cells to be changed from the amorphous state to the polycrystalline state. 2 . The phase-change memory according to claim 1 , wherein the number of branches of the output stage corresponds to a predetermined coefficient multiplied by a predetermined number of bits of the data signal. The phase change memory according to claim 2 , wherein the predetermined coefficient is equal to 1.

4. The phase change memory according to claim 2 , wherein the one or more driving circuits are configured to apply a current to the memory cell that is to be changed from the amorphous state to the polycrystalline state, the current decreasing from the set current to zero according to a division signal within a second interval.

5. The phase-change memory of claim 4 , wherein generating the enable signal according to the number of the memory cells to be changed from the amorphous state to the polycrystalline state comprises generating the enable signal in such a manner that a second variable number of the voltage generators are activated during the second interval, the second variable number being determined according to the number of the memory cells and the division signal.

6. The phase-change memory of claim 1 , wherein generating the enable signal according to the number of the memory cells that are to be changed from the amorphous state to the polycrystalline state comprises generating the enable signal in a manner such that a first number of the voltage generators are activated during the first interval, and wherein the first number corresponds to a predetermined coefficient multiplied by the number of the memory cells that are to be changed from the amorphous state to the polycrystalline state. The phase change memory according to claim 6 , wherein the predetermined coefficient is equal to 1.

8. The phase change memory according to claim 6, wherein the one or more driving circuits are configured to apply a current to the memory cell that is to be changed from the amorphous state to the polycrystalline state, the current decreasing from the set current to zero according to a division signal within a second interval.

9. The phase-change memory of claim 8 , wherein generating the enable signal according to the number of the memory cells to be changed from the amorphous state to the polycrystalline state comprises generating the enable signal in such a manner that a second variable number of the voltage generators are activated during the second interval, the second variable number being determined according to the first number and the division signal.

10. The phase-change memory according to claim 1 , wherein each voltage generator comprises a first field-effect transistor and an electronic switch, the first field-effect transistor and the electronic switch being connected in series between the positive input terminal and the positive output terminal, wherein a gate terminal of the first field-effect transistor is driven via a corresponding drive signal, and wherein the electronic switch is driven via a corresponding enable signal.

11. The phase change memory according to claim 10, further comprising: a second field effect transistor and a first current generator, the second field effect transistor and the first current generator being connected in series between the positive input terminal and the negative input terminal, wherein the second field effect transistor has the same type of channel as the first field effect transistor; a voltage divider configured to provide a voltage proportional to the voltage across the first current generator; as well as An operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to a reference voltage, the second input terminal is connected to the voltage proportional to the voltage on the first current generator, and the output terminal is connected to the gate terminal of the first field effect transistor and the gate terminal of the second field effect transistor.

12. The phase change memory according to claim 11, further comprising: a third field-effect transistor and a second current generator, the third field-effect transistor and the second current generator being connected in series between the positive input terminal and the negative input terminal, wherein the third field-effect transistor has a channel of the same type as that of the first field-effect transistor, wherein the second current generator is configured to provide a current corresponding to the current provided by the first current generator, wherein the output terminal of the operational amplifier is connected to the gate terminal of the third field-effect transistor, and wherein an intermediate point between the third field-effect transistor and the second current generator is connected to the positive output terminal. 13 . The phase change memory according to claim 11 , wherein the first current generator is configured to provide a current proportional to the set current according to a selection signal.

14. The phase change memory according to claim 1, wherein the memory cell is capable of changing from the polycrystalline state to the amorphous state by applying a reset current for a third interval, and The one or more driving circuits are configured to apply the reset current to the memory cells in the selected sub-region for the third interval. 15 . The phase-change memory according to claim 14 , wherein the first current generator is configured to provide a current proportional to the reset current according to a selection signal.

16. An electronic system comprising: processing unit; as well as The phase change memory according to claim 1.

17. A voltage regulator comprising: positive and negative input terminals for receiving a supply voltage, and positive and negative output terminals for providing a regulated voltage to one or more driver circuits; a capacitor connected between the positive output terminal and the negative output terminal; an output stage comprising a plurality of branches, wherein each branch comprises a voltage generator connected between the positive input terminal and the positive output terminal, wherein each voltage generator is configured to generate a variable current according to a drive signal and the regulated voltage, and wherein each voltage generator is selectively activated according to a corresponding enable signal; as well as a regulating circuit configured to generate a drive signal for the voltage generator in such a manner as to regulate the voltage between the positive output terminal and the negative output terminal to a desired value, Each voltage generator includes a first field effect transistor and an electronic switch, the first field effect transistor and the electronic switch being connected in series between the positive input terminal and the positive output terminal, wherein a gate terminal of the first field effect transistor is driven via a corresponding drive signal, and wherein the electronic switch is driven via a corresponding enable signal to activate the first field effect transistor.

18. The voltage regulator according to claim 17, further comprising: a second field effect transistor and a first current generator, the second field effect transistor and the first current generator being connected in series between the positive input terminal and the negative input terminal, wherein the second field effect transistor has the same type of channel as the first field effect transistor; a voltage divider configured to provide a voltage proportional to the voltage across the first current generator; as well as An operational amplifier comprising a first input terminal connected to a reference voltage, a second input terminal connected to a voltage proportional to the voltage on the first current generator, and an output terminal connected to the gate terminal of the first field effect transistor and the gate terminal of the second field effect transistor.

Images