Non-volatile memory device

Abstract

A non-volatile memory device includes a first semiconductor layer, a second semiconductor layer, a control circuit, and a pad region, the first semiconductor layer including an upper substrate and an array of memory cells, word lines extending in a first direction and bit lines extending in a second direction disposed in the upper substrate. The array of memory cells includes vertical structures located on the upper substrate, and the vertical structures include memory blocks. The second semiconductor layer includes a lower substrate including an address decoder and a page buffer circuit. The vertical structures include via regions with one or more through-via vias disposed therein, and the via regions are spaced apart in the second direction. The array of memory cells includes pads corresponding to different ones of the bit lines. At least two of the pads include different numbers of the via regions according to a distance from the pad region in the first direction.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0148349, filed on November 19, 2019 with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to memory devices, and more specifically to non-volatile memory devices. Background Technology

[0004] Semiconductor memory devices can be volatile or non-volatile. Flash memory devices are typically non-volatile semiconductor memory devices. Flash memory devices can be used as data storage media for voice and image data in information devices such as computers, cellular phones, personal digital assistants (PDAs), digital cameras, and handheld personal computers (PCs).

[0005] Recently, non-volatile memory devices with three-dimensionally stacked memory cells have been investigated to improve the integrity of non-volatile memory devices. As information communication devices are developed to have many functions, the memory used in such devices may require large capacity and high integration. As memory cell size decreases to achieve high integration, the structural complexity of the operating circuitry and / or wiring included in the memory device may degrade electrical characteristics. Summary of the Invention

[0006] According to an example embodiment of the inventive concept, a non-volatile memory device includes a first semiconductor layer, a second semiconductor layer, a control circuit, and a pad region. The first semiconductor layer includes an upper substrate having a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction, and a memory cell array including vertical structures on the upper substrate, wherein the vertical structures include a plurality of memory blocks. The second semiconductor layer is disposed below the first semiconductor layer in a third direction perpendicular to the first and second directions, and includes a lower substrate including a plurality of address decoders and a plurality of page buffer circuits configured to control the memory cell array. The control circuit controls the plurality of address decoders and the plurality of page buffer circuits in response to commands and addresses from an external device. The pad region is disposed adjacent to the first semiconductor layer in the first direction and extends in the second direction. The vertical structures include a plurality of via regions having one or more through-via vias disposed therein, and the plurality of via regions are spaced apart in the second direction. The memory cell array includes a plurality of pads corresponding to different bit lines of the plurality of bit lines. At least two pads of the plurality of pads include different numbers of via regions according to a distance from the pad region in the first direction.

[0007] According to example embodiments of the inventive concepts, a non-volatile memory device includes a first semiconductor layer, a second semiconductor layer, a control circuit, and a pad region. The first semiconductor layer includes an upper substrate having a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction disposed therein, and a memory cell array including vertical structures on the upper substrate, wherein the vertical structures include a plurality of memory blocks. The second semiconductor layer is disposed below the first semiconductor layer in a third direction perpendicular to the first and second directions, and includes a lower substrate including a plurality of address decoders and a plurality of page buffer circuits configured to control the memory cell array. The control circuit controls the plurality of address decoders and the plurality of page buffer circuits in response to commands and addresses from an external device. The pad region is disposed adjacent to the first semiconductor layer in the first direction and extends in the second direction. The vertical structures include a plurality of via regions having one or more through-via vias disposed therein, and the plurality of via regions are spaced apart in the second direction. At least a first portion of the one or more through-via vias connects at least some portions of the plurality of bit lines to at least some portions of the plurality of page buffer circuits. At least a second portion of the one or more through-via vias connects at least some portions of the plurality of word lines to at least some portions of the plurality of address decoders. The memory cell array includes a plurality of pads corresponding to different bit lines of the plurality of bit lines. Each of the plurality of pads includes a first tile and a second tile identified based on a distance from the pad region in the first direction. The first tile and the second tile include different numbers of via regions according to the distance from the pad region in the first direction.

[0008] According to an example embodiment of the inventive concept, a non-volatile memory device includes a first semiconductor layer, a second semiconductor layer, a control circuit, and a pad area. The first semiconductor layer includes an upper substrate in which a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction are disposed, and a memory cell array including vertical structures on the upper substrate, wherein the vertical structures include a plurality of memory blocks. The second semiconductor layer is disposed below the first semiconductor layer in a third direction perpendicular to the first and second directions, and includes a lower substrate including a plurality of address decoders configured to control the memory cell array and a plurality of page buffer circuits. The control circuit controls the plurality of address decoders and the plurality of page buffer circuits in response to commands and addresses from an external device. The pad area is disposed adjacent to the first semiconductor layer in the first direction and extends in the second direction. A plurality of input / output pads and at least one power pad are disposed in the pad area. The vertical structures include a plurality of via regions in which one or more via through holes are disposed, and the plurality of via regions are spaced apart in the second direction. The at least one power pad is disposed adjacent to a first edge portion of the pad area. The memory cell array includes a plurality of pads corresponding to different bit lines of the plurality of bit lines. At least two pads of the plurality of pads include different numbers of via regions according to a distance from the at least one power pad in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other features of the inventive concept will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:

[0010] Figure 1 is a block diagram illustrating a memory device according to an example embodiment of the inventive concept.

[0011] Figure 2 is a block diagram illustrating a memory controller in the memory device of Figure 1 according to an example embodiment of the inventive concept.

[0012] Figure 3 is a block diagram illustrating a non-volatile memory device in the memory device of Figure 1 according to an example embodiment of the inventive concept.

[0013] Figure 4 is a diagram illustrating a structure of the non-volatile memory device of Figure 3 according to an example embodiment of the inventive concept.

[0014] Figure 5 is a perspective view illustrating a memory block of Figure 3 according to an example embodiment of the inventive concept.

[0015] Figure 6 is a plan view showing a memory cell array of Figure 5 according to an example embodiment of the present inventive concept.

[0016] Figure 7 is a plan view showing a cell region of a memory cell array in which Figure 3 according to an example embodiment of the present inventive concept.

[0017] Figure 8A and Figure 8B is a cross-sectional view showing a memory block string of Figure 7 according to an example embodiment of the present inventive concept.

[0018] Figure 9 is a block diagram showing a control circuit in a nonvolatile memory device of Figure 3 according to an example embodiment of the present inventive concept.

[0019] Figure 10 is a block diagram showing a voltage generator in a nonvolatile memory device of Figure 3 according to an example embodiment of the present inventive concept.

[0020] Figure 11 is a plan view showing an upper surface of a second semiconductor layer in Figure 4 according to an example embodiment of the present inventive concept.

[0021] Figure 12 is a plan view showing an upper surface of a second semiconductor layer in Figure 4 according to an example embodiment of the present inventive concept.

[0022] Figure 13 is a diagram showing a first semiconductor layer in Figure 4 according to an example embodiment of the present inventive concept.

[0023] Figure 14 is a first pad in Figure 13 according to an example embodiment of the present inventive concept.

[0024] Figure 15 is a cross-sectional view taken along line VI-VI' of Figure 14 according to an example embodiment of the present inventive concept.

[0025] Figure 16 is a cross-sectional view taken along line VII-VII' of Figure 14 according to an example embodiment of the present inventive concept.

[0026] Figure 17showing an example of a plurality of pads in the Figure 13 including different numbers of via regions according to example embodiments of the inventive concept.

[0027] Figure 18 is a cross-sectional view taken along the line VIII-VIII' of Figure 17 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0028] Figure 19 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0029] Figure 20 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0030] Figure 21 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0031] Figure 22 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0032] Figure 23 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0033] Figure 24 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0034] Figure 25 Figure 13 showing an example of a plurality of pads in the including different numbers of via regions according to example embodiments of the inventive concept.

[0035] Figure 26 is a block diagram showing an address decoder in a non-volatile memory device according to example embodiments of the inventive concept. Figure 3

[0036] is a block diagram showing a solid state disk or drive (SSD) including a non-volatile memory device according to example embodiments of the inventive concept. Figure 27 DETAILED DESCRIPTION

[0037] Exemplary embodiments of the inventive concept provide a non-volatile memory device having enhanced performance and reduced size.

[0038] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the application.

[0039] Figure 1 is a block diagram illustrating a memory device according to exemplary embodiments of the inventive concept.

[0040] Referring to Figure 1 , the memory device (or memory system) 30 can include a memory controller 40 and a non-volatile memory device (NVM) 50.

[0041] In exemplary embodiments of the inventive concept, each of the memory controller 40 and the non-volatile memory device 50 can be provided in the form of a chip, a package, or a module. Alternatively, the memory controller 40 and the non-volatile memory device 50 can be mounted on various packages to be provided as a memory device such as a memory card.

[0042] The non-volatile memory device 50 can perform a read operation, an erase operation, and a program operation or a write operation under the control of the memory controller 40. The non-volatile memory device 50 receives a command CMD, an address ADDR, and data DATA from the memory controller 40 through input / output lines for performing these operations. In addition, the non-volatile memory device 50 receives a control signal CTRL from the memory controller 40 through a control line. In addition, the non-volatile memory device 50 receives power PWR from the memory controller 40 through a power supply line.

[0043] The non-volatile memory device 50 can include a memory cell array 100 to store data DATA, and the memory cell array 100 can include a plurality of pads MT1, MT2, MT3, and MT4 corresponding to different bit line pairs.

[0044] The memory cells of the non-volatile memory device 50 can have physical characteristics whose threshold voltage distributions vary due to different reasons such as program-erase time, temperature, program disturb, read disturb, etc. Accordingly, the data stored at the non-volatile memory device 50 can be erroneous (e.g., have errors) due to the above reasons. The memory controller 40 can correct these errors using various error correction techniques. For example, the memory controller 40 can include an error correction code (ECC) engine 42.

[0045] The memory controller 40 can perform an erase operation on the non-volatile memory device 50 in units of sub-blocks, and a sub-block is smaller than one memory block of the non-volatile memory device 50. As an example, one memory block can include a plurality of sub-blocks. The memory controller 40 can include an erase management module 43a to manage the erase operation in units of sub-blocks (e.g., sub-block erase operation).

[0046] After the sub-block erase operation, the erase management module 43a can check the erase status of the erased sub-block and / or a sub-block adjacent to the erased sub-block. For example, the erase management module 43a can sense memory cells of the erased sub-block to determine whether a particular parameter exceeds a reference value. The erase management module 43a can read data of a sub-block adjacent to the erased sub-block to detect an erase inhibit efficiency. For example, the erase management module 43a can detect a bit error rate (BER) based on the data read from the erased sub-block. The erase management module 43a can acquire and monitor wear leveling information (e.g., erase count) regarding the erased sub-block. In addition, the erase management module 43a can read data of the erased sub-block to monitor a change in threshold voltage of selected memory cells and / or a change in bit error rate (BER). The erase management module 43a can also read data of unselected sub-blocks to detect a change in threshold voltage. The memory controller 40 can perform various processes to compensate for an insufficient erase of a selected sub-block based on the erase status information detected by the erase management module 43a.

[0047] Generally, a memory block is the largest unit of memory that can be erased at the same time. In a three-dimensional non-volatile memory device in which word lines are stacked in a direction crossing (e.g., perpendicular to) a substrate, a memory block can be defined as a set of cell strings sharing all of the stacked word lines. A sub-block corresponds to a sub-memory unit defined by dividing a memory block (or physical block) in units of word lines or in units of select lines. For example, each sub-block can be formed of memory cells sharing a portion of the word lines of a memory block.

[0048] During a read operation on the non-volatile memory device 50, the memory controller 40 can read data stored at a first page of the non-volatile memory device 50 using a default set of read voltages. The default set of read voltages can include predetermined read voltages. The ECC engine 42 can detect and correct errors included in the data read from the non-volatile memory device 50. The ECC engine 42 can perform an ECC operation by detecting and correcting errors. In an example embodiment of the present inventive concept, the ECC engine 42 can be implemented in the form of hardware. The ECC engine 42 can determine a frequency of error occurrence of the data read from the non-volatile memory device 50 in units of sub-blocks, and can designate a sub-block as a bad sub-block when the frequency of error occurrence is greater than a reference value during a predetermined time.

[0049] Figure 2is to illustrate exemplary embodiments according to the inventive concept Figure 1 a block diagram of a memory controller in a storage device.

[0050] Referring to Figure 1 and Figure 2 The memory controller 40 can include a processor 41, an ECC engine 42, a buffer 43, an erase management module 43a, a randomizer 44, a host interface 45, a read only memory (ROM) 46, and a non-volatile memory interface 47 connected via a bus 48. The ECC engine 42 and the erase management module 43a are described with reference to Figure 1 , and thus a description thereof is omitted.

[0051] The processor 41 controls overall operations of the memory controller 40. In exemplary embodiments of the inventive concept, the erase management module 43a can be implemented in software and stored in the buffer 43. The erase management module 43a stored in the buffer 43 can be driven by the processor 41. The ROM 46 stores various information in firmware for operations of the memory controller 40. The buffer 43 can store data provided from the non-volatile memory device 50 and can include the erase management module 43a.

[0052] The randomizer 44 randomizes data to be stored in the non-volatile memory device 50. For example, the randomizer 44 can randomize data to be stored in the non-volatile memory device 50 in units of a word line.

[0053] Data randomization is to process data so that programming states of memory cells connected to a word line have the same ratio. For example, if memory cells connected to one word line are multi-level cells (MLC) each storing 2-bit data, each memory cell has an erased state and one of first to third programming states. In this case, the randomizer 44 randomizes data so that the number of memory cells having the erased state, the number of memory cells having the first programming state, the number of memory cells having the second programming state, and the number of memory cells having the third programming state among memory cells connected to one word line are substantially the same as each other. For example, memory cells in which randomized data is stored have programming states in the number equal to each other. The randomizer 44 also de-randomizes data read from the non-volatile memory device 50.

[0054] The memory controller 40 communicates with the external host 20 through a host interface 45. For example, the host interface 45 can include a universal serial bus (USB), a multimedia card (MMC), an embedded MMC, a peripheral component interconnect (PCI), a high-speed PCI, an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a mobile industry processor interface (MIPI), a non-volatile memory express (NVMe), a universal flash storage (UFS), or the like. The memory controller 40 communicates with the non-volatile memory device 50 through a non-volatile memory interface 47.

[0055] Figure 3 is a block diagram of a non-volatile memory device in a storage device according to an example embodiment of the inventive concept. Figure 1

[0056] Referring to Figure 3 The non-volatile memory device 50 includes a memory cell array 100, an address decoder 600, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 500, and a voltage generator 700.

[0057] The memory cell array 100 can be coupled to the address decoder 600 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. In addition, the memory cell array 100 can be coupled to the page buffer circuit 410 through a plurality of bit lines BLs.

[0058] The memory cell array 100 can include a plurality of pads MT1, MT2, MT3, and MT4 corresponding to different bit lines. The memory cell array 100 can include a plurality of memory cells coupled to the plurality of word lines WLs and the plurality of bit lines BLs. Each of the plurality of pads MT1, MT2, MT3, and MT4 can include a plurality of memory blocks BLK1 to BLKz (where z is an integer greater than 2), and each memory block can have a planar structure or a three-dimensional (3D) structure. The memory cell array 100 can include a single-level cell (SLC) block including a single-level cell (SLC), a multi-level cell (MLC) block including a multi-level cell (MLC), for example, a triple-level cell (TLC) block including a triple-level cell (TLC) or a quad-level cell (QLC) block including a quad-level cell (QLC). For example, some of the memory blocks BLK1 to BLKz can be a single-level cell block, and other memory blocks can be a multi-level cell block, for example, a triple-level cell block or a quad-level cell block.

[0059] ​In exemplary embodiments of the inventive concept, the memory cell array 100 can include a vertical structure on the upper substrate. For example, the vertical structure can include a plurality of via regions, and in the via regions, one or more first via holes are provided spaced apart in the second direction. A plurality of pads MT1, MT2, MT3, and MT4 can be formed in a cell region adjacent to the pad region. The plurality of pads MT1, MT2, MT3, and MT4 can include different numbers of via regions according to a distance from the pad region in a first direction crossing (e.g., perpendicular to) the second direction.

[0060] The control circuit 500 can receive a command (signal) CMD and an address (signal) ADDR from the memory controller 40, and control an erase operation, a program operation, and a read operation of the nonvolatile memory device 50 based on the command signal CMD and the address signal ADDR.

[0061] In exemplary embodiments of the inventive concept, the control circuit 500 can generate control signals CTLs for controlling the voltage generator 700 based on the command signal CMD, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 500 can provide the row address R_ADDR to the address decoder 600 and the column address C_ADDR to the data input / output circuit 420. The control circuit 500 can also provide a meta signal MTS associated with a property of data to be stored to the address decoder 600.

[0062] The address decoder 600 can transfer voltages to the string selection line SSL, the plurality of word lines WLs, and the ground selection line GSL for operating the memory cells of the memory cell array 100 in response to the address signal ADDR and the command signal CMD received from the memory controller 40 by receiving various word line voltages VWLs from the voltage generator 700. The voltage generator 700 can provide the word line voltages VWLs to the address decoder 600 to the memory cell array 100 in response to the control signals CTLs received from the control circuit 500. The address decoder 600 can include a first address decoder 601 and a second address decoder 603, which will be described in detail below.

[0063] For example, during a program operation, the voltage generator 700 can apply a program voltage to a selected word line and can apply a program pass voltage to an unselected word line. Also, during a program verify operation, the voltage generator 700 can apply a program verify voltage to the selected word line and can apply a verify pass voltage to the unselected word line. Also, during a read operation, the voltage generator 700 can apply a read voltage to the selected word line and can apply a read pass voltage to the unselected word line.

[0064] The page buffer circuit 410 can be coupled to the memory cell array 100 through a plurality of bit lines BLs. The page buffer circuit 410 can include a plurality of page buffers. The page buffer circuit 410 can temporarily store data to be programmed in a selected page of the memory cell array 100 or data read out from the selected page. The page buffer circuit 410 can include a plurality of page buffers. The page buffer circuit 410 can temporarily store data to be programmed in the selected page and can temporarily store data read from the selected page. The page buffer circuit 410 can be controlled by a control signal PCTL received from the control circuit 500. The page buffer circuit 410 can include a first page buffer circuit 411 and a second page buffer circuit 413 which will be described in detail below.

[0065] The data input / output circuit 420 can be coupled to the page buffer circuit 410 through a plurality of data lines DLs. During a program operation, the data input / output circuit 420 can receive program data DATA (e.g., data DATA) from the memory controller 40 and provide the program data DATA to the page buffer circuit 410 based on a column address C_ADDR received from the control circuit 500. During a read operation, the data input / output circuit 420 can provide read data DATA (e.g., data DATA) stored in the page buffer circuit 410 to the memory controller 40 based on a column address C_ADDR received from the control circuit 500. Figure 1 Figure 1

[0066] Figure 4 is a diagram illustrating a structure of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. Figure 3

[0067] Hereinafter, D1 denotes a first direction, D2 denotes a second direction crossing the first direction, and D3 denotes a third direction crossing the first and second directions.

[0068] Referring to Figure 4 , the nonvolatile memory device 50 can include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 can be stacked on the second semiconductor layer L2 in the third direction. In an exemplary embodiment of the present inventive concept, the memory cell array 100 can be formed on the first semiconductor layer L1, and at least one among the control circuit 500, the address decoder 600, and the page buffer circuit 410 can be formed on the second semiconductor layer L2. For example, various circuits can be formed on the second semiconductor layer L2 by forming semiconductor elements such as transistors and patterns for wiring the semiconductor elements on a lower substrate of the second semiconductor layer L2.

[0069] ​​​After the circuit is formed on the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100 can be formed. For example, the first semiconductor layer L1 can include a plurality of upper substrates. The memory cell array 100 can be formed on the first semiconductor layer L1 by forming a plurality of gate conductive layers stacked on each of the upper substrates and a plurality of pillars passing through the plurality of gate conductive layers and extending in a vertical direction (e.g., a third direction) perpendicular to a top surface of each of the upper substrates. In addition, patterns (e.g., word lines WL and bit lines BL) for electrically connecting the memory cell array 100 with the circuit formed on the second semiconductor layer L2 can be formed on the first semiconductor layer L1. For example, the word lines WL can extend in the first direction and can be arranged in the second direction. In addition, the bit lines BL can extend in the second direction and can be arranged in the first direction.

[0070] Accordingly, the non-volatile memory device 50 can have a cell-on-periphery or cell-over-periphery (COP) structure in which the control circuit 500, the address decoder 600, the page buffer circuit 410, or various other peripheral circuits and the memory cell array 100 are arranged in a stacking direction (e.g., a third direction).

[0071] Figure 5 is a perspective view of a memory block according to an example embodiment of the present inventive concept. Figure 3 is a perspective view of a memory block according to an example embodiment of the present inventive concept.

[0072] Referring to Figure 5 The memory block BLK1 includes a structure extending along the first direction D1 to the third direction D3.

[0073] A substrate 111 is provided. For example, the substrate 111 can have a well of a first type (e.g., a first conductive type). For example, the substrate 111 can have a p-well formed by implanting a group 3 element such as boron (B). For example, the substrate 111 can have a pocket p-well disposed in an n-well. In an example embodiment of the present inventive concept, the substrate 111 has a p-type well (or a p-type pocket well). However, the conductive type of the substrate 111 is not limited to the p-type.

[0074] A plurality of doped regions 311 to 314 extending along the second direction are disposed in / on the substrate 111. For example, the plurality of doped regions 311 to 314 can have a second type (e.g., a second conductive type) different from the first type of the substrate 111. In an example embodiment of the present inventive concept, the first doped region 311 to the fourth doped region 314 have an n-type. However, the conductive type of the first doped region 311 to the fourth doped region 314 is not limited to the n-type.

[0075] A plurality of insulating materials 112 extending along the first direction is sequentially disposed on the region of the substrate 111 between the first doped region 311 and the second doped region 312 along the third direction. For example, the plurality of insulating materials 112 is disposed to be spaced apart by a certain distance along the third direction. Illustratively, the insulating materials 112 can include an insulating material such as an oxide layer.

[0076] A plurality of pillars 113 penetrating the insulating materials along the third direction D3 is sequentially disposed on the region of the substrate 111 between the first doped region 311 and the second doped region 312 along the first direction. For example, the plurality of pillars 113 penetrates the insulating materials 112 to contact the substrate 111.

[0077] For example, each pillar 113 can include a plurality of materials. For example, a channel layer 114 of each pillar 113 can include a silicon material having a first type. For example, the channel layer 114 of each pillar 113 can include a silicon material having the same type as that of the substrate 111. In an exemplary embodiment of the inventive concept, the channel layer 114 of each pillar 113 includes p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0078] An inner material 115 of each pillar 113 includes an insulating material. For example, the inner material 115 of each pillar 113 can include an insulating material such as silicon oxide. For example, the inner material 115 of each pillar 113 can include an air gap.

[0079] An insulating layer 116 is disposed on the region between the first doped region 311 and the second doped region 312 along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. Illustratively, the insulating layer 116 disposed on the exposed surface of the last insulating material 112 in the third direction D3 can be removed.

[0080] A plurality of first conductive materials 211 to 291 is disposed on the exposed surface of the insulating layer 116 between the first doped region 311 and the second doped region 312. For example, the first conductive material 211 extending along the first direction is disposed between the substrate 111 and the insulating material 112 adjacent to the substrate 111.

[0081] The first conductive material extending along the second direction is disposed between the insulating layer 116 at the top of a certain one of the insulating materials 112 and the insulating layer 116 at the bottom of the certain one of the insulating materials 112. For example, a plurality of first conductive materials 221 to 281 extending along the second direction D2 is disposed between the insulating materials 112, and it can be understood that the insulating layer 116 is disposed between the insulating materials 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 can include a metal material. The first conductive materials 211 to 291 can include a conductive material such as polysilicon.

[0082] A structure substantially the same as that between the first doped region 311 and the second doped region 312 can be provided in a region between the second doped region 312 and the third doped region 313. For example, the region between the second doped region 312 and the third doped region 313 includes a plurality of insulating materials 112 extending along the second direction, a plurality of pillars 113 sequentially provided along the second direction D2 and penetrating the plurality of insulating materials 112 along the third direction, an insulating layer 116 provided on exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 213 to 293 extending along the second direction. The plurality of first conductive materials 213 to 293 between the second doped region 312 and the third doped region 313 can be similar to the first conductive materials 211 to 291 between the first doped region 311 and the second doped region 312.

[0083] A structure substantially the same as that on the first doped region 311 and the second doped region 312 can be provided in a region between the third doped region 313 and the fourth doped region 314. The region between the third doped region 313 and the fourth doped region 314 includes a plurality of insulating materials 112 extending along the second direction, a plurality of pillars 113 sequentially provided along the second direction and penetrating the plurality of insulating materials 112 along the third direction, an insulating layer 116 provided on exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 213 to 293 extending along the second direction. The plurality of first conductive materials 213 to 293 between the third doped region 313 and the fourth doped region 314 can be similar to the first conductive materials 211 to 291 between the first doped region 311 and the second doped region 312.

[0084] The drain 320 is provided on the plurality of pillars 113. On the drain 320, a second conductive material 331 to 333 extending along the second direction is provided. The second conductive material 331 to 333 is provided to be spaced apart by a certain distance along the first direction. The second conductive material 331 to 333 is respectively connected to the drain 320 in a corresponding region. The drain 320 and the second conductive material 331 to 333 extending along the second direction can be connected through a contact plug.

[0085] Figure 6 is a memory block according to an exemplary embodiment of the present inventive concept. Figure 5 is an equivalent circuit diagram of a memory block.

[0086] Figure 6 The memory block BLK1 of FIG. 1 can be formed in a three-dimensional structure (or a vertical structure) on a substrate. For example, a plurality of memory cell strings included in the memory block BLK1 can be formed in a direction perpendicular to the substrate.

[0087] Referring to Figure 6 , memory block BLK1 can include memory cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and common source line CSL. Each of memory cell strings NS11 to NS33 can include string select transistor SST, a plurality of memory cells MC1 to MC12, and ground select transistor GST. In Figure 7 , each of memory cell strings NS11 to NS33 is shown to include 12 memory cells MC1 to MC12. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, each of memory cell strings NS11 to NS33 can include any number of memory cells.

[0088] String select transistor SST can be connected to corresponding string select lines SSL1 to SSL3. The plurality of memory cells MC1 to MC12 can be connected to corresponding word lines WL1 to WL12, respectively. Ground select transistor GST can be connected to corresponding ground select lines GSL1 to GSL3. String select transistor SST can be connected to corresponding bit lines BL1, BL2, and BL3, and ground select transistor GST can be connected to common source line CSL.

[0089] In an exemplary embodiment of the inventive concept, a dummy memory cell connected to a dummy word line can be coupled between string select transistor SST and memory cell MC12 and / or coupled between ground select transistor GST and memory cell MC1. For example, the dummy memory cell can be formed substantially simultaneously with normal memory cells using the same process. The dummy memory cell can be activated by the dummy word line, but can not have any "data" stored for reading from an external device. For example, data stored in the dummy memory cell electrically connected to the dummy word line can not be sent to the outside of the memory cell array by a selection signal provided by a column decoder as in the case of normal memory cells. For example, the dummy memory cell electrically connected to the dummy word line can not have any connection to a bit line to send data therebetween as in the case of normal memory cells.

[0090] Word lines having substantially the same height (e.g., WL1) can be commonly connected, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. In Figure 6 , memory block BLK1 is shown to be coupled to twelve word lines WL1 to WL12 and three bit lines BL1 to BL3. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, memory cell array 100 can be coupled to any number of word lines and bit lines.

[0091] According to an exemplary embodiment of the present invention, memory block BLK1 is divided into multiple sub-blocks indicated by representative sub-blocks SB1, SB2, and SB3, each sub-block having a size smaller than that of memory block BLK1. Figure 6 As shown, sub-blocks SB1, SB2, and SB3 can be divided in the word line direction. Alternatively, sub-blocks SB1, SB2, and SB3 can be divided based on bit lines or string select lines. Sub-blocks SB1, SB2, and SB3 in memory block BLK1 can be erased independently, regardless of the reference used to divide memory block BLK1 into sub-blocks.

[0092] Figure 7 Exemplary embodiments of the present invention are shown, wherein the following are formed: Figure 3 The cell region of the memory cell array.

[0093] Reference Figure 7 The unit region CR includes multiple channel holes CH.

[0094] The via size (e.g., via diameter) can vary depending on its location within the cell region CR. For example, a via CH adjacent to the first edge EDG1 and the second edge EDG2 has a low peripheral density and can therefore have a diameter different from that of other via CHs. Memory block BLK1 may be adjacent to the first edge EDG1 and may be spaced apart from the first edge EDG1 by a first distance d11. Memory block BLKb may not be adjacent to the first edge EDG1 and the second edge EDG2 and may be located at the center of the cell region CR, and may be spaced apart from the first edge EDG1 by a second distance d12. The second distance d12 may be greater than the first distance d11. The first diameter DA1 of the first via CHa included in memory block BLK1 (see...) Figure 8A It can be smaller than the second diameter DA2 of the second channel aperture CHb included in the memory block BLKb (see...). Figure 8B ).

[0095] Figure 8A and Figure 8B Exemplary embodiments shown according to the concept of the present invention Figure 7 A cross-section of the memory block string.

[0096] Reference Figure 8A A pillar including a channel layer 114 and an internal material 115 may be formed in a first channel hole CHa included in the memory block BLKa, and a charge storage layer CS may be formed around the first channel hole CHa, and the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure.

[0097] Reference Figure 8BThe pillar including the channel layer 114 and the inner material 115 can be formed in a second channel hole CHb included in the memory block BLKb, and the charge storage layer CS can be formed to surround the second channel hole CHb, and the charge storage layer CS can have an ONO structure.

[0098] In an exemplary embodiment of the inventive concept, the thickness of the charge storage layer CS included in the memory block BLKb can be different from the thickness of the charge storage layer CS included in the memory block BLKa. The characteristics of the memory cells can vary due to the difference in the channel hole diameter. For example, in a 3D memory device having a ring gate structure in which a gate electrode is disposed around the circumference of a channel hole, if the channel hole diameter is reduced, the size of the electric field formed between the gate electrode and the channel layer 114 increases. Thus, the programming and erasing speed of the memory cell having a relatively small channel hole diameter (like the first channel hole CHa) can be higher than the programming and erasing speed of the memory cell having a relatively large channel hole diameter (like the second channel hole CHb).

[0099] Referring back to Figure 7 , the memory blocks are formed in the cell region CR to include all memory cells corresponding to one page in the first direction (e.g., in the word line direction), and to include some strings in the second direction (e.g., in the bit line direction). Thus, the individual memory blocks extend in the first direction, and the channel hole size (e.g., the channel hole diameter) can differ in units of memory blocks. Thus, the programming and erasing speed of the memory cells included in the memory block BLKa can be higher than the programming and erasing speed of the memory cells included in the memory block BLKb.

[0100] Figure 9 is a block diagram of a control circuit in a nonvolatile memory device according to an exemplary embodiment of the inventive concept. Figure 3

[0101] Referring to Figure 9 , the control circuit 500 can include a command decoder 510, an address buffer 530, and a control signal generator 540.

[0102] The command decoder 510 decodes the command CMD and provides the decoded command D_CMD to the control signal generator 540. The address buffer 530 receives the address signal ADDR, provides a row address R_ADDR to the address decoder 600, and provides a column address C_ADDR to the data input / output circuit 420.

[0103] ​The control signal generator 540 receives the decoded command D_CMD, generates a control signal CTLs, a meta signal MTS, and a control signal PCTL based on an operation indicated by the decoded command D_CMD, provides the control signal CTLs to the voltage generator 700, provides the control signal PCTL to the page buffer circuit 410, and provides the meta signal MTS to the address decoder 600. The decoded command D_CMD can include meta information associated with a property of the data DATA, and the meta signal MTS can include the meta information. The memory controller 40 can incorporate the meta information into the command CMD based on an access frequency of the data DATA. The data DATA can be divided into cold data and hot data. The hot data is accessed at a first frequency greater than a reference frequency during a reference time interval, and the cold data is accessed at a second frequency less than or equal to the reference frequency during the reference time interval.

[0104] Figure 10 is a block diagram of a voltage generator in a non-volatile memory device according to an example embodiment of the inventive concept. Figure 3

[0105] Referring to Figure 10 , the voltage generator 700 can include a high voltage (HV) generator 710 and a low voltage (LV) generator 730. The voltage generator 700 can further include a negative voltage (NV) generator 750.

[0106] The high voltage generator 710 can generate a program voltage VPGM, a program pass voltage VPPASS, a verify pass voltage VVPASS, and a read pass voltage VRPASS according to an operation indicated by the command CMD in response to a first control signal CTL1 in the control signal CTLs. The program voltage VPGM is applied to a selected word line, and the program pass voltage VPPASS, the verify pass voltage VVPASS, and the read pass voltage VRPASS can be applied to an unselected word line. The first control signal CTL1 can include a plurality of bits indicating the operation indicated by the command CMD.

[0107] The low voltage generator 730 can generate a program verify voltage VPV, a read voltage VRD, and an erase verify voltage VEV according to the operation indicated by the command CMD in response to a second control signal CTL2 in the control signal CTLs. The program verify voltage VPV, the read voltage VRD, and the erase verify voltage VEV can be applied to a selected word line according to an operation of the non-volatile memory device 50. The second control signal CTL2 can include a plurality of bits indicating the operation indicated by the command CMD.

[0108] ​The negative voltage generator 750 can generate the program verify voltage VPV', the read voltage VRD', and the erase verify voltage VEV' having a negative level according to an operation indicated by the command CMD in response to a third control signal CTL3 among the control signals CTLs. The third control signal CTL3 can include a plurality of bits indicating the operation indicated by the command CMD.

[0109] Figure 11 is a plan view showing an upper surface of a second semiconductor layer in Figure 4

[0110] Referring to Figure 3 , Figure 4 and Figure 11 , the second semiconductor layer L2 can be divided into the first to fourth regions R1 to R4 by a first virtual line X0-X0' in a first direction substantially parallel to the word line WL and a second virtual line Y0-Y0' in a second direction substantially parallel to the bit line BL. In other words, the first to fourth regions R1 to R4 are divided along the first and second directions which intersect at a point at which the memory cell array 100 is stacked in the third direction.

[0111] The first pad MT1 can be disposed at an upper portion of the first region R1, the second pad MT2 can be disposed at an upper portion of the second region R2, the third pad MT3 can be disposed at an upper portion of the third region R3, and the fourth pad MT4 can be disposed at an upper portion of the fourth region R4.

[0112] The first address decoder (RD1) 601 and the first page buffer circuit (PB1) 411 can be disposed in the first region R1 and can be electrically connected to the first pad MT1. The second address decoder (RD2) 603 and the second page buffer circuit (PB2) 413 can be disposed in the second region R2 and can be electrically connected to the second pad MT2. The third address decoder (RD3) 605 and the third page buffer circuit (PB3) 415 can be disposed in the third region R3 and can be electrically connected to the third pad MT3. The fourth address decoder (RD4) 607 and the fourth page buffer circuit (PB4) 417 can be disposed in the fourth region R4 and can be electrically connected to the fourth pad MT4. In Figure 11 , one address decoder and one page buffer circuit are shown as being disposed in each of the first to fourth regions R1 to R4, but the present inventive concept is not limited thereto. In exemplary embodiments of the present inventive concept, a plurality of address decoders and a plurality of page buffer circuits can be disposed in each of the first to fourth regions R1 to R4.

[0113] ​A control circuit (CCT) 500 can be disposed in a specific region of the second semiconductor layer L2. The control circuit 500 can be connected to the first, second, third, and fourth address decoders 601, 603, 605, and 607 and the first, second, third, and fourth page buffer circuits 411, 413, 415, and 417. In Figure 11 In the above-described exemplary embodiment, the control circuit 500 is disposed in a central region of the second semiconductor layer L2, but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the control circuit 500 can be disposed in at least one of the first to fourth regions R1 to R4.

[0114] Figure 12 is a plan view illustrating an upper surface of the second semiconductor layer in Figure 4 according to an exemplary embodiment of the inventive concept.

[0115] Referring to Figure 3 , Figure 4 and Figure 12 , the second semiconductor layer L2a can be divided into the first to fourth regions R1 to R4 by a first virtual line X0-X0' in a first direction substantially parallel to the word line WL and a second virtual line Y0-Y0' in a second direction substantially parallel to the bit line BL.

[0116] Figure 12 is different from Figure 11 in that each of the first, second, third, and fourth address decoders 601, 603, 605, and 607 and each of the first, second, third, and fourth page buffer circuits 411, 413, 415, and 417 is disposed adjacent to an edge portion of a corresponding one of the first to fourth regions R1 to R4.

[0117] Figure 13 is a view illustrating the first semiconductor layer in Figure 4 according to an exemplary embodiment of the inventive concept.

[0118] Referring to Figure 3 , Figure 4 and Figure 13 , the first semiconductor layer L1 can include a cell region CR and a pad region PRG adjacent to each other in a first direction.

[0119] Figure 3 The memory cell array 100 in

[0120] The pad area can include a plurality of input / output (I / O) pads DP1~DPr and at least one power pad (e.g., power pads 761 and 763). A ground voltage GND can be supplied to the pads MT1, MT2, MT3, and MT4 through the power pad 761, and a power voltage EVC can be supplied to the pads MT1, MT2, MT3, and MT4 through the power pad 763. The plurality of I / O pads DP1~DPr can be disposed between the first edge portion EG11 and the second edge portion EG12 of the pad area PRG in the second direction, and the power pads 761 and 763 can be disposed adjacent to the first edge portion EG11.

[0121] Figure 14 FIG. 1 illustrates a first pad in a memory device according to an example embodiment of the present inventive concept. Figure 13

[0122] Referring to Figure 13 and Figure 14 , the first pad MT1 can be located on the first semiconductor layer L1, and the first pad MT1 can include a first vertical structure VS1 and a second vertical structure VS2. As shown in Figure 14 , the first pad MT1 can include a plurality of memory blocks BLKa~BLKq formed as the first vertical structure VS1 and the second vertical structure VS2. The memory blocks BLK1~BLKq can be arranged in the second direction. Each of the memory blocks BLKa~BLKq can include a first sub-block and a second sub-block. The memory block BLKa includes a first sub-block SBa1 and a second sub-block SBa2. The memory block BLKi includes a first sub-block SBi1 and a second sub-block SBi2. The memory block BLKq includes a first sub-block SBq1 and a second sub-block SBq2.

[0123] As shown in Figure 14 , the first vertical structure VS1 can include a plurality of first sub-blocks of the memory blocks BLKa~BLKq and a plurality of first via areas EVA11, VA11, VA12, and EVA12 spaced apart in the second direction. Also, the second vertical structure VS2 can include a plurality of second sub-blocks of the memory blocks BLKa~BLKq and a plurality of second via areas EVA21, VA21, VA22, and EVA22 spaced apart in the second direction. The first sub-blocks can be arranged between the first via areas EVA11, VA11, VA12, and EVA12, and the second sub-blocks can be arranged between the second via areas EVA21, VA21, VA22, and EVA22.

[0124] ​The first via regions EVA11 and EVA12 adjacent to edges of the first sub-block in the second direction can be referred to as a first edge via region and a second edge via region, respectively. The first via regions EVA21 and EVA22 adjacent to edges of the second sub-block in the second direction can be referred to as a third edge via region and a fourth edge via region, respectively.

[0125] For example, in the first via regions VA11 and VA12, one or more first via-through-holes each passing through the first vertical structure VS1 and connected to the first page buffer circuit 411 can be formed. Also, in the second via regions VA21 and VA22, one or more second via-through-holes each passing through the second vertical structure VS22 and connected to the second page buffer circuit 413 can be formed.

[0126] For example, in the first edge via region EVA11 and the second edge via region EVA12, one or more edge via-through-holes each passing through the first vertical structure VS1 and connected to the first address decoder 601 can be formed. Also, in the third edge via region EVA21 and the fourth edge via region EVA22, one or more edge via-through-holes each passing through the second vertical structure VS22 and connected to the second address decoder 603 can be formed.

[0127] Figure 15 is a cross-sectional view taken along a line VI-VI' of an exemplary embodiment according to the inventive concept. Figure 14 is a cross-sectional view taken along a line VI-VI' of an exemplary embodiment according to the inventive concept. Figure 15 is a cross-sectional view taken along a line VI-VI' of an exemplary embodiment according to the inventive concept. Figure 14 is a cross-sectional view taken along a line VI-VI' of an exemplary embodiment according to the inventive concept.

[0128] Referring to Figure 15 The second semiconductor layer L2 can include a lower substrate L_SUB and the second address decoder 603 and the second page buffer circuit 413 formed on the lower substrate L_SUB. Also, the second semiconductor layer L2 can include a plurality of first lower contacts LMC1 electrically connected to the second address decoder 603, a first lower wire PM1 electrically connected to the plurality of first lower contacts LMC1, and a lower insulating layer IL1 covering the plurality of first lower contacts LMC1 and the first lower wire PM1.

[0129] The second address decoder 603 and the second page buffer circuit 413 can be formed on some portions of the lower substrate L_SUB. In other words, the second address decoder 603 and / or the second page buffer circuit 413 can be formed by forming a plurality of transistors TR on the lower substrate L_SUB.

[0130] The first semiconductor layer L1 can include a first upper substrate U_SUB_1, a second upper substrate U_SUB_2, a first vertical structure VS1 on the first upper substrate U_SUB_1, and a second vertical structure VS2 on the second upper substrate U_SUB_2. In addition, the first semiconductor layer L1 can include a plurality of first upper contact members UMC1 electrically connected to the first vertical structure VS1, a plurality of first bit lines BL_1, a plurality of first edge contact members EC1, and a plurality of first upper conductive lines UPM1. In addition, the first semiconductor layer L1 can include a plurality of second upper contact members UMC2 electrically connected to the second vertical structure VS2, a plurality of second bit lines BL_2, a plurality of second edge contact members EC2, and a plurality of second upper conductive lines UPM2. In addition, the first semiconductor layer L1 can include an upper insulating layer IL2 covering the first and second vertical structures VS1 and VS2 and the various conductive lines.

[0131] The first and second upper substrates U_SUB_1 and U_SUB_2 can be support layers that respectively support the first and second gate conductive layers GS_1 and GS_2. The first and second upper substrates U_SUB_1 and U_SUB_2 can be, for example, base substrates.

[0132] The first vertical structure VS1 can include the first gate conductive layer GS_1 on the first upper substrate U_SUB_1 and a plurality of pillars P1 that pass through the first gate conductive layer GS_1 and extend in the third direction on a top surface of the first upper substrate U_SUB_1. The first gate conductive layer GS_1 can include a ground select line GSL_1, word lines WL1_1 to WL4_1, and a string select line SSL_1. The ground select line GSL_1, the word lines WL1_1 to WL4_1, and the string select line SSL_1 can be sequentially formed on the first upper substrate U_SUB_1, and an insulating layer 52 can be located below or above each first gate conductive layer GS_1.

[0133] Each of the plurality of pillars P1 can include a surface layer S1 and an interior I1. For example, the surface layer S1 of each pillar P1 can include a silicon material doped with impurities or a silicon material that is not doped with impurities.

[0134] For example, the ground select line GSL_1 and portions of the surface layer S1 adjacent to the ground select line GSL_1 can constitute a ground select transistor GST (see Figure 6 ). In addition, the word lines WL1_1 to WL4_1 and portions of the surface layer S1 adjacent to the word lines WL1_1 to WL4_1 can constitute memory cells MC1 to MC8 (see Figure 6 ). In addition, the string select line SSL_1 and portions of the surface layer S1 adjacent to the string select line SSL_1 can constitute a string select transistor SST (see Figure 6 ).

[0135] A drain region DR1 can be formed on the pillar P1. For example, the drain region DR1 can include a silicon material doped with impurities. An etch stop film 53 can be formed on sidewalls of the drain region DR1.

[0136] The first vertical structure VS1 can include an edge region EG1. As shown in FIG. 6A, a cross-section of the edge region EG1 can form a landing pad structure. The landing pad structure can be referred to as a "word line pad". A plurality of first edge contacts EC1 can be connected to the edge region EG1, and an electrical signal can be applied from a peripheral circuit such as the second address decoder 603 through the first edge contacts EC1. For example, a contact plug MCP1 passing through the first vertical structure VS1, the first upper substrate U_SUB_1, and a portion of the second semiconductor layer L2 can have one side connected to the first lower wire PM1 and the other side electrically connected to the edge region EG1 through the first upper wire UPM1. The contact plug MCP1 can include an insulating film pattern IP1 and a conductive pattern MP1. Figure 15 At least some of the first edge contacts EC1 can pass through some portions of the first semiconductor layer L1 and the second semiconductor layer L2 in the third direction between the first upper substrate U_SUB_1 and the second upper substrate U_SUB_2, and can have one side electrically connected to a contact plug (e.g., MCP1) connected with a lower wire (e.g., PM1).

[0137] Since the first vertical structure VS1 and the second vertical structure VS2 have corresponding configurations in a cross-sectional view taken along the line VI-VI' of the first memory block BLK1 of FIG. 6A, a repeated explanation of elements of the second vertical structure VS2 corresponding to elements of the first vertical structure VS1 can not be given.

[0138] Figure 14 The second vertical structure VS2 can include a plurality of pillars P2 passing through the second gate conductive layer GS_2. Each pillar P2 can include a surface layer S2 and an interior I2. The second gate conductive layer GS_2 can include a ground select line GSL_2, word lines WL1_2 to WL4_2, and a string select line SSL_2. An insulating layer 62 can be located below or above each second gate conductive layer GS_2.

[0139] A drain region DR2 can be formed on the pillar P2. An etch stop film 63 can be formed on sidewalls of the drain region DR2. The second vertical structure VS2 can include an edge region EG2. A contact plug MCP2 passing through the second vertical structure VS2, the second upper substrate U_SUB_2, and a portion of the second semiconductor layer L2 can have one side connected to the first lower wire PM1 and the other side electrically connected to the edge region EG2 through the second upper wire UPM2. The contact plug MCP2 can include an insulating film pattern IP2 and a conductive pattern MP2.

[0140] A drain region DR2 can be formed on the pillar P2. An etch stop film 63 can be formed on sidewalls of the drain region DR2. The second vertical structure VS2 can include an edge region EG2. A contact plug MCP2 passing through the second vertical structure VS2, the second upper substrate U_SUB_2, and a portion of the second semiconductor layer L2 can have one side connected to the first lower wire PM1 and the other side electrically connected to the edge region EG2 through the second upper wire UPM2. The contact plug MCP2 can include an insulating film pattern IP2 and a conductive pattern MP2.​

[0141] Figure 16 is a cross-sectional view taken along a line VII-VII' of a configuration of a first semiconductor layer and a second semiconductor layer according to an example embodiment of the inventive concept. For example, Figure 14 may be a cross-sectional view illustrating the second semiconductor layer L2 overlapping with the via areas VA11 and VA21 provided in the first semiconductor layer L1. Figure 16 may not give a repeated explanation of the same elements in Figure 16 Figure 15

[0142] Referring to Figure 16 , a plurality of through-hole vias THV1 passing through the first vertical structure VS1, the first upper substrate U_SUB_1, and a portion of the second semiconductor layer L2 can be formed in the first via area VA11. Each of the through-hole vias THV1 can include an insulating film pattern IP4 and a conductive pattern MP4. A plurality of through-hole vias THV2 passing through the second vertical structure VS2, the second upper substrate U_SUB_2, and a portion of the second semiconductor layer L2 can be formed in the second via area VA21. Each of the through-hole vias THV2 can include an insulating film pattern IP3 and a conductive pattern MP3.

[0143] As shown in Figure 16 , each of the through-hole vias THV2 can electrically connect the second page buffer circuit 413 and the second upper contact UMC2, and each of the through-hole vias THV2 can electrically connect the second page buffer circuit 413 and the first upper contact UMC1. The first upper contact UMC1 can be connected to the first bit line BL_1, and the second upper contact UMC2 can be connected to the second bit line BL_2. In other words, the first bit line BL_1 can be electrically connected to the second page buffer circuit 413 formed on the second semiconductor layer L2 through the plurality of through-hole vias THV1 formed in the first via area VA11, and the second bit line BL_2 can be electrically connected to the second page buffer circuit 413 formed on the second semiconductor layer L2 through the plurality of through-hole vias THV2 formed in the second via area VA21. In an example embodiment of the inventive concept, a conductive pattern such as a contact can not be formed in an edge region EG_V1 of the first via area VA11 and an edge region EG_V2 of the second via area VA21.

[0144] In an example embodiment of the inventive concept, in Figures 14 to 16 , the first upper substrate U_SUB_1 and the second upper substrate U_SUB_2 can be connected to each other to form an upper substrate, and the first vertical structure VS1 and the second vertical structure VS2 can be connected to each other to form a vertical structure.

[0145] Figure 17 ​​A cross-sectional view taken along the line VIII-VIII' of FIG. 8A is shown according to an exemplary embodiment of the inventive concept. Figure 13 Examples in which the plurality of pads in the cell region CR include different numbers of via regions are shown.

[0146] Referring to FIG. 8A, Figure 17 The cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT11, MT12, MT13, and MT14. The first pad MT11 and the second pad MT12 can include different numbers of via regions according to a distance from the pad region PRG in the first direction. The third pad MT13 and the fourth pad MT14 can include different numbers of via regions according to a distance from the pad region PRG in the first direction.

[0147] A first distance from the pad region PRG to the first pad MT11 in the first direction is less than the reference distance d1, and the first pad MT11 includes a first number of via regions VA11a and VA11b. A second distance from the pad region PRG to the second pad MT12 in the first direction is greater than or equal to the reference distance d1, and the second pad MT12 includes a second number of via regions VA12a, VA12b, VA12c, and VA12d.

[0148] A first distance from the pad region PRG to the third pad MT13 in the first direction is less than the reference distance d1, and the third pad MT13 includes a first number of via regions VA13a and VA13b. A second distance from the pad region PRG to the fourth pad MT14 in the first direction is greater than or equal to the reference distance d1, and the fourth pad MT14 includes a second number of via regions VA14a, VA14b, VA14c, and VA14d.

[0149] Here, the first number can be less than the second number. The number of via regions included in each of the first pad MT11, the second pad MT12, the third pad MT13, and the fourth pad MT14 can be determined based on a power requirement and a signal routing of each of the first pad MT11, the second pad MT12, the third pad MT13, and the fourth pad MT14, or can be determined based on a voltage drop of a power supply line due to resistance with respect to the pad region PRG.

[0150] Figure 18 A cross-sectional view taken along the line VIII-VIII' of FIG. 8A is shown according to an exemplary embodiment of the inventive concept. Figure 17 A cross-sectional view taken along the line VIII-VIII' of FIG. 8A is shown according to an exemplary embodiment of the inventive concept. Figure 18 A configuration of the first semiconductor layer and the second semiconductor layer is shown.

[0151] Referring to FIG. 8A, Figure 18The metal region UMR is provided in the first semiconductor layer L1, and the pad region PRG and the power / signal delivery region PW / SG are provided above the metal region UMR. In addition, different numbers of the through-hole vias THVa to THVf are provided in the first semiconductor layer L1 and the second semiconductor layer L2 with respect to the pad boundary MTBR according to a distance from the pad region PRG in the first direction.

[0152] The through-hole via THVa is connected to the lower wire PM4. The through-hole via THVb is connected to the second address decoder 603 through the lower wire PM51 and the lower contact LMC31, and the through-hole via THVc is connected to the second address decoder 603 through the lower wire PM52 and the lower contact LMC32. The through-hole via THVd is connected to the lower wire PM53. The through-hole via THVe is connected to the lower wire PM54, and the through-hole via THVf is connected to the second page buffer circuit 413 through the lower wire PM55 and the lower contact LMC2. The through-hole via THVf can include the insulating film pattern IP3 and the conductive pattern MP3.

[0153] Figure 19 An example in which a plurality of pads in a cell region CR according to an exemplary embodiment of the present inventive concept is illustrated. Figure 13

[0154] Referring to FIG. 1, a plurality of pads MT21, MT22, MT23, and MT24 in a cell region CR adjacent to a pad region PRG in a first direction can include different numbers of via regions. Figure 19 In the first direction, a first distance from the pad region PRG to a first pad MT21 is less than a reference distance d1, and the first pad MT21 includes a first number of via regions VA21a, VA21b, VA21c, and VA21d. In the first direction, a second distance from the pad region PRG to a second pad MT22 is greater than or equal to the reference distance d1, and the second pad MT22 includes a second number of via regions VA22a and VA22b.

[0155] In the first direction, a first distance from the pad region PRG to a first pad MT21 is less than a reference distance d1, and the first pad MT21 includes a first number of via regions VA21a, VA21b, VA21c, and VA21d. In the first direction, a second distance from the pad region PRG to a second pad MT22 is greater than or equal to the reference distance d1, and the second pad MT22 includes a second number of via regions VA22a and VA22b.

[0156] ​A first distance from the pad region PRG to the third pad MT23 in the first direction is less than the reference distance d1, and the third pad MT23 includes a first number of via regions VA23a, VA23b, VA23c, and VA24d. A second distance from the pad region PRG to the fourth pad MT24 in the first direction is greater than or equal to the reference distance d1, and the fourth pad MT24 includes a second number of via regions VA24a and VA24b.

[0157] Here, the first number can be greater than the second number. Based on a frequency of access of data, Figure 3 The control circuit 500 in the memory device 1000 can store hot data in at least one of the first pad MT21 and the third pad MT23, and can store cold data in at least one of the second pad MT22 and the fourth pad MT24. The hot data is accessed at a first frequency greater than a reference frequency during a reference time interval, and the cold data is accessed at a second frequency less than or equal to the reference frequency during the reference time interval.

[0158] Figure 20 An example in which a plurality of pads includes different numbers of via regions according to an exemplary embodiment of the present inventive concept is illustrated. Figure 13 An example in which a plurality of pads includes different numbers of via regions according to an exemplary embodiment of the present inventive concept is illustrated.

[0159] Referring to Figure 20 , a cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT31, MT32, MT33, and MT34. The first pad MT31 includes a first tile TL11 and a second tile TL12 identified according to a distance from the pad region PRG in the first direction. The second pad MT32 includes a first tile TL21 and a second tile TL22 identified according to a distance from the pad region PRG in the first direction. The third pad MT33 includes a first tile TL31 and a second tile TL32 identified according to a distance from the pad region PRG in the first direction. The fourth pad MT34 includes a first tile TL41 and a second tile TL42 identified according to a distance from the pad region PRG in the first direction. Each of the first tiles TL11, TL21, TL31, and TL41 and each of the second tiles TL12, TL22, TL32, and TL42 can include different numbers of via regions according to a distance from the pad region PRG in the first direction.

[0160] For example, in the first direction, the first distance from the pad region PRG to the first panel TL11 is less than the reference distance d2, and the first panel TL11 includes a first number of via regions VA31a and VA31b. In the first direction, the second distance from the pad region PRG to the second panel TL12 is greater than or equal to the reference distance d2, and the second panel TL12 includes a second number of via regions VA32a, VA32b, VA32c, and VA32d.

[0161] Here, the first quantity may be less than the second quantity. The number of via regions included in each of the first panel TL11 and the second panel TL12 may be determined based on the power requirements and signal routing of each of the first panel TL11 and the second panel TL12, or may be determined based on the voltage drop of the power line due to the resistance of the PRG relative to the pad area.

[0162] Figure 21 An exemplary embodiment of the invention is shown in which... Figure 13 Examples of multiple pads in the image include varying numbers of through-hole areas.

[0163] Reference Figure 21 The cell region CR adjacent to the pad region PRG in the first direction includes multiple pads MT31a, MT32a, MT33a, and MT34a. The first pad MT31a includes a first panel TL11a and a second panel TL12a identified according to their distance from the pad region PRG in the first direction. The second pad MT32a includes a first panel TL21a and a second panel TL22a identified according to their distance from the pad region PRG in the first direction. The third pad MT33a includes a first panel TL31a and a second panel TL32a identified according to their distance from the pad region PRG in the first direction. The fourth pad MT34a includes a first panel TL41a and a second panel TL42a identified according to their distance from the pad region PRG in the first direction. Each of the first panels TL11a, TL21a, TL31a and TL41a and each of the second panels TL12a, TL22a, TL32a and TL42a may include a different number of via regions depending on the distance from the pad region PRG in the first direction.

[0164] For example, in the first direction, the first distance from the pad region PRG to the first panel TL11a is less than the reference distance d2, and the first panel TL11a includes a first number of via regions VA33a, VA33b, VA33c, and VA33d. In the first direction, the second distance from the pad region PRG to the second panel TL12a is greater than or equal to the reference distance d2, and the second panel TL12a includes a second number of via regions VA34a and VA34b.

[0165] Here, the first number can be greater than the second number. Figure 3 The control circuit 500 in the memory device 1000 can store hot data in the first tile TL11a and can store cold data in the second tile TL12a.

[0166] Figure 22 shows a memory device according to an exemplary embodiment of the present inventive concept Figure 13 Examples in which the plurality of pads in the memory device include different numbers of via regions.

[0167] Referring to Figure 22 The cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT41, MT42, MT43, and MT44. The pad region PRG includes power supply pads 761 and 763 disposed adjacent to the first edge portion EG11. A ground voltage GND can be supplied to the pads MT41, MT42, MT43, and MT44 through the power supply pad 761, and a power supply voltage EVC can be supplied to the pads MT41, MT42, MT43, and MT44 through the power supply pad 763.

[0168] The first pad MT41 and the third pad MT43 can include different numbers of via regions according to a distance from the power supply pad 763 in the second direction. The second pad MT42 and the fourth pad MT44 can include different numbers of via regions according to a distance from the power supply pad 763 in the second direction.

[0169] A first distance from the power supply pad 763 or the first edge portion EG11 to the third pad MT43 in the second direction is less than the reference distance d3, and the third pad MT43 includes a first number of via regions VA43a and VA43b. A second distance from the power supply pad 763 or the first edge portion EG11 to the first pad MT41 in the second direction is greater than or equal to the reference distance d3, and the first pad MT41 includes a second number of via regions VA41a, VA41b, VA41c, and VA41d.

[0170] A first distance from the power supply pad 763 or the first edge portion EG11 to the fourth pad MT44 in the second direction is less than the reference distance d3, and the fourth pad MT44 includes a first number of via regions VA44a and VA44b. A second distance from the power supply pad 763 or the first edge portion EG11 to the second pad MT42 in the second direction is greater than or equal to the reference distance d3, and the second pad MT42 includes a second number of via regions VA42a, VA42b, VA42c, and VA42d. Here, the first number can be less than the second number.

[0171] Figure 23 shows a memory device according to an exemplary embodiment of the present inventive conceptFigure 13 Examples in which the plurality of pads include different numbers of via regions.

[0172] Referring to Figure 23 The cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT51, MT52, MT53, and MT54. The pad region PRG includes power supply pads 761 and 763 disposed adjacent to the first edge portion EG11. A ground voltage GND can be supplied to the pads MT51, MT52, MT53, and MT54 through the power supply pad 761, and a power supply voltage EVC can be supplied to the pads MT51, MT52, MT53, and MT54 through the power supply pad 763.

[0173] The first pad MT51 and the third pad MT53 can include different numbers of via regions according to a distance from the power supply pad 763 in the second direction. The second pad MT52 and the fourth pad MT54 can include different numbers of via regions according to a distance from the power supply pad 763 in the second direction.

[0174] A first distance from the power supply pad 763 or the first edge portion EG11 to the third pad MT53 in the second direction is less than the reference distance d3, and the third pad MT53 includes a first number of via regions VA53a, VA53b, VA53c, and VA53d. A second distance from the power supply pad 763 or the first edge portion EG11 to the first pad MT51 in the second direction is greater than or equal to the reference distance d3, and the first pad MT51 includes a second number of via regions VA51a and VA51b.

[0175] A first distance from the power supply pad 763 or the first edge portion EG11 to the fourth pad MT54 in the second direction is less than the reference distance d3, and the fourth pad MT54 includes a first number of via regions VA54a, VA54b, VA54c, and VA54d. A second distance from the power supply pad 763 or the first edge portion EG11 to the second pad MT52 in the second direction is greater than or equal to the reference distance d3, and the second pad MT52 includes a second number of via regions VA52a and VA52b. Here, the first number can be greater than the second number.

[0176] Figure 3 The control circuit 500 in the memory device 700 can store hot data in the pad MT53 or the pad MT54, and can store cold data in the pad MT51 or the pad MT52.

[0177] Figure 24 Examples in which the plurality of pads include different numbers of via regions. Figure 13 Examples in which the plurality of pads include different numbers of via regions.

[0178] Referring to Figure 24The cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT61, MT62, MT63, and MT64. The pad region PRG includes power supply pads 761 and 763 disposed adjacent to the first edge portion EG11. A ground voltage GND can be supplied to the pads MT61, MT62, MT63, and MT64 through the power supply pad 761, and a power supply voltage EVC can be supplied to the pads MT61, MT62, MT63, and MT64 through the power supply pad 763.

[0179] The pad MT61 includes a first tile TL51 and a second tile TL52, the pad MT62 includes a first tile TL61 and a second tile TL62, the pad MT63 includes a first tile TL71 and a second tile TL72, and the pad MT64 includes a first tile TL81 and a second tile TL82. The pad MT63 includes the first tile TL71 and the second tile TL72 identified according to a distance from the power supply pad 763 or the first edge portion EG11 in the second direction, and the pad MT64 includes the first tile TL81 and the second tile TL82 identified according to a distance from the power supply pad 763 or the first edge portion EG11 in the second direction.

[0180] A first distance from the power supply pad 763 or the first edge portion EG11 to the second tile TL72 is smaller than a first reference distance d41, and the second tile TL72 includes a first number of via regions VA81a and VA81b. The second tile TL82 can also include the first number of via regions. A second distance from the power supply pad 763 or the first edge portion EG11 to the first tile TL71 is greater than or equal to the first reference distance d41 and smaller than a second reference distance d42, and the first tile TL71 includes a second number of via regions VA71a, VA71b, and VA71c. The first tile TL81 can also include the second number of via regions.

[0181] A third distance from the power supply pad 763 or the first edge portion EG11 to the first tile TL51 is greater than or equal to the second reference distance d42, and the first tile TL51 includes a third number of via regions VA61a, VA61b, VA61c, and VA61d. A fourth distance from the power supply pad 763 or the first edge portion EG11 to the second tile TL52 is greater than or equal to the second reference distance d42, and the second tile TL52 also includes the third number of via regions. The first tile TL61 and the second tile TL62 can also each include the third number of via regions. Here, the second number is greater than the first number, and the third number is greater than the second number.

[0182] Figure 25 An exemplary embodiment according to the inventive concept is illustrated in which Figure 13Examples of the plurality of pads in the cell region CR including different numbers of via regions.

[0183] Referring to Figure 25 The cell region CR adjacent to the pad region PRG in the first direction includes a plurality of pads MT61a, MT62a, MT63a, and MT64a. The pad region PRG includes power supply pads 761 and 763 disposed adjacent to the first edge portion EG11. A ground voltage GND can be supplied to the pads MT61a, MT62a, MT63a, and MT64a through the power supply pad 761, and a power supply voltage EVC can be supplied to the pads MT61a, MT62a, MT63a, and MT64a through the power supply pad 763.

[0184] The pad MT61a includes a first tile TL51a and a second tile TL52a, the pad MT62a includes a first tile TL61a and a second tile TL62a, the pad MT63a includes a first tile TL71a and a second tile TL72a, and the pad MT64a includes a first tile TL81a and a second tile TL82a. The pad MT63a includes the first tile TL71a and the second tile TL72a identified according to a distance from the power supply pad 763 or the first edge portion EG11 in the second direction, and the pad MT64a includes the first tile TL81a and the second tile TL82a identified according to a distance from the power supply pad 763 or the first edge portion EG11 in the second direction.

[0185] A first distance from the power supply pad 763 or the first edge portion EG11 to the second tile TL72a is less than a first reference distance d41, and the second tile TL72a includes a first number of via regions VA82a, VA82b, VA82c, and VA82d. The second tile TL82a can also include the first number of via regions. A second distance from the power supply pad 763 or the first edge portion EG11 to the first tile TL71a is greater than or equal to the first reference distance d41 and less than a second reference distance d42, and the first tile TL71a includes a second number of via regions VA72a, VA72b, and VA72c. The first tile TL81a can also include the second number of via regions.

[0186] The third distance from the power pad 763 or the first edge portion EG11 to the first panel TL51a is greater than or equal to the second reference distance d42, and the first panel TL51a includes a third number of via regions VA62a and VA62b. The fourth distance from the power pad 763 or the first edge portion EG11 to the second panel TL52a is greater than or equal to the second reference distance d42, and the second panel TL52a also includes a third number of via regions. Additionally, the first panel TL61a and the second panel TL62a may each include a third number of via regions. Here, the first number is greater than the second number, and the second number is greater than the third number.

[0187] Figure 3 The control circuit 500 can store hot data in the modules TL72a and TL82a, and can store cold data in the pads MT61a and MT62a.

[0188] Figure 26 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 3 A block diagram of an address decoder in a non-volatile memory device.

[0189] exist Figure 26 The image also shows a first pad MT1 and a second pad MT2 of the memory cell array 100, as well as a voltage generator 700.

[0190] Reference Figure 26 The address decoder 600 includes a decoder 610, a first switching circuit 620, and a second switching circuit 630. The first switching circuit 620 may be included in... Figure 11 In the first address decoder 601, the second switch circuit 630 may be included in Figure 11 In the second address decoder 603.

[0191] Decoder 610 receives address ADDR and metadata signal MTS, and generates a first pad selection signal MSS1 for selecting the first pad MT1 and a second pad selection signal MSS2 for selecting the second pad MT2 based on at least one pad specified by address ADDR and metadata signal MTS. Decoder 610 provides the first pad selection signal MSS1 and the second pad selection signal MSS2 to the first switching circuit 620 and the second switching circuit 630, respectively.

[0192] The first and second switch circuits 620 and 630 can be coupled to a plurality of selection lines Sls coupled to the voltage generator 700. The first switch circuit 620 is coupled to the first pad MT1 through at least one string selection line SSL, a plurality of word lines WL1-WLn, and at least one ground selection line GSL. The second switch circuit 630 is coupled to the second pad MT2 through at least one string selection line SSL, a plurality of word lines WL1-WLn, and at least one ground selection line GSL.

[0193] The first switch circuit 620 includes a switch controller 621 and a plurality of pass transistors PT11-PT14 coupled to the string selection line SSL, the word lines WL1-WLn, and the ground selection line GSL of the first pad MT1. The switch controller 621 can control the on and off of the pass transistors PT11-PT14 and the timing of the on of the pass transistors PT11-PT14 in response to a first pad selection signal MSS1 via a signal SCS1.

[0194] The second switch circuit 630 includes a switch controller 631 and a plurality of pass transistors PT21-PT24 coupled to the string selection line SSL, the word lines WL1-WLn, and the ground selection line GSL of the second pad MT2. The switch controller 631 can control the on and off of the pass transistors PT21-PT24 in response to a second pad selection signal MSS2 via a signal SCS2.

[0195] Figure 27 is a block diagram illustrating a solid state disk or drive (SSD) including a nonvolatile memory device according to an example embodiment of the present inventive concept.

[0196] Referring to Figure 27 The SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200.

[0197] The SSD controller 1200 can be connected to the nonvolatile memory devices 1100 through a plurality of channels CH1, CH2, CH3, …, CHi. The SSD controller 1200 can include one or more processors 1210, a buffer memory 1220, an error correction code (ECC) circuit 1230, a host interface 1250, and a nonvolatile memory interface 1260.

[0198] The buffer memory 1220 can store data for driving the SSD controller 1200. The buffer memory 1220 can include a plurality of memory lines each storing data or commands. The ECC circuit 1230 can calculate error correction code values of data to be programmed during a program operation, and can use the error correction code values to correct errors of read data during a read operation. In a data recovery operation, the ECC circuit 1230 can correct errors of data recovered from the nonvolatile memory device 1100. The host interface 1250 can provide an interface with an external device. The nonvolatile memory interface 1260 can provide an interface with the nonvolatile memory device 1100.

[0199] Each nonvolatile memory device 1100 can be a nonvolatile memory device according to the exemplary embodiments of the inventive concept described above, and can optionally be supplied with an external high voltage VPP.

[0200] The nonvolatile memory device or storage device according to the exemplary embodiments of the inventive concept can be packaged using various package types or package configurations.

[0201] The inventive concept can be applied to various electronic devices including a nonvolatile memory device.

[0202] Accordingly, a nonvolatile memory device having a cell-on-periphery (COP) structure can include a plurality of pads / tiles including a plurality of via regions in which through-hole vias are disposed, and the through-hole vias transmit signals / power to the plurality of pads / tiles. At least some of the pads / tiles include different numbers of via regions according to a distance from a pad region or a power pad. Accordingly, the nonvolatile memory device can have enhanced performance without increasing a chip size.

[0203] Although the inventive concept has been shown and described with respect to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various modifications can be made to the inventive concept without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A nonvolatile memory device comprising: a first semiconductor layer including an upper substrate in which a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction are disposed, and an array of memory cells including vertical structures on the upper substrate, wherein the vertical structures include a plurality of memory blocks; a second semiconductor layer below the first semiconductor layer in a third direction perpendicular to the first and second directions, wherein the second semiconductor layer includes a lower substrate including a plurality of address decoders and a plurality of page buffer circuits configured to control the array of memory cells; a control circuit configured to control the plurality of address decoders and the plurality of page buffer circuits in response to commands and addresses from an external device; and a pad region disposed adjacent to the first semiconductor layer in the first direction and extending in the second direction, wherein the vertical structures include a plurality of via regions in which one or more through-via vias are disposed, and the plurality of via regions are spaced apart in the second direction, wherein the array of memory cells includes a plurality of pads corresponding to different bit lines among the plurality of bit lines, and wherein at least two pads among the plurality of pads include different numbers of via regions according to a distance from the pad region in the first direction.

2. The nonvolatile memory device of claim 1, wherein: the plurality of pads includes at least a first pad and a second pad, a first distance from the pad region to the first pad in the first direction is less than a reference distance, and a second distance from the pad region to the second pad in the first direction is greater than or equal to the reference distance.

3. The nonvolatile memory device of claim 2, wherein: the first pad includes a first number of via regions, the second pad includes a second number of via regions, and the first number is less than the second number.

4. The nonvolatile memory device of claim 2, wherein: the first pad includes a first number of via regions, the second pad includes a second number of via regions, and the first number is greater than the second number.

5. The nonvolatile memory device of claim 4, wherein: the control circuit is configured to selectively store hot data and cold data in the first pad and the second pad based on a frequency of access by the external device, the control circuit is configured to store the hot data in the first pad and is configured to store the cold data in the second pad, the hot data is accessed at a first frequency greater than a reference frequency during a reference time interval, and the cold data is accessed at a second frequency less than or equal to the reference frequency during the reference time interval.

6. The nonvolatile memory device of claim 1, wherein, the second semiconductor layer includes a first region, a second region, a third region, and a fourth region divided along the first and second directions intersecting at a point at which the array of memory cells is stacked in the third direction, wherein the first region and the second region are adjacent to each other in the first direction, and the second region and the third region are adjacent to each other in the second direction, wherein the plurality of page buffer circuits includes first to fourth page buffer circuits respectively located in the first to fourth regions.

7. The nonvolatile memory device of claim 1, wherein, at least a first portion of the one or more through-hole vias connects at least some portions of the plurality of bit lines to at least some portions of the plurality of page buffer circuits, and wherein at least a second portion of the one or more through-hole vias connects at least some portions of the plurality of word lines to at least some portions of the plurality of address decoders.

8. A non-volatile memory device, comprising: a first semiconductor layer including an upper substrate in which a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction are disposed, and a memory cell array including vertical structures located on the upper substrate, wherein the vertical structures include a plurality of memory blocks; a second semiconductor layer located below the first semiconductor layer in a third direction perpendicular to the first and second directions, wherein the second semiconductor layer includes a lower substrate including a plurality of address decoders and a plurality of page buffer circuits configured to control the memory cell array; a control circuit configured to control the plurality of address decoders and the plurality of page buffer circuits in response to commands and addresses from an external device; and a pad region disposed adjacent to the first semiconductor layer in the first direction and extending in the second direction, wherein the vertical structures include a plurality of via regions in which one or more through-hole vias are disposed, and the plurality of via regions are spaced apart in the second direction, wherein at least a first portion of the one or more through-hole vias connects at least some portions of the plurality of bit lines to at least some portions of the plurality of page buffer circuits, wherein at least a second portion of the one or more through-hole vias connects at least some portions of the plurality of word lines to at least some portions of the plurality of address decoders, wherein the memory cell array includes a plurality of pads corresponding to different bit lines among the plurality of bit lines, wherein each of the plurality of pads includes a first tile and a second tile identified based on a distance from the pad region in the first direction, and wherein the first tile and the second tile include different numbers of via regions according to the distance from the pad region in the first direction.

9. The non-volatile memory device of claim 8, wherein: a first distance from the pad region to the first tile in the first direction is less than a reference distance, and a second distance from the pad region to the second tile in the first direction is greater than or equal to the reference distance.

10. The non-volatile memory device of claim 9, wherein: the first tile includes a first number of via regions, the second tile includes a second number of via regions, and the first number is different from the second number. the second tile includes a second number of via regions, and the first number is less than the second number.

11. The non-volatile memory device of claim 9, wherein: the first tile includes a first number of via regions, the second tile includes a second number of via regions, and the first number is greater than the second number.

12. The non-volatile memory device of claim 11, wherein: the control circuit is configured to selectively store hot data and cold data in the first tile and the second tile based on a frequency of access from the external device, the control circuit is configured to store the hot data in the first tile and configured to store the cold data in the second tile, the hot data is accessed at a first frequency greater than a reference frequency during a reference time interval, and the cold data is accessed at a second frequency less than or equal to the reference frequency during the reference time interval.

13. A non-volatile memory device, comprising: a first semiconductor layer including an upper substrate in which a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction are disposed, and a memory cell array including vertical structures on the upper substrate, wherein the vertical structures include a plurality of memory blocks; a second semiconductor layer located below the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, wherein the second semiconductor layer includes a lower substrate including a plurality of address decoders configured to control the memory cell array and a plurality of page buffer circuits; a control circuit configured to control the plurality of address decoders and the plurality of page buffer circuits in response to a command and an address from an external device; and a pad region disposed adjacent to the first semiconductor layer in the first direction and extending in the second direction, wherein a plurality of input / output pads and at least one power pad are disposed in the pad region, wherein the vertical structures include a plurality of via regions in which one or more through-hole vias are disposed, and the plurality of via regions are spaced apart in the second direction, wherein the at least one power pad is disposed adjacent to a first edge portion of the pad region, wherein the memory cell array includes a plurality of pads corresponding to different bit lines among the plurality of bit lines, and wherein at least two pads among the plurality of pads include different numbers of via regions according to a distance from the at least one power pad in the second direction.

14. The non-volatile memory device of claim 13, wherein: the plurality of pads includes at least a first pad and a second pad, a first distance from the at least one power pad to the first pad in the second direction is less than a first reference distance, and a second distance from the at least one power pad to the second pad in the second direction is greater than or equal to the first reference distance.

15. The non-volatile memory device of claim 14, wherein: the first pad includes a first number of via regions, the second pad includes a second number of via regions, and the first number is less than the second number.

16. The non-volatile memory device of claim 14, wherein: the first pad includes a first number of via regions, the second pad includes a second number of via regions, and the first number is greater than the second number.

17. The non-volatile memory device of claim 16, wherein: the control circuit is configured to selectively store hot data and cold data in the first pad and the second pad based on a frequency of access from the external device, the control circuit is configured to store the hot data in the first pad and is configured to store the cold data in the second pad, the hot data is accessed at a first frequency greater than a reference frequency during a reference time interval, and the cold data is accessed at a second frequency less than or equal to the reference frequency during the reference time interval.

18. The non-volatile memory device of claim 14, wherein: the first pad includes a first tile and a second tile identified based on a distance from the at least one power pad in the second direction, the second pad includes a third tile and a fourth tile identified based on a distance from the at least one power pad in the second direction, a third distance from the at least one power pad to the first tile in the second direction is less than a second reference distance, and a fourth distance from the at least one power pad to the second tile in the second direction is greater than or equal to the second reference distance.

19. The non-volatile memory device of claim 18, wherein: the first tile includes a first number of via regions, the second tile includes a second number of via regions, each of the third tile and the fourth tile includes a third number of via regions, and the second number is greater than the first number and the third number is greater than the second number.

20. The non-volatile memory device of claim 18, wherein: the first tile includes a first number of via regions, the second tile includes a second number of via regions, each of the third tile and the fourth tile includes a third number of via regions, and the first number is greater than the second number and the second number is greater than the third number.

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