High bandwidth flash memory chip, memory and data reading method

Abstract

The application discloses a high-bandwidth flash memory chip, a memory and a data reading method. The high-bandwidth flash memory chip comprises N flash memory modules arranged in an array, and the N flash memory modules are used for storing data. Any flash memory module comprises a flash memory cell, an address decoder, a data register and an IO interface group. The flash memory cell is used for outputting data in a reading mode and storing data in a programming mode. The address decoder is used for outputting the address of the flash memory cell. The data register is used for storing data. The IO interface group is used for transmitting data and information. The data register is coupled to the flash memory cell, and the IO interface group is coupled to the data register. The flash memory chip of the application is provided with multiple flash memory modules working in parallel, so that the reading and writing speed of data is improved. In addition, the data register is directly coupled to the flash memory cell and the IO interface group, the transmission path of data is shortened, and the flash memory chip has high transmission capacity.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of flash memory chips, in particular to a high-bandwidth flash memory chip, a memory and a data reading method. BACKGROUND

[0002] NAND flash is a non-volatile storage device, and data will not be lost even if power is cut off. The current flash memory chip adopts ONFI5.0 protocol, and the data transmission rate is 2.4GB / s. This protocol can still meet the demand of traditional terminal products. However, in the era of artificial intelligence, the transmission rate of AI computing chips for data has been greatly improved. For example, a large language model requires a transmission rate of about 500GB / s. The transmission rate of NAND flash is far from meeting the demand, and it has become one of the bottlenecks restricting the computing speed.

[0003] At the same time, based on the existing NAND flash circuit and packaging structure, the storage unit array occupies more than 80% of the area of the chip, and is concentrated together, and then transmitted to the IO interface through the cache circuit. The current NAND has 8 IO interfaces, and the circuit architecture and the number of IOs limit the data transmission speed. SUMMARY

[0004] The main purpose of the present application is to provide a high-bandwidth flash memory chip, a memory and a data reading method, which aims to solve the technical problem of slow data transmission speed of the flash memory chip in the prior art.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a high-bandwidth flash memory chip, comprising:

[0006] N flash memory modules arranged in an array, N being an integer not less than 2, the N flash memory modules being used for storing data, any of the flash memory modules comprising a flash memory cell, an address decoder, a data register and an IO interface group, the flash memory cell being used for outputting the data in a read mode and storing the data in a programming mode, the address decoder being used for determining the address of the flash memory cell corresponding to the data, the data register being used for storing data to be input into the flash memory cell and storing data output by the flash memory cell, and the IO interface group being used for transmitting the data and information;

[0007] Among them, the data register is directly coupled to the flash memory cell, and the IO interface group is directly coupled to the data register.

[0008] In some embodiments, the IO interface group comprises a plurality of IO interfaces, the plurality of IO interfaces comprising an IO input port and an IO output port, the IO input port being used for receiving the data and the information, and the IO output port being used for outputting the data and the information.

[0009] In some embodiments, the address decoder comprises a row decoder and a column decoder, both coupled to the flash memory cell, the row decoder being configured to determine that the data corresponds to a row address of the flash memory cell, and the column decoder being configured to determine that the data corresponds to a column address of the flash memory cell.

[0010] In some embodiments, the total number of the IO input ports and the IO output ports is 32.

[0011] In some embodiments, the N is 16.

[0012] In a second aspect, the present application further provides a memory comprising a computing chip, a control chip and a high-bandwidth flash memory chip as described above, the flash memory chip, the control chip and the computing chip being vertically stacked and bonded in sequence, the computing chip being configured to receive and parse a data read / write request from an external user terminal to obtain a data read operation instruction and a logical address of the flash memory chip;

[0013] The control chip is configured to convert the logical address into a physical address, and perform a data read operation on the flash memory chip according to the data read operation instruction and the physical address.

[0014] In a third aspect, the present application further provides a data read method, comprising:

[0015] The computing chip receives a data read request, the data read request comprising a logical address of to-be-output data and a data read operation instruction;

[0016] The control chip converts the logical address into a physical address of the to-be-output data, and performs a data read operation on the flash memory chip according to the data read operation instruction;

[0017] The flash memory chip sends the data read operation instruction and the physical address to N flash memory modules;

[0018] The address decoder converts the physical address to determine that the to-be-output data is located at an address of the N flash memory modules;

[0019] The N flash memory modules output the to-be-output data in parallel.

[0020] In some embodiments, the address decoder converts the physical address to determine that the to-be-output data is located at an address of the N flash memory modules, comprising:

[0021] The row decoder converts the physical address to determine that the to-be-output data is located at a page address of the flash memory cell of the N flash memory modules, the number of the page addresses being N.

[0022] The column decoder converts the physical address to determine the start byte table of the N page addresses.

[0023] In some embodiments, the N flash modules output the to-be-output data in parallel, comprising:

[0024] The to-be-output data in the start byte table within the N page addresses are transmitted to N data registers in parallel;

[0025] The to-be-output data are checked for error protection;

[0026] The N data registers send the to-be-output data to the IO output ports of the N IO interface groups in parallel.

[0027] In some embodiments, the to-be-output data are checked for error protection, comprising:

[0028] Comparing the ECC check code in the to-be-output data with a newly calculated ECC check code;

[0029] According to the comparison result, whether the N data registers send the to-be-output data to the N IO interface groups is controlled.

[0030] The flash chip of the present application provides a large data storage capacity to the user end by setting multiple flash modules, any of which includes a flash unit, an address decoder, a data register and an IO interface group. The multiple flash modules can transmit data in parallel through the multiple IO interface groups, improving the read-write speed of data and making the flash chip have a high bandwidth advantage. When the user end needs to read or write a large amount of data, multiple flash modules can be operated simultaneously, thereby greatly shortening the data processing time. In addition, the data register is directly coupled with the flash unit and the IO interface group, shortening the data transmission path and making the flash chip have high transmission efficiency, thereby providing the user end with continuous, efficient and stable data storage services. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 Part of the structure diagram of an embodiment of the high-bandwidth flash chip of the present application;

[0032] Figure 2 Part of the structure diagram of an embodiment of the flash module of the present application;

[0033] Figure 3 Part of the structure diagram of an embodiment of the flash module in the prior art;

[0034] Figure 4 Part of the structure diagram of an embodiment of the memory of the present application;

[0035] Figure 5 Fig. 1 is a schematic diagram of a partial structure of a memory in the prior art;

[0036] Figure 6 Fig. 2 is a schematic diagram of steps of a data reading method provided in an embodiment of the present application;

[0037] Figure 7 Fig. 3 is a schematic diagram of a partial structure of a memory in the prior art; Figure 6 Fig. 4 is a schematic diagram of a specific embodiment of step S4 in Fig. 2;

[0038] Figure 8 Fig. 5 is a schematic diagram of a partial structure of a memory in the prior art; Figure 6 Fig. 6 is a schematic diagram of a specific embodiment of step S5 in Fig. 2;

[0039] Figure 9 Fig. 7 is a schematic diagram of a specific embodiment of step S52 in Fig. 6. Figure 8 BRIEF DESCRIPTION OF THE DRAWINGS

[0040]

[0041] DETAILED DESCRIPTION The scheme in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0042] It should be noted that all directional indications, such as up, down, left, right, front, back, etc., in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0043] It should also be noted that when an element is referred to as being “fixed to” or “set on” another element, it can be directly on the other element or can have a middle element. When an element is referred to as being “connected” to another element, it can be directly connected to the other element or can have a middle element.

[0044]

[0045] ​​In addition, the descriptions involving "first", "second", etc. in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0046] Please refer to Figure 1 and Figure 2 , in order to solve the above-mentioned problems, the present application proposes a high-bandwidth flash memory chip 1, comprising N flash memory modules 11 arranged in an array. Wherein, N is an integer not less than 2, N flash memory modules 11 are used to store data, any flash memory module 11 comprises a flash memory unit 111, an address decoder 112, a data register 113 and an IO interface group 114, the flash memory unit 111 is used to output data in read mode and store data in programming mode, the address decoder 112 is used to determine the address of the data corresponding to the flash memory unit 111, the data register 113 is used to store the data to be input into the flash memory unit 111 and store the data output by the flash memory unit 111, and the IO interface group 114 is used to transmit data and information.

[0047] In the present embodiment, the flash memory unit 111 is the core storage component, which undertakes the functions of outputting data and storing data in different modes. The address decoder 112 can accurately convert the address of the flash memory unit 111, ensuring the accurate reading of data and the determination of storage location. The data register 113 plays the role of data transfer, on the one hand, it stores the data to be input into the flash memory unit 111, on the other hand, it stores the data output by the flash memory unit 111. The IO interface group is responsible for transmitting data and information, and is an important channel for the flash memory chip 1 to interact with the outside.

[0048] Among them, please refer to Figure 1 The flash memory modules 11 arranged in an array can realize parallel data access. When the external device needs to read or write data, multiple flash memory modules 11 can be operated at the same time, thereby greatly improving the data transmission speed and access efficiency. For example, in large-scale data storage and retrieval applications, the flash memory modules 11 arranged in an array can quickly respond to multiple concurrent data requests, improving the overall performance of the system.

[0049] Correspondingly, the plurality of IO interface groups 114 are also arranged in an array, each coupled to one of the flash memory units 111, and the plurality of IO interface groups 114 can be parallel throughput, greatly improving the data transmission speed of the flash memory chip 1.

[0050] As a preferred embodiment of the present application, N is 16, that is, the flash memory chip 1 proposed in the present application comprises 16 flash memory modules 11. By arranging 16 flash memory modules 11, the storage capacity of the flash memory chip 1 can be increased, and each flash memory module 11 is arranged with an independent data register 113 and an IO interface group 114. When the user terminal requests to write data or read data, the 16 flash memory modules 11 are started at the same time, which improves the data transmission rate of the flash memory chip 1 and meets the demand of the user terminal for large data transmission.

[0051] Please refer to Figure 3 In the prior art, when data is read, the data is first transmitted from the flash memory unit 111 to the data register 113, then transmitted from the data register 113 to the page buffer register 115, and finally transmitted into the IO interface group 114 to be read by the user terminal. The long transmission path results in slow transmission speed, which cannot meet the demand of specific scenarios such as artificial intelligence.

[0052] In view of this, please refer to Figure 2 As a preferred embodiment of the present application, the data register 113 is directly coupled to the flash memory unit 111, and the IO interface group 114 is directly coupled to the data register 113.

[0053] The data register 113 is coupled to the flash memory unit 111, and the IO interface group is directly coupled to the data register 113. This connection mode enables the data to be directly transmitted from the IO interface group 114 to the data register 113 and then transmitted from the data register 113 to the flash memory unit 111 when the data is written, and the transmission path of the data is from the flash memory unit 111 to the data register 113 to the IO interface group 114 when the data is read. The data path is shortened, the data is efficiently circulated among the flash memory unit 111, the data register 113 and the IO interface group, and the data transmission efficiency of the flash memory chip 1 is improved.

[0054] The steps of data programming using the flash memory chip 1 of the present application are as follows:

[0055] (1) The external device prepares the data to be written and provides target address information.

[0056] (2) The data enters the flash memory module 11 through the IO interface group.

[0057] (3) The entered data is first stored in the data register 113.

[0058] (4) The address decoder 112 determines the position of the flash memory unit 111 to which the data is to be written according to the target address information.

[0059] (5) The data is transmitted from the data register 113 to the corresponding flash memory unit 111 for storage, and the programming process is completed.

[0060] The data reading process using the flash memory chip 1 of the present application is as follows:

[0061] (1) The external device sends a data reading request and provides corresponding address information.

[0062] (2) After receiving the request, the flash memory chip 1 determines the location of the corresponding flash memory unit 111 according to the provided address information by the address decoder 112.

[0063] (3) After determining the flash memory unit 111, the flash memory unit 111 outputs data in the reading mode according to the instruction.

[0064] (4) The output data is temporarily stored in the data register 113.

[0065] (5) The data in the data register 113 is transmitted to the external device through the IO interface group, completing the data reading process.

[0066] The flash memory chip 1 of the present application has the following advantages:

[0067] By adopting the design of multiple flash memory modules 11, a larger data storage capacity can be provided, and multiple flash memory modules 11 can transmit data in parallel through multiple IO interface groups, improving the read and write speed of data, so that the flash memory chip has the advantage of high bandwidth. When the system needs to read or write a large amount of data, multiple flash memory modules 11 can be operated simultaneously, thereby greatly shortening the data processing time. In addition, the data register 113 is directly coupled with the flash memory unit 111 and the IO interface group, shortening the data transmission path, so that the flash memory chip 1 has high transmission capacity and can provide continuous and efficient and stable data storage services for the user end.

[0068] In some embodiments, the IO interface group 114 includes multiple IO interfaces, and the multiple IO interfaces include IO input ports and IO output ports, the IO input ports being used for receiving data and information, and the IO output ports being used for outputting data and information.

[0069] The flash memory module 11 of the present application has multiple IO interfaces, which provides more channels for data transmission and improves the parallelism and efficiency of data transmission. Whether it is fast writing of a large amount of data or frequent data reading, multiple interfaces can work simultaneously, greatly shortening the data transmission time. In addition, multiple IO interfaces can also be used to transmit commands and addresses to operate and address the flash memory unit 111.

[0070] The interface is divided into an IO input port and an IO output port, making the flow of data clearer. The IO input port is responsible for receiving data and information, and can efficiently handle data input requests from external devices, ensuring that data is accurately entered into the flash chip 1. The IO output port focuses on outputting data and information, and can quickly transmit data in the flash chip 1 to external devices, meeting the needs of data output in different application scenarios and improving the data transmission speed of the flash chip 1.

[0071] To further improve the efficiency of data transmission of the flash chip 1, the sum of the number of IO input ports and IO output ports is 32.

[0072] By providing 32 interfaces in each flash module 11, a large number of data transmission tasks can be handled simultaneously, greatly improving the speed of data transmission. Whether it is high-speed data acquisition, large-scale data storage or real-time data processing, it can meet the requirements of data transmission speed. In addition, the existence of multiple interfaces can distribute the load of data transmission and reduce the pressure on a single interface, thereby improving the stability and reliability of the entire system. Even in high-load data transmission situations, stable performance can be maintained, reducing the occurrence of data transmission errors and failures.

[0073] As an embodiment, the flash chip 1 of the present application is a NAND FLASH chip, which uses the ONFI protocol for data transmission. The flash chip 1 provided by the present application is provided with 16 flash modules 11, and any flash module 11 contains 32 IO interfaces, that is, the flash chip 1 has 512 IO interfaces. When the flash chip 1 is working, the 512 IO interfaces can transmit data at the same time, and the transmission rate is as high as 1228.8 GB / s, which can meet the needs of the flash chip 1 in the era of artificial intelligence.

[0074] Please refer to Figure 2 In some embodiments, the address decoder 112 includes a row decoder 112a and a column decoder 112b, both coupled to the flash memory cells 111. The row decoder 112a is configured to determine a row address of the data corresponding to the flash memory cells 111, and the column decoder 112b is configured to determine a column address of the data corresponding to the flash memory cells 111.

[0075] In some embodiments, the row decoder 112a and the column decoder 112b are coupled to the adjacent sides of the flash memory cells 111, respectively. Specifically, the row decoder 112a is coupled in the direction of the word lines inside the flash memory cells 111, and the column decoder 112b is coupled in the direction of the bit lines. In this embodiment, by setting the row decoder 112a to output data corresponding to the row address of the flash memory cells 111, it can be determined which page on which bit line the data is stored. And by setting the column decoder 112b to output data corresponding to the column address of the flash memory cells 111, it can be determined which byte in the page the data is finally stored in. This double orientation positioning can achieve high-precision addressing of the flash memory cells 111. Whether it is to store large-scale data or to quickly access a specific data block, the target location can be accurately found. In addition, accurate address decoding can greatly shorten the data read and write time. When reading data, the target data can be quickly located in the row and column. Similarly, when programming, the target storage location can be quickly determined, and the data can be accurately written into the flash memory cells 111. In summary, the row decoder 112a and the column decoder 112b and their coupling relationship with the flash memory cells 111 provide the flash memory chip 1 with high-precision addressing capability, improve the read-write efficiency, optimize the storage management, and enhance the reliability.

[0076] Please refer to Figure 1 In some embodiments, the flash memory chip 1 further includes a command register 12 coupled to the IO interface group 114 for storing and sending the operation commands of the flash memory cells 111 to the flash memory cells 111.

[0077] Firstly, the presence of the command register 12 enables the operation commands of the flash memory cells 111 to be quickly and accurately transmitted from the IO interface group to the flash memory cells 111. In scenarios where read or program operations need to be performed frequently, the response speed of the operation can be greatly improved, and the delay of command transmission can be reduced. Secondly, storing operation commands in the command register 12 facilitates the unified management of the operation of the flash memory chip 1. Through monitoring and controlling the command register 12, the orderly scheduling of the operation of the flash memory cells 111 can be realized, and the stability and reliability of the system can be improved. Finally, since the command register 12 can store different operation commands, it provides greater flexibility for the application of the flash memory chip 1. Different commands can be sent to the command register 12 through the IO interface group according to different needs, thereby realizing diversified operations of the flash memory cells 111.

[0078] Please continue to refer to Figure 1In some embodiments, the flash memory chip 1 further comprises an address register 14 coupled to the IO interface group 114 for storing address information and delivering the address information to the address decoder 112 for the data register 113 to fetch data corresponding to the address information of the flash memory cell 111 or write data to the location of the flash memory cell 111 corresponding to the address information.

[0079] In the present embodiment, the address register 14 takes on the important task of storing the address information delivered by the IO interface group 114 and delivering the address information to the address decoder 112. This connection ensures that the address information can be accurately delivered from the external input to the row decoder 112a and the column decoder 112b of the flash memory cell 111.

[0080] In the present embodiment, the address register 14 takes on the important task of storing the address information delivered by the IO interface group 114 and delivering the address information to the address decoder 112. This connection ensures that the address information can be accurately delivered from the external input to the row decoder 112a and the column decoder 112b of the flash memory cell 111.

[0081] In summary, the address register 14, through its specific functions and synergies with other components, provides the flash memory chip 1 with efficient address delivery, accurate data positioning, enhances the flexibility of the flash memory chip 1 and optimizes the performance of the flash memory chip 1, plays an important role in the normal operation and efficient data processing of the flash memory chip 1.

[0082] Please continue to refer to Figure 1 In some embodiments, the flash memory chip 1 further comprises a state register 13 coupled to the IO interface group 114 to deliver the state signal of the flash memory cell 111 temporarily stored in the state register 13 to the IO interface group 114.

[0083] The state register 13 has the ability to temporarily store the state signal of the flash memory cell 111. This means that it can collect and store the state information of the flash memory cell 111 at a specific point in time, so as to deliver it to the external device in a timely manner when needed, ensuring that the external device can accurately understand the current working state of the flash memory cell 111. For example, the external device can obtain important information such as whether the flash memory cell 111 is performing read / write operations, whether it is in a busy state, whether an error has occurred, etc. through the state register 13, so as to timely adjust the operation strategy and improve the stability and reliability of the flash memory chip 1.

[0084] Please refer to Figure 5, the prior art memory 100 is physically connected by wire bonding the flash memory chip 1 and the control chip 3, encapsulated into a chip, and then connected to the computing chip 2 through a PCB (printed circuit board). The wire bonding itself may introduce signal interference and attenuation. In addition, due to the physical properties of wire bonding, signal reflection, crosstalk and other problems may occur when transmitting high-speed signals, resulting in a decrease in signal quality and a decrease in transmission rate.

[0085] In view of this, please refer to Figure 4 The application also provides a memory 100, comprising a computing chip 2, a control chip 3 and a high-bandwidth flash memory chip 1 as described above. The flash memory chip 1, the control chip 3 and the computing chip 2 are sequentially vertically stacked and bonded. The computing chip 2 is used to receive and parse data read / write requests from an external user terminal to obtain data read operation instructions and logical addresses for the flash memory chip 1. The control chip 3 is used to convert the logical addresses into physical addresses and perform data read operations on the flash memory chip 1 according to the data read operation instructions and the physical addresses.

[0086] The computing chip 2 receives data read / write requests from an external user terminal, which may come from various devices such as computers, mobile phones, etc. These data read / write requests include specific data read operation instructions or data programming operation instructions, as well as data based on the user's logical address. When the user wants to read or write data from the flash memory chip 1, the computing chip 2 can parse these diverse data read / write requests into specific data read or programming operation instructions for the flash memory chip 1, and obtain the logical address for the control chip 3 to perform data read / write operations on the flash memory chip 1. This parsing and conversion function allows external devices to access the memory 100 without needing to understand the complex internal structure and operation of the flash memory chip 1, simply by interacting with the computing chip 2.

[0087] The control chip 3 receives data read or programming operation instructions from the computing chip 2, as well as the logical address of the data. The control chip 3 can convert the logical address into the physical address of the data in the flash memory chip 1, i.e. the actual address, so that the user can access the correct data. At the same time, the control chip 3 is responsible for accurately transmitting these instructions to the flash memory chip 1. After receiving the instructions, the flash memory chip 1 will convert into the corresponding read mode or programming mode. For example, the control chip 3 sends a data read operation instruction to the flash memory chip 1, which becomes a read mode and performs a data read operation. It will retrieve the corresponding data from multiple flash memory modules 11 according to the instruction and output it to the user for reading.

[0088] Please continue to refer to Figure 4As a preferred embodiment of the present application, the hybrid bonding method is adopted when packaging the computing chip 2, the control chip 3 and the flash memory chip 1. Hybrid bonding is a 3D packaging technology mainly used to realize high-density and high-performance interconnection between different chips. When packaging the computing chip 2, the control chip 3 and the flash memory chip 1, the metal layers (usually copper layers) of the three chips are precisely aligned and pressed together to achieve direct electrical contact.

[0089] To ensure good connection, the surfaces of the computing chip 2, the control chip 3 and the flash memory chip 1 need to be treated. For example, a layer of dielectric material such as silicon dioxide can be deposited on the surface, and micron or even nanometer copper pads and vias can be prepared on it. The copper pads and vias can connect the internal circuits of the chip to the outside, making the data transmission speed of the memory 100 faster and the power consumption lower, while greatly improving the integration of the internal chips of the memory 100. Of course, the above is only exemplary, and the dielectric material deposited on the surface of the chip can also be silicon carbonitride, etc. The specific type can be determined according to actual needs, and the present application does not limit it.

[0090] The control chip 3 can be one of USB, EMMC, UFS and SSD controller, etc. For example, the control chip 3 is an SSD controller that supports high-speed transmission and multi-channel parallel processing, and has good data transmission performance. In addition, the SSD controller can effectively detect and mark bad blocks in the flash memory chip 1, and automatically avoid these bad blocks during data storage and reading, ensuring correct data storage and reading and improving the reliability of the memory 100. Of course, the above is only exemplary, and the specific type of control chip 3 can be determined according to actual needs, and the present application does not limit it.

[0091] Generally, the computing chip 2 can be one of CPU, GPU and NPU. For example, the computing chip 2 is an NPU that has efficient neural network computing capability and is particularly good at processing neural network training and inference calculation, especially suitable for current artificial intelligence applications. Because the NPU can provide efficient computing support, for example, in image recognition, speech recognition and other application scenarios, the NPU can quickly process and analyze stored image and speech data. Of course, the above is only exemplary, and the specific type of computing chip 2 can be determined according to actual needs, and the present application does not limit it.

[0092] It should be noted that since the memory 100 adopts all the technical solutions of the above-mentioned flash memory chip 1 embodiments, the memory 100 provided by the present application also has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0093] The application also provides a data reading method based on the memory 100. Figure 6 In a preferred embodiment, the data reading method comprises the following steps:

[0094] In step S1, the computing chip 2 receives a data reading request, which comprises a logical address of data to be output and a data reading operation instruction.

[0095] When the user terminal sends a data reading request to the flash memory chip 1, the data reading request is first received by the computing chip 2. As an embodiment, in the application of artificial intelligence, the computing chip 2 is an NPU, which converts the data reading operation instruction contained in the data reading request through the NPU, so that the subsequent control chip 3 can read and operate, and the flash memory chip 1 is converted to a reading mode.

[0096] In step S2, the control chip 3 converts the logical address into a physical address of the data to be output, and performs a data reading operation on the flash memory chip 1 according to the data reading operation instruction.

[0097] As an embodiment, the control chip 3 is an SSD controller, which contains a mapping table inside, which can map the logical address of the data to the actual physical address. After the flash memory chip 1 obtains the physical address, it can access and read the data stored in the flash memory unit 111.

[0098] In addition, the control chip 3 can convert the data reading request operation instruction transmitted by the computing chip 2 into a specific data reading operation on the flash memory chip 1, so as to operate multiple flash memory modules 11 inside in parallel to output the data to be output.

[0099] In step S3, the flash memory chip 1 sends the data reading operation instruction and the physical address to the N flash memory modules 11.

[0100] After the data reading operation instruction is transmitted to the flash memory chip 1, it is stored in the command register 12, and then sent to the N flash memory modules by the command register 12 to simultaneously start the data reading operation. The physical address of the data to be output is stored in the address register 14, and then sent to the address decoder 112 in the N flash memory modules 11 for address decoding.

[0101] It should be noted that in the present application, N is 16, that is, the flash memory chip 1 can operate 16 flash memory modules 11 to simultaneously start and transmit data to the external device in parallel, thereby improving the data transmission rate of the flash memory chip 1.

[0102] In step S4, the address decoder 112 converts the physical address to determine the address of the data to be output in the N flash memory modules 11.

[0103] In the present application, any flash memory module 11 contains a flash memory unit 111, which internally contains array storage units. The address decoder 112 can decode the physical address into the specific row address and column address of the array storage unit corresponding to the data to be output, ensuring that the user can access and read the required data.

[0104] Referring to Figure 7 In some embodiments, the aforementioned step S4 comprises:

[0105] Step S41, the row decoder 112a converts the physical address to determine the page address of the flash memory unit 111 of the N flash memory modules 11 where the data to be output is located, and the number of page addresses is N.

[0106] The array storage units of the flash memory unit 111 are composed of a plurality of data blocks, each of which contains a plurality of pages, and each page contains a plurality of bytes. When reading the flash memory unit 111, data is read in units of pages. Therefore, the row decoder 112a is needed to decode the physical address to determine the page address of the array storage unit where the data to be read is located.

[0107] In the present application, N is 16, i.e. the row decoder 112a coupled to each of the 16 flash memory units 111 can simultaneously decode to obtain 16 page addresses to determine the location of the data to be output, realizing large-scale reading of data.

[0108] Step S42, the column decoder 112b converts the physical address to determine the starting byte table of the N page addresses.

[0109] Each page in the array storage unit stores a certain number of data, and the column decoder 112b can determine the position of the data to be output in a certain bit or several bits of each page. Decoding the specific starting byte table by the column decoder 112b can avoid reading unnecessary data and improve reading efficiency.

[0110] Step S5, the N flash memory modules 11 output the data to be output in parallel.

[0111] Referring to Figure 8 In some embodiments, the aforementioned step S5 comprises:

[0112] Step S51, the starting byte table in the N page addresses is transmitted to the N data registers 113 simultaneously.

[0113] Step S52, the data register 113 checks the data to be output for error prevention before sending it to the IO output port in parallel.

[0114] Data read and write on the flash memory unit 111 will occur a certain probability of error, so that the data is read by the user before the error check.

[0115] Step S53, N data registers 113 will be output data parallel into the IO interface group 114 IO output port.

[0116] The output data after the step S52 step of no error, 16 data registers 113 will be data directly into the corresponding IO output port, shortening the transmission path of the output data, improve the transmission efficiency.

[0117] Reference Figure 9 In some embodiments, the foregoing step S52 also includes:

[0118] Step S521, the ECC check code of the output data and the new ECC check code are compared.

[0119] The original data of the output data is written into the flash memory chip 1, and an ECC check code is generated every 256 bytes, which is defined as the original ECC check code. The original ECC check code is saved in the OOB (out-of-band) database of the page. When the user reads the output data, the ECC module inside the flash memory chip 1 will generate another ECC check code according to the algorithm, which is the new ECC check code. When the output data is output from the array storage unit, the original ECC check code and the new ECC check code are XORed to determine whether the output data stored in the flash memory unit 111 is consistent with the original data, so as to ensure that the user reads the correct output data.

[0120] Step S522, according to the comparison result, control N data registers 113 whether to send the output data to N IO interface group 114.

[0121] The comparison result of the original ECC check code and the new ECC check code has many possibilities. If the comparison result is 0, it means that the data has no error, and the 16 data registers 113 are allowed to send the output data to the corresponding IO interface group 114 in parallel; if the 3 byte XOR result shows that there are 11 bits of 1, it means that the output data has a bit error, and after correction, the output data is transmitted to the corresponding IO interface group 114 by 16 data registers 113 in parallel; if the 3 byte XOR result only has one bit of 1, it means that the OOB database is wrong, or the comparison result appears except the above situation, which means that there is an uncorrectable error, and the data register 113 is prohibited to send the output data to the IO interface group 114. At this time, the user cannot read the data, and the memory 100 data error is prompted.

[0122] The above merely is part or preferred embodiments of the present application, neither the text nor the drawings can limit the scope of protection of the present application, any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields are included in the scope of protection of the present application.

Claims

1. A high bandwidth flash memory chip, characterized by, The application comprises: N flash memory modules arranged in an array, N being an integer not less than 2, the N flash memory modules being used for storing data, any of the flash memory modules comprising a flash memory cell, an address decoder, a data register and an IO interface group, the flash memory cell being used for outputting the data in a read mode and storing the data in a programming mode, the address decoder being used for determining the address of the data corresponding to the flash memory cell, the data register being used for storing data to be input into the flash memory cell and storing data output by the flash memory cell, and the IO interface group being used for transmitting the data and information; wherein the data register is directly coupled to the flash memory cell, and the IO interface group is directly coupled to the data register; the flash memory chip further comprises a command register, an address register and a status register, the command register being coupled to the IO interface group, the address register being coupled to the IO interface group, and the status register being coupled to the IO interface group; the IO interface group comprises a plurality of IO interfaces, the plurality of IO interfaces comprising an IO input port and an IO output port, the IO input port being used for receiving the data and the information, and the IO output port being used for outputting the data and the information; the total number of the IO input port and the IO output port is 32.

2. The high-bandwidth flash memory chip of claim 1, wherein, the address decoder comprises a row decoder and a column decoder, both of which are coupled to the flash memory cell, the row decoder being used for determining the row address of the data corresponding to the flash memory cell, and the column decoder being used for determining the column address of the data corresponding to the flash memory cell.

3. The high-bandwidth flash memory chip of claim 1 or 2, wherein, N is 16.

4. A memory, comprising: The application comprises a computing chip, a control chip and a high-bandwidth flash memory chip as claimed in any one of claims 1 to 3, the flash memory chip, the control chip and the computing chip being vertically stacked and bonded in sequence, the computing chip being used for receiving and analyzing a data read-write request from an external user terminal to obtain a data read operation instruction and a logical address of the flash memory chip; the control chip being used for converting the logical address into a physical address and performing a data read operation on the flash memory chip according to the data read operation instruction and the physical address.

5. A data reading method characterized by, The application is applied to the memory as claimed in claim 4, and the method comprises: the computing chip receives a data read request, the data read request comprising a logical address of data to be output and a data read operation instruction; the control chip converts the logical address into a physical address of the data to be output and performs a data read operation on the flash memory chip according to the data read operation instruction and the physical address; the flash memory chip sends the data read operation instruction and the physical address to the N flash memory modules; the address decoder converts the physical address to determine the address of the data to be output in the N flash memory modules; the N flash memory modules output the data to be output in parallel.

6. The data reading method according to claim 5, wherein, the address decoder converts the physical address to determine the address of the data to be output in the N flash memory modules, comprising: the address decoder comprises a row decoder and a column decoder; The row decoder converts the physical address to determine page addresses of the flash memory cells in N flash memory modules, wherein the number of the page addresses is N; The column decoder converts the physical address to determine a starting byte table of the N page addresses.

7. The data reading method according to claim 6, wherein The N flash memory modules output the data to be output in parallel, comprising: The starting byte table of the data to be output in the N page addresses is transmitted to N data registers in parallel; The data to be output is checked for error prevention; N data registers send the data to be output to N IO interface groups in parallel.

8. The data reading method according to claim 7, wherein, The checking of the data to be output for error prevention comprises: Comparing an ECC check code in the data to be output with a newly calculated ECC check code; According to the comparison result, whether the N data registers send the data to be output to the N IO interface groups is controlled.

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