Method of performing atomic operations

Abstract

The application discloses an atomic operation execution method, and relates to the technical field of computers, and comprises the following steps: determining a target atomic register corresponding to an access request, a target address in the target atomic register and an operation type in a register file unit through an address decoder; sequentially executing the atomic operation based on the target atomic register, the target address and the operation type through control logic and a sequencer; if it is determined that register value transformation information corresponding to the target address meets a preset interrupt condition through an interrupt control logic module, sending interrupt trigger information to an interrupt signal generator; and generating a corresponding interrupt based on the interrupt trigger information through the interrupt signal generator, and sending the interrupt to a second target CPU corresponding to the interrupt trigger information. All atomic operations in the application are implemented in a hardware mode within a module, and the atomic operation register and the interrupt control logic are closely integrated at a hardware level, thereby realizing atomic synchronization across a CPU cluster.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method for performing atomic operations. Background Technology

[0002] In multi-core System-on-Chip (SoC) designs, the adoption of multi-CPU cluster architecture has become mainstream due to the surge in processing performance demands. Cores within a single cluster are typically connected via an inter-core interconnect bus that supports cache coherency and atomic operations, achieving efficient data synchronization. However, multiple CPU clusters are often interconnected based on simpler, lower-cost underlying buses such as AXI (Advanced eXtensible Interface). These underlying buses do not provide hardware-level atomic operation support, making atomic synchronization across CPU clusters difficult.

[0003] Therefore, how to achieve atomic synchronization across CPU clusters is a problem that urgently needs to be solved.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a method for executing atomic operations, aiming to solve the technical problem of how to achieve atomic synchronization across CPU clusters.

[0006] To achieve the above objectives, this application proposes a method for executing atomic operations, applied to an atomic operation register module. The atomic operation register module includes an AXI bus interface, an address decoder, control logic and a sequencer, a register file unit, an arithmetic logic unit, an interrupt control logic module, and an interrupt signal generator. The AXI bus interface of the atomic operation register module is electrically connected to each CPU cluster via an AXI bus. The method for executing the atomic operations includes:

[0007] When an access request is received from the first target CPU in the CPU cluster via the AXI bus interface, the target atomic register, the target address in the target atomic register, and the operation type are determined in the register file unit by the address decoder.

[0008] The control logic and sequencer execute atomic operations in an orderly manner based on the target atomic register, the target address, and the operation type.

[0009] If the interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, then it sends interrupt trigger information to the interrupt signal generator.

[0010] An interrupt is generated by an interrupt signal generator based on the interrupt trigger information, and the interrupt is sent to the second target CPU corresponding to the interrupt trigger information.

[0011] In one embodiment, the target address includes the register address corresponding to the atomic increment operation, the operation type includes the atomic increment operation, and the step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes:

[0012] The first read result is obtained by performing a read operation on the target address of the target atomic register through the control logic and sequencer.

[0013] The arithmetic logic unit performs an atomic increment operation on the first read result to obtain the first atomic operation result;

[0014] The result of the first atomic operation is written to the target address of the target atomic register.

[0015] In one embodiment, the target address includes the register address corresponding to the atomic decrement operation, the operation type includes the atomic decrement operation, and the step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes:

[0016] The second read result is obtained by performing a read operation on the target address of the target atomic register through the control logic and sequencer.

[0017] The arithmetic logic unit performs an atomic decrement operation on the second read result to obtain the second atomic operation result;

[0018] The result of the second atomic operation is written to the target address of the target atomic register.

[0019] In one embodiment, the operation type includes atomic swap 0 or atomic swap 1, and the step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes:

[0020] If the target address includes the register address corresponding to an atomic swap of 0, then the control logic and sequencer perform a read operation on the target address of the target atomic register, obtain a third read result, and write 0 to the target address of the target atomic register; or,

[0021] If the target address includes the register address corresponding to an atomic swap of 1, then the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain the fourth read result, and write 1 into the target address of the target atomic register.

[0022] In one embodiment, the interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register; the interrupt triggering information includes lock release information and lock acquisition information.

[0023] The interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, and then sends the interrupt trigger information to the interrupt signal generator. The steps include:

[0024] The value change detector determines register value transformation information based on the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation;

[0025] If the register value change information is that the register value becomes 0, the value change detector determines that the register value change information meets the preset lock release interrupt condition, and the interrupt enable register sends the lock release information to the interrupt signal generator.

[0026] If the register value change information is that the register value becomes 1, the value change detector determines that the register value change information meets the preset lock acquisition interrupt condition, and the interrupt enable register sends the lock acquisition information to the interrupt signal generator.

[0027] In one embodiment, the interrupt triggering information includes resource availability notification and lock state change notification; the interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, and then the step of sending the interrupt triggering information to the interrupt signal generator includes:

[0028] If the register value change information is that the register value changes from 0 to non-zero, the value change detector determines that the register value change information meets the preset resource interruption condition, and the interrupt enable register sends a resource availability notification to the interrupt signal generator.

[0029] If the register value change information is that the register value changes from 1 to 0, the value change detector determines that the register value change information meets the preset lock state change interrupt condition, and the interrupt enable register sends the lock state change notification to the interrupt signal generator.

[0030] In one embodiment, when an access request is received from a first target CPU in a CPU cluster via the AXI bus interface, the step of determining the target atomic register corresponding to the access request, the target address in the target atomic register, and the operation type in the register file unit using an address decoder includes:

[0031] The address decoder receives the access request sent by the first target CPU through the AXI bus interface;

[0032] The address decoder parses the access request to obtain the parsing result;

[0033] The address decoder determines the target atomic register corresponding to the access request in the register file unit based on the parsing result, and determines the target address and operation type in the target atomic register based on the parsing result.

[0034] In one embodiment, the atomic operation register module further includes a first selector, the address decoder includes an atomic register address decoder, and the register file unit includes atomic registers;

[0035] The atomic register address decoder is communicatively connected to the AXI bus interface and the control logic and sequencer, respectively.

[0036] The atomic register is communicatively connected to the selection units of each atomic operation in the control logic and sequencer through the first selector.

[0037] In one embodiment, the atomic operation register module further includes a second selector and a third selector; the interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register;

[0038] The second selector is communicatively connected to both the atomic register and the third selector.

[0039] The value change detector is communicatively connected to the atomic register;

[0040] The interrupt enable register is communicatively connected to the value change detector and the second selector, respectively.

[0041] The interrupt status register is communicatively connected to the value change detector, the second selector, and the third selector, respectively.

[0042] The interrupt target register is communicatively connected to the second selector and the third selector, respectively;

[0043] The third selector is connected to each CPU in the CPU cluster.

[0044] In one embodiment, the atomic operation register module further includes a register read address decoder; the address decoder further includes an interrupt register address decoder;

[0045] The interrupt register address decoder is communicatively connected to the AXI bus interface, the interrupt enable register, the interrupt status register, and the interrupt target register, respectively.

[0046] The register read address decoder is communicatively connected to the AXI bus interface and the second selector, respectively.

[0047] One or more technical solutions proposed in this application have at least the following technical effects:

[0048] By setting multiple atomic registers in the atomic operation register module, atomic operations are implemented through the atomic registers. All atomic operations are implemented in hardware within the module. Different atomic operations are directly accessed through address decoding, realizing the hardware fusion of multi-address mapping atomic operations and interrupt generation. The atomic operation register and interrupt control logic are tightly integrated at the hardware level, and interrupts are automatically generated when the value changes, thus achieving atomic synchronization across CPU clusters. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A flowchart illustrating an embodiment of the method for performing atomic operations according to this application;

[0052] Figure 2 A schematic diagram of the framework provided for an embodiment of the method for performing atomic operations in this application;

[0053] Figure 3 A schematic diagram of the module structure of an atomic operation register module provided in an embodiment of the atomic operation execution method of this application;

[0054] Figure 4 This is a schematic diagram of the device structure of the hardware operating environment involved in the execution method of atomic operations in the embodiments of this application;

[0055] Figure 5 This is a schematic diagram of the circuit principle of an embodiment of the atomic operation register module of this application.

[0056] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0057] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0058] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0059] The main solution of this application embodiment is as follows: When an access request sent by the first target CPU in the CPU cluster is received through the AXI bus interface, the address decoder determines the target atomic register, the target address in the target atomic register, and the operation type corresponding to the access request in the register file unit; the control logic and sequencer execute atomic operations in an orderly manner based on the target atomic register, the target address, and the operation type; if the interrupt control logic module determines that the register value transformation information corresponding to the target address meets the preset interrupt conditions, then the interrupt trigger information is sent to the interrupt signal generator; the interrupt signal generator generates a corresponding interrupt based on the interrupt trigger information and sends the interrupt to the second target CPU corresponding to the interrupt trigger information.

[0060] In this embodiment, for ease of description, the execution device that identifies atomic operations will be used as the execution subject in the following description.

[0061] In multi-core System-on-Chip (SoC) design, with the surge in processing performance demands, multi-CPU cluster architecture has become mainstream. Cores within a single cluster are typically connected via an inter-core interconnect bus that supports cache coherency and atomic operations, achieving efficient data synchronization. However, multiple CPU clusters are often interconnected based on simpler, lower-cost underlying buses such as AXI (Advanced eXtensible Interface). These underlying buses do not provide hardware-level atomic operation support, making atomic synchronization across CPU clusters difficult.

[0062] In related technologies, synchronization can be simulated using algorithms with non-atomic instructions, but this approach is prone to memory ordering vulnerabilities, incurs significant performance overhead, causes a surge in bus traffic during periods of high contention, and is susceptible to livelock in multi-core environments. Alternatively, consistency extensions such as CHI or ACE can be added to the basic AXI bus, but this design is complex, increases chip area and cost, and is difficult to reconcile with older IPs.

[0063] Therefore, how to achieve atomic synchronization across CPU clusters is a problem that urgently needs to be solved.

[0064] This application provides a solution that sets up multiple atomic registers in the atomic operation register module, implements atomic operations through the atomic registers, and implements all atomic operations in hardware within the module. Different atomic operations are directly decoded through address decoding, realizing the hardware integration of multi-address mapping atomic operations and interrupt generation. The atomic operation register and interrupt control logic are tightly integrated at the hardware level, and interrupts are automatically generated when the value changes, thus realizing atomic synchronization across CPU clusters.

[0065] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or an execution device for atomic operations capable of performing the above functions. The following description uses an execution device for atomic operations as an example to illustrate this embodiment and the subsequent embodiments.

[0066] Based on this, embodiments of this application provide a method for performing atomic operations, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the method for executing atomic operations according to this application.

[0067] In this embodiment, as Figure 2 as well as Figure 3 As shown, the atomic operation register module includes an AXI bus interface, an address decoder, control logic and sequencer, a register file unit, an arithmetic logic unit, an interrupt control logic module, and an interrupt signal generator;

[0068] The interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register.

[0069] The register file unit comprises 16 independent 32-bit atomic registers, each capable of independent synchronization operations, with a reset value of 0 for each. Each atomic register is associated with eight address locations; for example, base address +0x00: addr_reg - atomic register value; base address +0x04: addr_add1 - atomic increment operation; base address +0x08: addr_sub1 - atomic decrement operation; base address +0x0C: addr_swap0 - atomic swap to 0; base address +0x10: addr_swap1 - atomic swap to 1; base address +0x14: intr_enable - interrupt enable configuration; base address +0x18: intr_status - interrupt status register (read / write 1 to clear); base address +0x1C: intr_target - interrupt target CPU configuration.

[0070] The AXI bus interface of the atomic operation register module is electrically connected to each CPU cluster via the AXI bus. The interrupt signal generator is connected to the interrupt control logic module and communicates with the CPUs in each CPU cluster through the interrupt signal network.

[0071] The address decoder is connected to the AXI bus interface and the control logic and sequencer respectively; the register file unit is connected to the control logic, sequencer and arithmetic logic unit respectively; the interrupt control logic module is connected to the arithmetic logic unit and interrupt signal generator respectively.

[0072] In this embodiment, the method for performing the atomic operation includes steps S110 to S140:

[0073] Step S110: When an access request is received from the first target CPU in the CPU cluster via the AXI bus interface, the target atomic register, the target address in the target atomic register, and the operation type are determined in the register file unit by the address decoder.

[0074] In this embodiment, each CPU in the CPU cluster can send an access request to the atomic operation register module via the AXI bus. The atomic operation register module receives the access request sent by the first target CPU in the CPU cluster via the AXI bus interface.

[0075] Upon receiving an access request, the access request is parsed using an address decoder to determine the target atomic register, the target address within the target atomic register, and the operation type in the register file unit. In one feasible implementation, step S110 may include steps S111-S113:

[0076] Step S111: The address decoder receives the access request sent by the first target CPU through the AXI bus interface;

[0077] Step S112: The address decoder performs a parsing operation on the access request to obtain a parsing result;

[0078] In step S113, the address decoder determines the target atomic register corresponding to the access request in the register file unit based on the parsing result, and determines the target address and operation type in the target atomic register based on the parsing result.

[0079] In this embodiment, after the atomic operation register module receives the access request sent by the first target CPU in the CPU cluster through the AXI bus interface, it transmits the access request to the address decoder. The address decoder parses the access request and obtains the parsing result.

[0080] After obtaining the parsing result, the address decoder determines the target atomic register corresponding to the access request, the target address in the target atomic register, and the operation type in the register file unit based on the parsing result. The operation type includes at least atomic increment 1, atomic decrement 1, atomic swap to 0, and atomic swap to 1.

[0081] Step S120: The control logic and sequencer execute atomic operations in an orderly manner based on the target atomic register, the target address, and the operation type.

[0082] In this embodiment, the address decoder can send the target atomic register and target address to the control logic and sequencer. The control logic and sequencer executes according to a first-in, first-out (FIFO) order. When executing the target atomic register, the control logic and sequencer performs atomic operations in an orderly manner based on the target atomic register, target address, and operation type. Specifically, if there are other unprocessed access requests, the corresponding atomic operations are executed sequentially based on the reception time of each access request. That is, the atomic operations corresponding to each access request are executed sequentially according to the order of reception time to achieve orderly execution of each atomic operation. Of course, if there are no other unprocessed access requests, the control logic and sequencer directly executes the atomic operation corresponding to that access request. Atomic operations include atomic increment (1), atomic decrement (1), atomic swap to 0, or atomic swap to 0.

[0083] In one feasible implementation, the target address includes the register address corresponding to the atomic increment operation, the operation type includes the atomic increment operation, and step S120 may include steps S121~S123:

[0084] Step S121: Perform a read operation on the target address of the target atomic register through the control logic and sequencer to obtain the first read result;

[0085] Step S122: Perform an atomic increment operation on the first read result through the arithmetic logic unit to obtain the first atomic operation result;

[0086] Step S123: Write the result of the first atomic operation to the target address of the target atomic register.

[0087] In this embodiment, when performing the atomic increment operation, the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain a first read result, and transmit the first read result to the arithmetic logic unit. The arithmetic logic unit performs an atomic increment operation on the first read result to obtain a first atomic operation result.

[0088] After obtaining the arithmetic logic unit, the result of the first atomic operation is written to the target address of the target atomic register to complete the atomic increment operation. This atomic increment operation is a read-only operation, meaning it can only be read first and then written; direct writing is not allowed.

[0089] In one feasible implementation, the target address includes the register address corresponding to the atomic increment operation, the operation type includes the atomic decrement operation, and step S120 may include steps S124~S126:

[0090] Step S124: Perform a read operation on the target address of the target atomic register through the control logic and sequencer to obtain the first read result;

[0091] Step S125: Perform an atomic increment operation on the first read result through the arithmetic logic unit to obtain the first atomic operation result;

[0092] Step S126: Write the result of the first atomic operation to the target address of the target atomic register.

[0093] In this embodiment, when performing the atomic decrement operation, the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain a second read result. The second read result is then transmitted to the arithmetic logic unit, which performs the atomic decrement operation on the second read result to obtain the second atomic operation result.

[0094] After obtaining the arithmetic logic unit, the result of the second atomic operation is written to the target address of the target atomic register to complete the atomic decrement operation. This atomic decrement operation is a read-only operation, meaning it can only be read first and then written; direct writing is not allowed.

[0095] In one feasible implementation, the operation type includes either an atom exchange of 0 or an atom exchange of 1, and step S120 may include steps S127-S128:

[0096] Step S127: If the target address includes the register address corresponding to an atomic swap of 0, then the control logic AND sequencer performs a read operation on the target address of the target atomic register to obtain a third read result, and writes 0 to the target address of the target atomic register; or,

[0097] Step S128: If the target address includes the register address corresponding to the atomic swap being 1, then the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain the fourth read result, and write 1 into the target address of the target atomic register.

[0098] In this embodiment, during the atomic swap operation, if the target address includes the register address corresponding to the atomic swap being 0, the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain a third read result, and write 0 into the target address of the target atomic register to realize the atomic operation of the atomic swap being 0.

[0099] If the target address includes the register address corresponding to the atomic swap being 1, then the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain the fourth read result, and write 1 into the target address of the target atomic register to realize the atomic operation of the atomic swap being 1.

[0100] It should be noted that atom swap of 0 and atom swap of 1 are read-only operations, meaning that you can only read first and then write, but you cannot write directly.

[0101] Step S130: If the interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, then the interrupt trigger information is sent to the interrupt signal generator.

[0102] In this embodiment, when the atomic operation is completed, the register value transformation information corresponding to the target address is obtained. The register value transformation information can be the difference between the register value after the atomic operation and the register value before the atomic operation. The interrupt control logic module can determine whether an interrupt is triggered at present through the register value transformation information, that is, whether the register value transformation information meets the preset interrupt conditions. If it meets the conditions, the interrupt trigger information is sent to the interrupt signal generator.

[0103] In one feasible implementation, the interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register; the interrupt triggering information includes lock release information and lock acquisition information; step S130 may include steps S131~S133:

[0104] Step S131: The value change detector determines register value transformation information based on the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation.

[0105] Step S132: If the register value change information is that the register value becomes 0, the value change detector determines that the register value change information meets the preset lock release interrupt condition, and the interrupt enable register sends the lock release information to the interrupt signal generator.

[0106] Step S133: If the register value change information is that the register value becomes 1, the value change detector determines that the register value change information meets the preset lock acquisition interrupt condition, and the interrupt enable register sends the lock acquisition information to the interrupt signal generator.

[0107] In this embodiment of the application, the interrupt triggering information may include lock release information and lock acquisition information. The value change detector acquires the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation, and determines the register value transformation information based on the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation. The register value transformation information may be the register value corresponding to the target address after the atomic operation minus the register value corresponding to the target address before the atomic operation.

[0108] After obtaining the register value change information, it is determined whether the register value change information is a register value becoming 0. If the register value change information is a register value becoming 0, then the interrupt trigger information is determined to be lock release information. At this time, the value change detector determines that the register value change information meets the preset lock release interrupt condition. The interrupt enable register sends the lock release information to the interrupt signal generator. Specifically, the interrupt target register determines the second target CPU to be sent the interrupt and sends the second target CPU to the interrupt signal generator. The interrupt signal generator generates the corresponding interrupt based on the lock release information and sends the interrupt corresponding to the lock release information to the CPU cluster to which the second target CPU belongs in each CPU cluster. The CPU cluster to which the second target CPU belongs sends the interrupt to the second target CPU so that the second target CPU can execute the interrupt.

[0109] If the register value change information is that the register value becomes 1, then the interrupt trigger information is determined to be lock acquisition information. At this time, the value change detector determines that the register value change information meets the preset lock acquisition interrupt condition. The interrupt enable register sends the lock acquisition information to the interrupt signal generator. Specifically, the interrupt target register determines the second target CPU to which the interrupt is sent and sends the second target CPU to the interrupt signal generator. The interrupt signal generator generates the corresponding interrupt based on the lock acquisition information and sends the interrupt corresponding to the lock acquisition information to the CPU cluster to which the second target CPU belongs in each CPU cluster. The CPU cluster to which the second target CPU belongs sends the interrupt to the second target CPU so that the second target CPU can execute the interrupt.

[0110] In one feasible implementation, the interruption triggering information includes resource availability notification and lock state change notification; step S130 may include steps S134~S135:

[0111] Step S134: If the register value change information is that the register value changes from 0 to non-zero, the value change detector determines that the register value change information meets the preset resource interruption condition, and the interrupt enable register sends a resource availability notification to the interrupt signal generator.

[0112] Step S135: If the register value change information is that the register value changes from 1 to 0, the value change detector determines that the register value change information meets the preset lock state change interrupt condition, and the interrupt enable register sends the lock state change notification to the interrupt signal generator.

[0113] In this embodiment of the application, the interruption triggering information may include resource availability notification and lock state change notification.

[0114] If the register value change information is a change from 0 to non-zero, then the interrupt trigger information is determined to be a resource availability notification. At this time, the value change detector determines that the register value change information meets the preset resource interrupt conditions. The interrupt enable register sends the resource availability notification to the interrupt signal generator. Specifically, the interrupt target register determines the second target CPU for interrupt transmission and sends the second target CPU to the interrupt signal generator. The interrupt signal generator generates the corresponding interrupt based on the resource availability notification and sends the interrupt corresponding to the resource availability notification to the CPU cluster to which the second target CPU belongs in each CPU cluster. The CPU cluster to which the second target CPU belongs sends the interrupt to the second target CPU so that the second target CPU can execute the interrupt.

[0115] If the register value change information is a change from 1 to 0, then the interrupt trigger information is determined to be a lock state change notification. At this time, the value change detector determines that the register value change information meets the preset lock state change interrupt condition. The interrupt enable register sends the lock state change notification to the interrupt signal generator. Specifically, the interrupt target register determines the second target CPU for interrupt transmission and sends the second target CPU to the interrupt signal generator. The interrupt signal generator generates the corresponding interrupt based on the lock state change notification and sends the interrupt corresponding to the lock state change notification to the CPU cluster to which the second target CPU belongs in each CPU cluster. The CPU cluster to which the second target CPU belongs sends the interrupt to the second target CPU so that the second target CPU can execute the interrupt.

[0116] It should be noted that the interrupt status register is used to record the triggered interrupt conditions and clear the corresponding bit by writing 1. For example, after the interrupt signal generator sends the interrupt corresponding to the lock state change notification to the second target CPU, the interrupt status register writes the data of the corresponding bit to 1.

[0117] It should be noted that the interrupt enable register includes various interrupt enable functions. For example, the interrupt enable register can be a 32-bit configuration register with the following bit definitions: [0]: interrupt enable when the value changes to 0, [1]: interrupt enable when the value changes to 1, [2]: interrupt enable when the value changes from 0 to non-zero, [3]: interrupt enable when the value changes from 1 to 0, [31:4]: reserved. The interrupt enable register triggers the corresponding interrupt enable function based on the register value change information of the value change detector. The interrupt target register determines the second target CPU based on the interrupt enable function of the interrupt enable register.

[0118] Step S140: The interrupt signal generator generates a corresponding interrupt based on the interrupt trigger information and sends the interrupt to the second target CPU corresponding to the interrupt trigger information.

[0119] In this embodiment of the application, after receiving the interrupt trigger information, the interrupt signal generator generates a corresponding interrupt according to the interrupt trigger information and sends the interrupt to the second target CPU corresponding to the interrupt trigger information. Specifically, the interrupt signal generator can send the interrupt to the CPU cluster to which the second target CPU belongs in each CPU cluster. The CPU cluster to which the second target CPU belongs sends the interrupt to the second target CPU so that the second target CPU can execute the interrupt.

[0120] In this embodiment, all atomic operations are implemented in hardware within the atomic operation register module, fundamentally avoiding race conditions and correctness issues inherent in software solutions. An interrupt-driven waiting mechanism replaces polling, allowing the CPU waiting for the lock to enter a low-power state, freeing up CPU cycles for other computational tasks and improving overall system performance. This eliminates numerous state query accesses, reduces bus bandwidth usage, and provides more resources for critical data transmission. It also supports various atomic operations (read, add, subtract, swap) and interrupt triggering conditions, adapting to different synchronization scenarios. The hardware interrupt mechanism provides deterministic wake-up latency, ensuring real-time requirements are met. Furthermore, software developers do not need to understand complex lock-free programming; efficient cross-cluster synchronization can be achieved through simple memory access.

[0121] It should be noted that the arithmetic logic unit in this embodiment can also support atomic bit operations (AND, OR, XOR) or comparison-swap operations; the interrupt signal generator can be extended to support the MSI mechanism, transmitting interrupts via memory writes to adapt to modern interconnect standards such as PCIe. A programmable suppression timer can also be added to prevent the same interrupt from being repeatedly triggered in a short period, effectively avoiding interrupt storms. The atomic operation register module can work in conjunction with the system-level power management unit to automatically wake up CPU cores in deep sleep when an interrupt is triggered. A statistical register can also be added for performance monitoring, recording metrics such as the number of interrupt triggers and average wait time, providing data support for system performance analysis and optimization. This application can support triggering interrupts based on conditional logic combinations of multiple atomic registers, implementing more complex synchronous notification mechanisms.

[0122] In one feasible implementation, such as Figure 5 As shown, the atomic operation register module further includes a first selector, the address decoder includes an atomic register address decoder, and the register file unit includes atomic registers.

[0123] The atomic register address decoder is communicatively connected to the AXI bus interface and the control logic and sequencer, respectively; the atomic register is communicatively connected to the selection unit of each atomic operation in the control logic and sequencer through the first selector.

[0124] It should be noted that a register file unit can set multiple atomic registers.

[0125] Among them, such as Figure 5 As shown, the selection units for each atomic operation in the control logic and sequencer include ADD1, SUB1, SWAP0, SWAP1, and LOAD. Among them, ADD1 is the selection unit for the atomic increment operation in the control logic and sequencer, SUB1 is the selection unit for the atomic decrement operation in the control logic and sequencer, SWAP0 is the selection unit for the atomic swap to 0 in the control logic and sequencer, SWAP1 is the selection unit for the atomic swap to 1 in the control logic and sequencer, and LOAD is the selection unit for the interrupt register in the control logic and sequencer.

[0126] In this embodiment, the atomic register address decoder parses the access request received by the AXI bus interface, determines the target atomic register from multiple atomic registers based on the parsing result, and determines the target address and operation type in the target atomic register. It then determines the selection unit that will communicate with the target atomic register, and filters the corresponding unit based on the operation type. For example, it selects a corresponding unit from ADD1, SUB1, SWAP0, SWAP1, and LOAD. Finally, the selected unit performs an atomic operation on the atomic register (target atomic register) according to the target address, i.e., reads the data at the target address.

[0127] It should be noted that, as Figure 5 As shown, the access request in this embodiment may include register read data, register address, register write enable, and register write data.

[0128] In one feasible implementation, such as Figure 5 As shown, the atomic operation register module further includes a second selector and a third selector; the interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register.

[0129] The second selector is communicatively connected to both the atomic register and the third selector.

[0130] The value change detector is communicatively connected to the atomic register;

[0131] The interrupt enable register is communicatively connected to the value change detector and the second selector, respectively.

[0132] The interrupt status register is communicatively connected to the value change detector, the second selector, and the third selector, respectively.

[0133] The interrupt target register is communicatively connected to the second selector and the third selector, respectively;

[0134] The third selector is connected to each CPU in the CPU cluster.

[0135] In this embodiment, the second selector is communicatively connected to the atomic register, the interrupt enable register, the interrupt status register, and the interrupt target register, respectively. The second selector can be used to select and read data from any one of the atomic register, the interrupt enable register, the interrupt status register, and the interrupt target register for output.

[0136] The value change detector communicates with each atomic register to detect changes in the register values. Based on these changes, it determines whether an interrupt condition is met. When the change meets the corresponding interrupt condition, the interrupt enable register sends the corresponding interrupt information to the interrupt signal generator, generating an enable signal (interrupt information) for the corresponding interrupt. The interrupt signal generator then generates the corresponding interrupt signal based on this interrupt information. Simultaneously, when the register value change meets the corresponding interrupt condition, the interrupt status register records that interrupt condition. The interrupt target register configures the target CPU core (e.g., a second target CPU) for interrupt transmission based on the access request and sends the target CPU core to the interrupt signal generator. The interrupt signal generator selects the core corresponding to the target CPU core (i.e., the second target CPU) through a third selector and sends the interrupt signal to that second target CPU. Figure 5 As shown, a CPU core may include INT_0, INT_1, INT_2, ..., INT_N.

[0137] It should be noted that the interrupt enable register, interrupt status register, and interrupt target register are all connected to the AXI bus interface. The interrupt target register determines the target CPU core for interrupt transmission based on the access request.

[0138] In one feasible implementation, such as Figure 5 As shown, the atomic operation register module further includes a register read address decoder; the address decoder further includes an interrupt register address decoder;

[0139] The interrupt register address decoder is communicatively connected to the AXI bus interface, the interrupt enable register, the interrupt status register, and the interrupt target register, respectively.

[0140] The register read address decoder is communicatively connected to the AXI bus interface and the second selector, respectively.

[0141] In this embodiment, as Figure 5 As shown, the interrupt register address decoder can parse the access request received by the AXI bus interface and determine whether to enable the interrupt enable register, the interrupt status register, and the interrupt target register based on the parsing result.

[0142] The register read address decoder can decode and parse the access requests received by the AXI bus interface. Based on the decoding and parsing results, it determines whether it is necessary to read data from the atomic register interrupt enable register, interrupt status register, or interrupt target register through the second selector. That is, based on the decoding and parsing results of the register read address decoder, the second selector selects to read data from any one of the atomic register, interrupt enable register, interrupt status register, and interrupt target register for output.

[0143] This embodiment provides a method for executing atomic operations. When an access request is received from a first target CPU in a CPU cluster via an AXI bus interface, the target atomic register corresponding to the access request and the target address in the target atomic register are determined in the register file unit by an address decoder. Then, the control logic and sequencer execute atomic operations based on the target atomic register and the target address. Subsequently, the interrupt control logic module determines that the register value change information corresponding to the target address meets a preset interrupt condition, and then sends interrupt trigger information to the interrupt signal generator. The interrupt signal generator then generates a corresponding interrupt based on the interrupt trigger information and sends the interrupt to the second target CPU corresponding to the interrupt trigger information. By setting multiple atomic registers in the atomic operation register module, atomic operations are implemented through atomic registers. All atomic operations are implemented in hardware within the module. Different atomic operations are directly accessed through address decoding, realizing the hardware fusion of multi-address mapping atomic operations and interrupt generation. The atomic operation registers and interrupt control logic are tightly integrated at the hardware level, and interrupts are automatically generated when values ​​change, achieving atomic synchronization across CPU clusters.

[0144] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the execution method of the atomic operations of this application. Any simple transformations based on this technical concept are within the protection scope of this application.

[0145] This application provides an atomic operation execution device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the atomic operation execution method in the above embodiment 1.

[0146] The following is for reference. Figure 4This document illustrates a schematic diagram of an execution device suitable for implementing atomic operations in the embodiments of this application. The execution device for atomic operations in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 4 The apparatus for executing atomic operations shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0147] like Figure 4 As shown, the execution device for atomic operations may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the execution device for atomic operations. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the atomic operation execution device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows atomic operation execution devices with various systems, it should be understood that it is not required to implement or possess all of the systems shown. More or fewer systems may be implemented alternatively.

[0148] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0149] The atomic operation execution device provided in this application, employing the atomic operation execution method in the above embodiments, can solve the technical problem of how to achieve atomic synchronization across CPU clusters. Compared with the prior art, the beneficial effects of the atomic operation execution device provided in this application are the same as those of the atomic operation execution method provided in the above embodiments, and other technical features in this atomic operation execution device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0150] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0151] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0152] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to perform the execution method of the atomic operations in the above embodiments.

[0153] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0154] The aforementioned computer-readable storage medium may be included in an atomic operation execution device; or it may exist independently and not assembled into an atomic operation execution device.

[0155] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by an atomic operation execution device, the atomic operation execution device: upon receiving an access request from a first target CPU in a CPU cluster via an AXI bus interface, determines the target atomic register, the target address in the target atomic register, and the operation type corresponding to the access request in a register file unit via an address decoder; executes atomic operations in an orderly manner based on the target atomic register, the target address, and the operation type via the control logic and sequencer; determines, via an interrupt control logic module, that the register value transformation information corresponding to the target address meets a preset interrupt condition, and then sends interrupt trigger information to an interrupt signal generator; and generates a corresponding interrupt based on the interrupt trigger information via the interrupt signal generator, and sends the interrupt to the second target CPU corresponding to the interrupt trigger information.

[0156] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0157] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0158] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0159] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described atomic operation method, thereby solving the technical problem of how to achieve atomic synchronization across CPU clusters. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the atomic operation execution method provided in the above embodiments, and will not be repeated here.

[0160] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the execution method of atomic operations as described above.

[0161] The computer program product provided in this application solves the technical problem of how to achieve atomic synchronization across CPU clusters. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the atomic operation execution method provided in the above embodiments, and will not be repeated here.

[0162] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for performing atomic operations, characterized in that, It is applied to an atomic operation register module, which includes an AXI bus interface, an address decoder, control logic and a sequencer, a register file unit, an arithmetic logic unit, an interrupt control logic module, and an interrupt signal generator; The AXI bus interface of the atomic operation register module is electrically connected to each CPU cluster via the AXI bus. The execution method of the atomic operation includes: When an access request is received from the first target CPU in the CPU cluster via the AXI bus interface, the target atomic register, the target address in the target atomic register, and the operation type are determined in the register file unit by the address decoder. The control logic and sequencer execute atomic operations in an orderly manner based on the target atomic register, the target address, and the operation type. If the interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, then it sends interrupt trigger information to the interrupt signal generator. An interrupt is generated based on the interrupt triggering information by an interrupt signal generator, and the interrupt is sent to the second target CPU corresponding to the interrupt triggering information. The interrupt control logic module includes a value change detector, an interrupt enable register, and an interrupt status register; the interrupt triggering information includes resource availability notification and lock status change notification. The interrupt control logic module determines that the register value change information corresponding to the target address meets the preset interrupt conditions, and then sends the interrupt trigger information to the interrupt signal generator. The steps include: The value change detector determines register value transformation information based on the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation; If the register value change information is that the register value changes from 0 to non-zero, the value change detector determines that the register value change information meets the preset resource interruption condition, and the interrupt enable register sends a resource availability notification to the interrupt signal generator. If the register value change information is that the register value changes from 1 to 0, the value change detector determines that the register value change information meets the preset lock state change interrupt condition, and the interrupt enable register sends the lock state change notification to the interrupt signal generator.

2. The method for performing atomic operations as described in claim 1, characterized in that, The target address includes the register address corresponding to the atomic increment operation, the operation type includes the atomic increment operation, and the step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes: The first read result is obtained by performing a read operation on the target address of the target atomic register through the control logic and sequencer. The arithmetic logic unit performs an atomic increment operation on the first read result to obtain the first atomic operation result; The result of the first atomic operation is written to the target address of the target atomic register.

3. The method for performing atomic operations as described in claim 1, characterized in that, The target address includes the register address corresponding to the atomic decrement operation, the operation type includes the atomic decrement operation, and the step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes: The second read result is obtained by performing a read operation on the target address of the target atomic register through the control logic and sequencer. The arithmetic logic unit performs an atomic decrement operation on the second read result to obtain the second atomic operation result; The result of the second atomic operation is written to the target address of the target atomic register.

4. The method for performing atomic operations as described in claim 1, characterized in that, The operation type includes atomic swap 0 or atomic swap 1. The step of sequentially executing atomic operations based on the target atomic register, the target address, and the operation type through the control logic and sequencer includes: If the target address includes the register address corresponding to an atomic swap of 0, then the control logic and sequencer perform a read operation on the target address of the target atomic register, obtain a third read result, and write 0 to the target address of the target atomic register; or, If the target address includes the register address corresponding to an atomic swap of 1, then the control logic and sequencer perform a read operation on the target address of the target atomic register to obtain the fourth read result, and write 1 into the target address of the target atomic register.

5. The method for performing atomic operations as described in claim 1, characterized in that, The interrupt triggering information includes lock release information and lock acquisition information; after the step of the value change detector determining the register value change information based on the register value corresponding to the target address before the atomic operation and the register value corresponding to the target address after the atomic operation, the execution method of the atomic operation further includes: If the register value change information is that the register value becomes 0, the value change detector determines that the register value change information meets the preset lock release interrupt condition, and the interrupt enable register sends the lock release information to the interrupt signal generator. If the register value change information is that the register value becomes 1, the value change detector determines that the register value change information meets the preset lock acquisition interrupt condition, and the interrupt enable register sends the lock acquisition information to the interrupt signal generator.

6. The method for performing atomic operations as described in claim 1, characterized in that, When an access request is received from the first target CPU in the CPU cluster via the AXI bus interface, the steps of determining the target atomic register corresponding to the access request, the target address in the target atomic register, and the operation type in the register file unit through the address decoder include: The address decoder receives the access request sent by the first target CPU through the AXI bus interface; The address decoder parses the access request to obtain the parsing result; The address decoder determines the target atomic register corresponding to the access request in the register file unit based on the parsing result, and determines the target address and operation type in the target atomic register based on the parsing result.

7. The method for performing atomic operations as described in any one of claims 1 to 6, characterized in that, The atomic operation register module further includes a first selector, the address decoder includes an atomic register address decoder, and the register file unit includes atomic registers; The atomic register address decoder is communicatively connected to the AXI bus interface and the control logic and sequencer, respectively. The atomic register is communicatively connected to the selection units of each atomic operation in the control logic and sequencer through the first selector.

8. The method for performing atomic operations as described in claim 7, characterized in that, The atomic operation register module further includes a second selector and a third selector; the interrupt control logic module includes a value change detector, an interrupt enable register, an interrupt status register, and an interrupt target register; The second selector is communicatively connected to both the atomic register and the third selector. The value change detector is communicatively connected to the atomic register; The interrupt enable register is communicatively connected to the value change detector and the second selector, respectively. The interrupt status register is communicatively connected to the value change detector, the second selector, and the third selector, respectively. The interrupt target register is communicatively connected to the second selector and the third selector, respectively; The third selector is connected to each CPU in the CPU cluster.

9. The method for performing atomic operations as described in claim 8, characterized in that, The atomic operation register module further includes a register read address decoder; the address decoder further includes an interrupt register address decoder; The interrupt register address decoder is communicatively connected to the AXI bus interface, the interrupt enable register, the interrupt status register, and the interrupt target register, respectively. The register read address decoder is communicatively connected to the AXI bus interface and the second selector, respectively.

Images