Image data analysis and storage system

Abstract

The utility model discloses an image data analysis and storage system, which comprises an image input interface, a feature extraction module, a decision module, a data buffer module and a storage control module, the image input interface is connected with the video processor of the feature extraction module; the feature extraction module extracts image features through a feature detection circuit based on a comparator, and generates a control signal through the decision module; and the control signal controls an address decoder in the storage control module, so that a data stream is automatically guided to a solid-state memory or a disk memory through a data gating switch. According to the utility model, analysis and shunt storage of image data are realized through a hardware circuit, and the system has the advantages of determined delay, high efficiency and no need of software intervention.

Description

Technical Field

[0001] This utility model relates to the field of data storage and processing technology, specifically an image data analysis and storage system. Background Technology

[0002] With the rapid development of artificial intelligence and image processing technologies, the demand for real-time analysis and storage of massive amounts of image data is increasing. In professional scenarios such as industrial inspection and security monitoring, systems not only require high throughput, but also have stringent requirements for deterministic response time and predictable behavior.

[0003] However, current mainstream image storage systems generally adopt a software architecture based on general-purpose processors. This type of architecture implements data analysis and storage functions within a software stack, and its processing latency and behavior inherently depend on the operating system's task scheduling, interrupt response, and software process state. These factors have inherent uncertainty and unpredictability, making it difficult for the system to provide deterministic real-time guarantees. Furthermore, this type of architecture typically lacks a mechanism to complete data distribution at the moment of data generation, failing to select the optimal storage medium in real time based on the physical characteristics of the image content (such as motion and edges), resulting in an imbalance between storage performance and cost.

[0004] Some existing improvement solutions (such as data migration through background service programs) attempt to optimize storage in terms of strategy, but their implementation is still based on the above-mentioned software architecture. Therefore, they are unable to overcome the underlying uncertainty problems and may introduce new latency fluctuations due to additional software overhead.

[0005] Therefore, existing technologies lack a data storage structure that can fundamentally avoid software stack uncertainties and achieve analysis and distribution based on the timing of the hardware circuit itself. There is an urgent need for an image data analysis and storage system that achieves deterministic and predictable automatic selection of storage paths through a hardware structure that coordinates hard-wired logic and signal flow. Utility Model Content

[0006] The purpose of this utility model is to overcome the shortcomings of the prior art and provide an image data analysis and storage system, including: an image input interface, a feature extraction module, a decision module, a data buffer module, and a storage control module;

[0007] The feature extraction module includes a video processor and a feature detection circuit; the analog video input terminal of the video processor is connected to the analog video output terminal of the image input interface, and the digital video data output terminal of the video processor is connected to the data input terminal of the data buffer module; the input terminal of the feature detection circuit is connected to the output terminal of the video processor, the feature signal output terminal of the feature detection circuit is connected to the input terminal of the decision module, the output terminal of the decision module is connected to the enable input terminal of the storage control module, and the output terminal of the data buffer module is connected to the data input terminal of the storage control module.

[0008] Preferably, the feature detection circuit includes a brightness detection circuit, a motion detection circuit, and an edge detection circuit; the input terminals of the brightness detection circuit and the edge detection circuit are respectively connected to the brightness signal output terminal of the video processor, the input terminal of the motion detection circuit is connected to the digital video data output terminal of the video processor, and the output terminals of the brightness detection circuit, the motion detection circuit, and the edge detection circuit are respectively connected to the input terminal of the decision module.

[0009] Preferably, the motion detection circuit includes a dual-channel FIFO memory, a motion detector, and a first operational amplifier; the 8-bit digital video data output terminal of the video processor is connected to the data input terminal of the dual-channel FIFO memory; the first channel data output terminal of the dual-channel FIFO memory is connected to the non-inverting input terminal of multiple comparators in the motion detector, and its second channel data output terminal is connected to the inverting input terminal of the multiple comparators; the output terminals of the multiple comparators are connected to the input terminal of a multi-input OR gate, the output terminal of the OR gate is connected to the non-inverting input terminal of the first operational amplifier, and the inverting input terminal of the first operational amplifier is connected to its output terminal;

[0010] The edge detection circuit includes an edge density detector; the luminance signal output terminal of the video processor is connected to the non-inverting input terminal of the edge density detector via a fifth resistor and a first capacitor connected in series; the inverting input terminal of the edge density detector is connected to a voltage divider node composed of a third resistor and a fourth resistor connected in series, and the voltage divider node is connected between the power supply and ground.

[0011] The brightness detection circuit includes a brightness comparator; the brightness signal output terminal of the video processor is connected to the non-inverting input terminal of the brightness comparator; the inverting input terminal of the brightness comparator is connected to a voltage divider node composed of a first resistor and a second resistor connected in series, and the voltage divider node is connected between the power supply and ground; the output terminals of the first operational amplifier, the edge density detector, and the brightness comparator are respectively connected to the three independent input terminals of the decision module.

[0012] Preferably, the storage control module includes a storage controller, a first storage medium, a second storage medium, a data gating switch, and an address decoder; the data output terminal of the data buffer module is connected to the data input terminal of the storage controller, the empty signal output terminal of the data buffer module is connected to the read enable input terminal of the storage controller, and the count output terminal of the data buffer module is connected to the address input terminal of the address decoder; the data output terminal of the storage controller is connected to the input terminal of the data gating switch; the output terminal of the address decoder is connected to the control terminal of the data gating switch; the output terminal of the decision module is connected to the enable input terminal of the address decoder; the first output terminal of the data gating switch is connected to the input terminal of the first storage medium, and the second output terminal of the data gating switch is connected to the input terminal of the second storage medium.

[0013] Preferably, the decision module includes a feature encoder and a logic circuit; the outputs of the first operational amplifier, the edge density detector, and the brightness comparator are respectively connected to the three independent inputs of the feature encoder, the output of the feature encoder and the vertical synchronization signal output of the video processor are respectively connected to the two inputs of the logic circuit, and the output of the logic circuit is connected to the enable input of the address decoder.

[0014] Preferably, the feature encoder is a priority encoder, and the logic circuit is an AND gate chip; the encoding output terminal of the feature encoder is connected to one input terminal of the AND gate chip, the vertical synchronization signal output terminal of the video processor is connected to the other input terminal of the AND gate chip; the output terminal of the AND gate chip is connected to the enable input terminal of the address decoder.

[0015] Preferably, the data buffer module includes a data buffer and an address generator; the data input terminal of the data buffer is connected to the digital video data output terminal of the video processor; the full signal output terminal of the data buffer is connected to the data flow control terminal of the video processor, and its empty signal output terminal is connected to the read enable input terminal of the storage controller; the data output terminal of the data buffer is connected to the parallel data input terminal of the storage controller; the clock input terminal of the address generator is connected to the pixel clock output terminal of the video processor, and its count output terminal is connected to the address input terminal of the address decoder.

[0016] Preferably, it further includes an address mapping unit; the address mapping unit includes a programmable read-only memory, the address input terminal of the programmable read-only memory is connected to the counting output terminal of the data buffer module, and the data output terminal of the programmable read-only memory is connected to the address input terminal of the address decoder.

[0017] Preferably, the storage controller is a SATA bridge controller chip.

[0018] Preferably, the first storage medium is a solid-state drive, and the second storage medium is a disk drive.

[0019] The beneficial effects of this invention are: 1. It achieves deterministic hardware-level real-time analysis and load balancing. By transforming image feature extraction into parallel comparison operations of analog / digital hardware, and simplifying the decision logic to fixed connections with basic logic devices such as gates and encoders, this system establishes a hard-wired data processing path from pixel input to storage medium without any program branches. The delay of this path is determined only by the physical characteristics of the devices and the signal propagation delay, and is constant and accurately measurable. This fundamentally solves the fundamental problem of behavioral uncertainty and delay drift caused by scheduling and branch prediction in software solutions.

[0020] 2. A hardware-based hierarchical storage mechanism based on the physical characteristics of content is provided. The system uses hardware circuitry to generate control signals based on the direct physical characteristics of image signals in brightness, frequency (edges), and temporal variations (motion), thereby enabling the selection of storage media. This method of directly mapping data physical characteristics to storage physical addresses is a native hardware data classification method, unlike the post-processing mode in software solutions that first identify semantics and then logically classify data. It is more efficient and completes simultaneously with data generation.

[0021] 3. It boasts high reliability and extremely low resource consumption. The entire system is composed of dedicated hardware modules, operating independently of general-purpose processors and operating systems, eliminating software overhead and crash risks, and ensuring high stability. Furthermore, its data processing and distribution tasks are completed independently, without consuming host computing resources, making it particularly suitable for high real-time and high-reliability embedded or dedicated image processing scenarios. Attached Figure Description

[0022] Figure 1 This is a system architecture diagram of an image data analysis and storage system;

[0023] Figure 2 This is a schematic diagram illustrating the working process of one embodiment of the present invention;

[0024] Figure 3 This is a circuit structure diagram of one embodiment of the data buffer module and storage control module of this utility model;

[0025] Figure 4 This is a circuit diagram of one embodiment of the feature extraction module of this utility model;

[0026] Figure 5 This is a circuit structure diagram of one embodiment of the decision module of this utility model;

[0027] Figure 6This is a circuit structure diagram of one embodiment of the crystal oscillator circuit of this utility model;

[0028] Figure 7 This is a circuit diagram illustrating one embodiment of the address mapping unit of this utility model.

[0029] Figure Labels

[0030] U1 is the image input interface, U2 is the video processor; G1 is the feature encoder, G2 is the AND gate chip, G4 is the inverter; M1 is the data buffer, M2 is the programmable read-only memory, M3 is the dual-channel FIFO memory, M4 is the solid-state drive, M5 is the disk drive; C1 is the brightness comparator, C2 is the motion detector, C3 is the edge density detector, C4 is the first operational amplifier; A1 is the address generator, A2 is the address decoder; K1 is the storage controller, K2 is the data strobe switch; R1 is the first resistor, R2 is the second resistor, R3 is the third resistor, R4 is the fourth resistor, R5 is the fifth resistor; Cc1 is the first capacitor, Cx and Cy are surface-mount capacitors, VSYNC is the vertical synchronization signal, Y_OUT is the brightness signal, A is the motion detection signal, B is the edge detection signal, and C is the brightness detection signal. Detailed Implementation

[0031] The technical solution of this utility model is described in further detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to the following description.

[0032] Example 1

[0033] like Figure 1 As shown, an image data analysis and storage system includes: an image input interface U1, a feature extraction module, a decision module, a data buffer module, and a storage control module;

[0034] The feature extraction module includes a video processor U2 and a feature detection circuit; the analog video input terminal of the video processor U2 is connected to the analog video output terminal of the image input interface U1, and the digital video data output terminal of the video processor U2 is connected to the data input terminal of the data buffer module; the input terminal of the feature detection circuit is connected to the output terminal of the video processor U2, the feature signal output terminal of the feature detection circuit is connected to the input terminal of the decision module, the output terminal of the decision module is connected to the enable input terminal of the storage control module, and the output terminal of the data buffer module is connected to the data input terminal of the storage control module.

[0035] After system startup, the image input interface U1 acquires external image data, and its analog video output transmits the signal to the analog video input of the video processor U2 in the feature extraction module. The video processor U2 processes and converts the input signal, and its digital video data output outputs the image data to the data input of the data buffer module for temporary storage. Simultaneously, the output of the video processor U2 provides an analysis signal to the feature detection circuit, which extracts image features and sends the feature information to the input of the decision module through its feature signal output. The decision module analyzes and makes a decision on the feature information, generating a storage control enable signal at its output and transmitting it to the enable input of the storage control module to trigger the storage operation. When enabled, the data buffer module outputs its temporarily stored image data to the data input of the storage control module, completing the entire process of image data acquisition, analysis, buffering, and controlled storage.

[0036] This embodiment provides a specific implementation of an image data analysis and storage system. Based on a collaborative architecture of image input, feature extraction, decision control, data buffering, and hierarchical storage, the system realizes the entire process from image acquisition to intelligent storage. Specifically, the feature extraction module, through its internal video processor and feature detection circuit, performs image data format conversion, temporary storage, and feature analysis in parallel, providing a crucial information foundation for subsequent intelligent decision-making and classification storage. The system has a clear design structure and well-defined signal flow, ensuring high efficiency in data processing and reliable storage control.

[0037] Example 2

[0038] This embodiment provides a specific implementation of the data buffer module and storage control module based on embodiment 1.

[0039] The image input interface U1 uses an OV7670 image sensor.

[0040] Feature extraction module: The video processor U2 uses a TVP5150 video decoder chip; the feature detection circuit includes a brightness detection circuit, a motion detection circuit, and an edge detection circuit; the input terminals of the brightness detection circuit and the edge detection circuit are respectively connected to the brightness signal output terminal of the video processor U2, the input terminal of the motion detection circuit is connected to the digital video data output terminal of the video processor U2, and the output terminals of the brightness detection circuit, the motion detection circuit, and the edge detection circuit are respectively connected to the input terminal of the decision module.

[0041] Decision module: includes feature encoder G1 and logic circuit; feature encoder G1 adopts priority encoder, and 74LVC148 priority encoder chip can be selected; the output terminal of feature detection circuit is connected to the input terminal of feature encoder G1, and the output terminal of feature encoder G1 and the vertical synchronization signal output terminal of video processor U2 are respectively connected to the two input terminals of the logic circuit.

[0042] like Figure 3 As shown, the data buffer module includes a data buffer M1 and an address generator A1. Data buffer M1 uses an IDT7202 FIFO memory chip. Address generator A1 uses four cascaded 74LVC161 binary counter chips to form a 16-bit address generator, with each chip responsible for 4-bit binary counting. The carry output of the preceding chip is connected to the count enable of the following chip. The clock inputs of all chips are connected in parallel to the pixel clock output of the video processor U2, and the clear input is connected to a 3.3V high level to maintain continuous counting. The digital video data output of the video processor U2 is connected to the data input of data buffer M1, the clock input of address generator A1 is connected to the pixel clock output of video processor U2, and the full signal output of data buffer M1 is connected to the data flow control of video processor U2.

[0043] like Figure 3 As shown, the storage control module includes a storage controller K1, a first storage medium, a second storage medium, a data strobe switch K2, and an address decoder A2. The storage controller K1 uses a JMB575 SATA bridge controller chip. The first and second storage media are a solid-state drive M4 and a disk drive M5, respectively. The solid-state drive M4 is a SATA interface solid-state drive; the disk drive M5 is a SATA interface hard disk drive. The data strobe switch K2 uses a dedicated multiplexer chip (such as the MAX4888B) that supports 3.0Gbps SATA differential signals to ensure the integrity and timing stability of high-speed serial signal switching. The address decoder A2 uses a 74LVC138 decoder chip. In the decision module, the output of the logic circuit is connected to the enable terminal of the address decoder A2, the data output of the data buffer M1 is connected to the parallel data input of the storage controller K1, the empty signal output of the data buffer M1 is connected to the read enable input of the storage controller K1, the count output of the address generator A1 is connected to the address signal input of the address decoder A2, the SATA data output of the storage controller K1 is connected to the common input of the data gating switch K2, the output of the address decoder A2 is connected to the control terminal of the data gating switch K2, the first output of the data gating switch K2 is connected to the data input of the solid-state drive M4, and the second output of the data gating switch K2 is connected to the data input of the disk drive M5.

[0044] Before use, the video processor U2 and the storage controller K1 are set to a predetermined working mode through their respective configuration ports (such as I2C and configuration pins), so that after power-on, they can directly output digital video streams that meet the system requirements and perform SATA bridging conversion functions without the need for real-time configuration by an external processor.

[0045] It also includes a system clock module and a power supply module. The system clock module uses a crystal oscillator circuit to provide the operating clock for the video processor U2. The power supply module uses an AMS1117-3.3V voltage regulator chip to convert the 12V voltage input from the external adapter into a stable 3.3V system operating voltage. In the attached diagram, this 3.3V power supply is indicated by the '3.3V' network label. The power ports of all core components, including the image input interface U1, video processor U2, feature detection circuit, and feature encoder G1, are connected to this 3.3V power supply network. All modules share a common ground, and the input terminal of the power supply module is connected to the 12V external adapter.

[0046] After the system starts up, the power module outputs 3.3V to power the core components, such as... Figure 2 As shown, the system clock module provides a stable operating clock for the video processor U2 through a crystal oscillator circuit. The image input interface U1 acquires analog video signals and transmits them to the analog video input terminal of the video processor U2, where the video processor U2 performs the decoding and conversion from analog video to digital video.

[0047] The decoded data is output by the video processor U2 in two signals: one is 8-bit digital video data, which is input to the motion detection circuit in the feature detection circuit and simultaneously stored in the data buffer M1; the other is a luminance signal Y_OUT, which is input to both the luminance detection circuit and the edge detection circuit in the feature detection circuit. The output signals of the luminance detection circuit, motion detection circuit, and edge detection circuit are all connected to the feature encoder G1 of the decision module to complete feature encoding. Simultaneously, the address generator A1, driven by the pixel clock of the video processor U2, outputs an incrementing physical address signal to the address input terminal of the address decoder A2. When the data buffer M1 is about to be full, its full signal is fed back to the data flow control terminal of the video processor U2, and the video processor U2 pauses data output to avoid overflow.

[0048] Once data buffer M1 is ready, its empty signal triggers the read enable of storage controller K1. Storage controller K1 performs the core operation: converting the parallel image data in data buffer M1 into a SATA data stream and outputting it to the common input of data strobe switch K2. Simultaneously, the physical address signal generated by address generator A1 is continuously sent to the address input of address decoder A2. When the image contains valid features and is in frame synchronization, the decision module internally processes the output of feature encoder G1 and the vertical synchronization signal VSYNC of video processor U2 to generate a storage enable signal, which is then sent to the enable terminal of address decoder A2.

[0049] The address decoder A2 is instantaneously activated only when the hardware enable pulse from the decision module is valid, decoding the signals on the address bus. The decoded output signal serves as the physical layer control level, directly driving the channel switching of the data gating switch K2. This series of actions (enabling, decoding, and gating) is continuous and without intermediate states at the hardware logic level, forming a 'one-time' hard decision on the direction of the data flow. This ensures the absolute determinism of the storage path selection, thereby automatically guiding the SATA data stream output by the storage controller K1 to the designated storage medium determined by the address (i.e., the address decoding result gating the solid-state drive M4 or the disk drive M5), completing tiered storage without software intervention.

[0050] This embodiment adopts a pure hardware modular architecture to realize the end-to-end hardware processing of "image acquisition-feature detection-synchronous buffer-hierarchical storage"; it relies on hardware logic to complete the hierarchical switching of feature-driven storage media without software intervention; the synchronous flow control and timing guarantee design has hardware-level real-time response capability and high operational stability, and is suitable for image data storage scenarios with high real-time performance and high reliability.

[0051] Example 3

[0052] Based on Embodiment 2, a specific implementation method for the brightness detection circuit, motion detection circuit, and edge detection circuit in the feature detection circuit is provided:

[0053] like Figure 4 As shown, the feature detection circuit includes a dual-channel first-in-first-out (FIFO) memory M3, a first operational amplifier C4, a brightness comparator C1, a motion detector C2, and an edge density detector C3. The dual-channel FIFO memory M3 uses an IDT7205 chip, the first operational amplifier C4 uses an LM324 chip, and both the brightness comparator C1 and the edge density detector C3 use LM339 chips. The motion detector C2 is composed of two LM339 chips.

[0054] Inside the dual-channel First-In-First-Out (FIFO) memory M3, the data output terminals (CH1_Q0~CH1_Q7) of its first channel are connected to the data input terminals (CH2_D0~CH2_D7) of its second channel, forming a cascaded structure. The digital video data output terminals (D0~D7) of the video processor U2 are connected to the data input terminals (CH1_D0~CH1_D7) of the first channel. By setting the depth of this cascaded structure to store the pixel data of one frame of image, the data output terminals (CH1_Q0~CH1_Q7) of the first channel output the pixel data of the current frame, while the data output terminals (CH2_Q0~CH2_Q7) of the second channel output the pixel data of the previous frame delayed by one frame.

[0055] In the motion detection circuit, the first channel data output terminal (CH1_Q0~CH1_Q7) of the dual-channel FIFO memory M3 is connected to the non-inverting input terminals of the four comparators of the first LM339 and the four comparators of the second LM339 in the motion detector C2; the second channel data output terminal (CH2_Q0~CH2_Q7) of the dual-channel FIFO memory M3 is connected to the inverting input terminals of the corresponding comparators of the two LM339s.

[0056] The outputs of these eight comparators are all connected to the input of an 8-input OR gate (e.g., a CD4078 chip). The output of this OR gate is connected to the non-inverting input of the first operational amplifier C4. The inverting input of the first operational amplifier C4 is directly connected to its output, and its output is used as the motion detection signal A.

[0057] In the brightness detection circuit and the edge detection circuit, the brightness signal output terminal of the video processor U2 is connected in two ways: the first way is connected to the non-inverting input terminal of the edge density detector C3 via the fifth resistor R5 and the first capacitor Cc1 connected in series; the second way is directly connected to the non-inverting input terminal of the brightness comparator C1.

[0058] The inverting input of edge density detector C3 is connected to a voltage divider node, consisting of a third resistor R3 and a fourth resistor R4 connected in series, between the power supply of the edge density detector and ground. The inverting input of brightness comparator C1 is connected to another voltage divider node, consisting of a first resistor R1 and a second resistor R2 connected in series, between the power supply of the brightness comparator and ground.

[0059] All comparator outputs using LM339 chips require a 10kΩ pull-up resistor to a 3.3V power supply to ensure the open-drain output structure generates a valid high-level logic signal. The output of edge density detector C3 generates an edge detection signal B, and the output of brightness comparator C1 generates a brightness detection signal C. Signals A, B, and C are connected to the three independent inputs of the decision module.

[0060] When the system is working, the digital video data output by the video processor U2 flows through the cascaded dual-channel first-in-first-out (FIFO) memory M3. For example... Figure 4 As shown, data is first written to the first FIFO channel; when the first channel is full of one frame, the data is sequentially transferred to the second FIFO channel through control logic. The storage depth of both channels is set to the capacity of a single frame's pixels, ensuring that the output provides corresponding pixel data that differs by one frame in time. These two frames of data are fed in parallel to the motion detector C2, where corresponding pixels are compared differentially in real time to detect inter-frame changes. If the difference between any pixel exceeds the comparator threshold, motion is detected, and the comparator outputs a high level (valid state). All comparator outputs are combined by an OR gate to form a high-level valid global motion flag, which is then buffered by the first operational amplifier C4, configured as a voltage follower, and outputs a high-level valid motion detection signal A.

[0061] Simultaneously, the luminance signal Y_OUT output by the video processor U2 is filtered by a high-pass filter circuit composed of the fifth resistor R5 and the first capacitor Cc1 to remove low-frequency background and extract high-frequency edge information. After processing, this signal is compared in two ways: one in the edge density detector C3 with a fixed threshold (approximately 1.2V) set by the third resistor R3 and the fourth resistor R4. When the threshold is exceeded, a high-level active edge detection signal B is output. The other is directly compared in the luminance comparator C1 with a luminance threshold (approximately 1.5V) set by the first resistor R1 and the second resistor R2. When the threshold is exceeded, a high-level active luminance detection signal C is output.

[0062] The three feature signals A, B, and C are sent to the feature encoder G1 in real time for subsequent decision-making modules to encode and make judgments.

[0063] The feature detection circuit shown in this embodiment abandons the approach of calculating features through algorithmic instructions, and instead maps features to physical quantities that can be directly distinguished by analog devices such as voltage comparators, resistor-capacitor networks, and basic digital logic. This shift in design paradigm frees the feature extraction process from the influence of variables such as processor load and cache hit rate, ensuring constant output latency and laying the foundation for the deterministic response of the entire system.

[0064] Example 4

[0065] Based on Example 3, a specific implementation method for the decision-making module is provided:

[0066] like Figure 5 As shown, the decision module includes a feature encoder G1 and a logic circuit, specifically an AND gate chip G2. The outputs of the first operational amplifier C4, the edge density detector C3, and the brightness comparator C1 are respectively connected to the three independent inputs of the feature encoder G1. Unused data inputs are connected to a high level (e.g., VCC) via pull-up resistors. The encoding output of the feature encoder G1 and the vertical synchronization signal output of the video processor U2 are connected to the same set of input ports of the AND gate chip G2. The output of the AND gate chip G2 is connected to the enable input of the address decoder A2. The AND gate chip G2 uses a 74LVC08 chip, connected to the system's 3.3V power supply, and its ground port is connected to the system's common ground.

[0067] The working process is as follows: The vertical synchronization signal VSYNC output by the video processor U2 identifies the start time of the image frame. The feature encoder G1 encodes the brightness, motion, and edge feature signals output by the feature detection circuit: when a frame contains any valid feature, G1 outputs a valid encoded signal. Only when the vertical synchronization signal VSYNC is valid (high-level pulse) and the feature encoded signal is valid simultaneously, the AND gate chip G2 outputs a high-level enable pulse; this pulse directly drives the enable input of the address decoder A2, instantaneously activating the address decoding operation, and then controlling the data gating switch K2 to direct the image data of this frame to the designated storage medium. This design strictly anchors the feature decision to the frame start edge defined by VSYNC through a single-stage AND gate G2, and uses the inherent timing of the video to achieve hardware-level gating: it not only eliminates false triggering at non-frame synchronization moments, but also eliminates the additional delay and uncertainty introduced by intermediate logic gates. This dual-condition hard-wired mechanism of "feature validity" and "frame synchronization" ensures the frame integrity, timing determinism, and path uniqueness of storage operations with the simplest circuitry. It is the core hardware logic of this invention to achieve "zero software intervention and deterministic off-line storage".

[0068] This decision module implements pure hardware feature frame synchronization decision-making through a combination of feature encoders and basic logic gates. It strictly binds the validity of image features to the timing of video frames, generating a storage enable signal only when valid features are present and the frame is at a synchronization point. This ensures the accuracy and integrity of data storage while meeting the system's core requirements for real-time performance and determinism, requiring absolutely no software intervention.

[0069] Example 5

[0070] Based on Embodiment 3, a specific implementation of a crystal oscillator circuit is provided:

[0071] like Figure 6As shown, the crystal oscillator circuit consists of a 12MHz passive crystal oscillator (HC-49S) and two 18pF surface-mount capacitors Cx and Cy. One end of the passive crystal oscillator and one end of the surface-mount capacitor Cx are connected to the clock input port of the video processor U2. The other end of the passive crystal oscillator and one end of the surface-mount capacitor Cy are connected to the clock output port of the video processor U2. The other ends of the surface-mount capacitors Cx and Cy are both connected to the system ground.

[0072] The clock input and output pins of the video processor U2 are dedicated to connecting to an external crystal oscillator circuit. Internally, it integrates an inverting amplifier and feedback resistor required to construct a Pierce oscillator. Upon power-up, the external crystal, capacitor, and internal circuitry of the video processor U2 together form a Pierce oscillator. The crystal operates at its series resonant frequency (12MHz), generating a stable oscillation signal. This signal, after being shaped by the internal circuitry of the video processor U2, serves as the system's master clock, providing a precise time reference for the video processor U2's digital processing, timing generation, and pixel clock output.

[0073] The crystal oscillator circuit provided in this embodiment has a simple structure. It provides a precise and highly stable clock source for the core video processor U2, ensuring the accuracy and synchronization of timing throughout the entire process of image data acquisition, processing, and transmission. This forms the foundation for the system to achieve highly reliable hardware processing.

[0074] Example 6

[0075] Based on Embodiment 2, an address mapping unit is added, and one implementation of the unit is provided, which is used to map the physical address generated by the address generator A1 to the logical address that controls the direction of data flow.

[0076] like Figure 7 As shown, the address mapping unit includes a programmable read-only memory M2, using the AT27C512R-70PU chip. Its address inputs (A0-A12) are directly connected to the lower 13 bits of the count output of the address generator A1 in the data buffer module to receive the physical address signal. Its data outputs are directly connected to the lower 3 bits of the address signal input of the address decoder A2.

[0077] The chip select pin of the programmable read-only memory (M2) is controlled by an enable logic circuit. This enable logic circuit is directly constructed from an inverter (which can be a single inverter unit from a 74HC04 chip). The address line A13 of the address generator A1 is directly connected to the input pin of the inverter G4. The output pin of the inverter G4 is directly connected to the chip select pin of the programmable read-only memory (M2), and the output enable pin of the programmable read-only memory (M2) is directly grounded, ensuring it is always in an output state.

[0078] In this embodiment, the enable logic circuit only detects the state of address line A13. Therefore, the effective working area of ​​the programmable read-only memory M2 (i.e., the physical address range involved in address mapping) is the address where address line A13 is equal to logic "1". The other high-order address lines (A14, A15) output by the address generator A1 do not participate in the enable judgment in this embodiment and can be left floating or connected according to other system requirements.

[0079] When the system is working, the lower 13 bits (A0-A12) of the 16-bit physical address signal output by address generator A1 serve as the address input for programmable read-only memory (M2); the 14th bit (A13), after being inverted by inverter G4, controls the chip select input of M2 (active low). When address line A13 of address generator A1 outputs "1", after being inverted by the inverter, the chip select input of programmable read-only memory M2 receives a valid low-level signal. Specifically: when address line A13 is high ("1"), the inverter outputs a low level, enabling programmable read-only memory M2 to work; when address line A13 is low ("0"), the inverter outputs a high level, disabling programmable read-only memory M2 to work.

[0080] When the programmable read-only memory M2 is enabled, it uses the lower 13 bits (A0-A12) of the address generator A1 as the lookup address to read the pre-programmed mapping table. The lower 3 bits (D0-D2) of its data output terminal are connected to the 3-bit address input terminal (A0 / A1 / A2) of the address decoder A2 as a logical address signal. The address decoder A2 then decodes according to this logical address signal, generates the corresponding control signal, drives the data selection switch K2 to operate, thereby guiding the current image data to the target memory channel specified by the logical address, completing the selection of the data flow direction.

[0081] In this embodiment, the address mapping unit implements the mapping from physical addresses to logical addresses through programmable read-only memory hardware and a single inverter enable logic circuit. This design, with its clear and simple hardware connections and preset mapping relationships, completely replaces the path of address forwarding by the memory controller, providing a definite address signal source for the address decoder. This enables the system to automatically control the splitting and storage of image data at the hardware level within a set limit, significantly reducing circuit complexity and enhancing reliability and economy while ensuring basic functionality.

[0082] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. An image data analysis storage system, characterized by, The application relates to a feature detection circuit and a feature detection method. The feature detection circuit comprises an image input interface U1, a feature extraction module, a decision module, a data buffer module and a storage control module. The feature extraction module comprises a video processor U2 and a feature detection circuit; an analog video input end of the video processor U2 is connected with an analog video output end of the image input interface U1; a digital video data output end of the video processor U2 is connected with a data input end of the data buffer module; an input end of the feature detection circuit is connected with an output end of the video processor U2; a feature signal output end of the feature detection circuit is connected with an input end of the decision module; an output end of the decision module is connected with an enable input end of the storage control module; and an output end of the data buffer module is connected with a data input end of the storage control module.

2. The image data analysis storage system of claim 1, wherein, The feature detection circuit comprises a brightness detection circuit, a motion detection circuit and an edge detection circuit; input ends of the brightness detection circuit and the edge detection circuit are connected with a brightness signal output end of the video processor U2; an input end of the motion detection circuit is connected with a digital video data output end of the video processor U2; and output ends of the brightness detection circuit, the motion detection circuit and the edge detection circuit are connected with input ends of the decision module.

3. An image data analysis storage system according to claim 2, wherein, The motion detection circuit comprises a double-channel first-in-first-out memory M3, a motion detector C2 and a first operational amplifier C4; an 8-bit digital video data output end of the video processor U2 is connected with a data input end of the double-channel first-in-first-out memory M3; a first-channel data output end of the double-channel first-in-first-out memory M3 is connected with non-inverted input ends of a plurality of comparators in the motion detector C2; a second-channel data output end of the double-channel first-in-first-out memory M3 is connected with inverted input ends of the plurality of comparators; output ends of the plurality of comparators are commonly connected with input ends of a multi-input OR gate; an output end of the OR gate is connected with a non-inverted input end of the first operational amplifier C4; and an inverted input end of the first operational amplifier C4 is connected with the output end of the first operational amplifier C4. The edge detection circuit comprises an edge density detector C3; a brightness signal output end of the video processor U2 is connected with a non-inverted input end of the edge density detector C3 via a fifth resistor R5 and a first capacitor Cc1 which are connected in series; an inverted input end of the edge density detector C3 is connected with a voltage division node composed of a third resistor R3 and a fourth resistor R4 which are connected in series; and the voltage division node is connected between a power supply and the ground. The brightness detection circuit comprises a brightness comparator C1; a brightness signal output end of the video processor U2 is connected with a non-inverted input end of the brightness comparator C1; and an inverted input end of the brightness comparator C1 is connected with a voltage division node composed of a first resistor R1 and a second resistor R2 which are connected in series; and the voltage division node is connected between the power supply and the ground. Output ends of the first operational amplifier C4, the edge density detector C3 and the brightness comparator C1 are respectively connected with three independent input ends of the decision module.

4. An image data analysis storage system according to claim 3, wherein, The storage control module comprises a storage controller K1, a first storage medium, a second storage medium, a data gating switch K2 and an address decoder A2; a data output end of the data buffer module is connected to a data input end of the storage controller K1, a null signal output end of the data buffer module is connected to a read enable input end of the storage controller K1, and a count output end of the data buffer module is connected to an address input end of the address decoder A2; a data output end of the storage controller K1 is connected to an input end of the data gating switch K2; an output end of the address decoder A2 is connected to a control end of the data gating switch K2; an output end of the decision module is connected to an enable input end of the address decoder A2; a first output end of the data gating switch K2 is connected to an input end of the first storage medium, and a second output end of the data gating switch K2 is connected to an input end of the second storage medium.

5. An image data analysis storage system according to claim 4, wherein, The decision module comprises a feature encoder G1 and a logic circuit; output ends of the first operational amplifier C4, the edge density detector C3 and the brightness comparator C1 are respectively connected to three independent input ends of the feature encoder G1, an output end of the feature encoder G1 and a vertical synchronization signal output end of the video processor U2 are respectively connected to two input ends of the logic circuit, and an output end of the logic circuit is connected to an enable input end of the address decoder A2.

6. An image data analysis storage system according to claim 5, wherein, The feature encoder G1 is a priority encoder, and the logic circuit is an AND gate chip G2; an encoding output end of the feature encoder G1 is connected to one input end of the AND gate chip G2, and a vertical synchronization signal output end of the video processor U2 is connected to the other input end of the AND gate chip G2; an output end of the AND gate chip G2 is connected to an enable input end of the address decoder A2.

7. The image data analysis storage system of claim 4, wherein, The data buffer module comprises a data buffer M1 and an address generator A1; a data input end of the data buffer M1 is connected to a digital video data output end of the video processor U2; a full signal output end of the data buffer M1 is connected to a data stream control end of the video processor U2, a null signal output end of the data buffer M1 is connected to a read enable input end of the storage controller K1, and a data output end of the data buffer M1 is connected to a parallel data input end of the storage controller K1; a clock input end of the address generator A1 is connected to a pixel clock output end of the video processor U2, and a count output end of the address generator A1 is connected to an address input end of the address decoder A2.

8. The image data analysis storage system of claim 4, wherein, An address mapping unit is further included; the address mapping unit comprises a programmable read-only memory M2, an address input end of the programmable read-only memory M2 is connected to a count output end of the data buffer module, and a data output end of the programmable read-only memory M2 is connected to an address input end of the address decoder A2.

9. The image data analysis storage system of claim 4, wherein, The storage controller K1 is a SATA bridge controller chip.

10. The image data analysis storage system of claim 4, wherein, The first storage medium is a solid state disk M4, and the second storage medium is a disk drive M5.

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