Self-timed circuit, shared self-timed circuit for SRAM read / write, and SRAM memory.

Abstract

This disclosure provides a self-timing circuit, a shared self-timing circuit for SRAM read / write operations, and an SRAM memory. The self-timing circuit includes: two frequency multiplier circuits, each including a connected PMOS transistor, a rising-edge D flip-flop, and an inverter; each frequency multiplier circuit also has a first output and a second output that are inverted; a delay chain connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits; a complementary XOR gate, comprising two XOR gates, the input of each XOR gate connected to the first output of one of the two frequency multiplier circuits and the second output of the other; and a NAND gate, its input connected to the outputs of the two XOR gates, and its output outputting a PULSE signal. The technical solution of this application embodiment can accurately simulate the delay process of the address decoder and the read / write operation delay process of the SRAM cell to generate corresponding control signals, reducing the power consumption of the SRAM and improving its operating efficiency.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit technology, and in particular relates to a self-timing circuit, a shared self-timing circuit for reading and writing SRAM, and an SRAM memory. Background Technology

[0002] Due to its fast access speed and refresh-free characteristics, Synchronous Static Random Access Memory (SRAM) is widely used in Very Large Scale Integration (VLSI) designs for storing and retrieving program data. Current technologies often employ self-timing modules to generate self-timing signals, accurately shutting down SRAM word lines and other modules after SRAM read / write operations, thus reducing SRAM power consumption and improving its efficiency. However, current self-timing modules cannot accurately simulate the actual SRAM cell write operation process, leading to additional power consumption and unnecessary time consumption. Therefore, accurately simulating the address decoder delay process and the SRAM cell read / write operation delay process to generate corresponding control signals, thereby reducing SRAM power consumption and improving its efficiency, has become an urgent technical problem to be solved. Summary of the Invention

[0003] The embodiments of this application provide a self-timing circuit, a shared self-timing circuit for SRAM read and write, and an SRAM memory, which can at least to a certain extent accurately simulate the delay process of the address decoder and the delay process of the SRAM cell read and write operation to generate corresponding control signals, reduce the power consumption of SRAM and improve its working efficiency.

[0004] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0005] According to one aspect of the embodiments of this application, a self-timing circuit is provided, comprising:

[0006] Two frequency multiplier circuits are provided, each of which includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series; each of the frequency multiplier circuits also has a first output terminal and a second output terminal, the output signals of the first output terminal and the second output terminal being inversely related to each other;

[0007] A delay chain, used to simulate the delay of the address decoder, is connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits;

[0008] A complementary XOR gate, comprising two XOR gates, wherein the input of each XOR gate is connected to a first output of one of the two frequency multiplier circuits and a second output of the other of the two frequency multiplier circuits;

[0009] The NAND gate has its input connected to the output of the two XOR gates, and the output of the NAND gate outputs the PULSE signal.

[0010] According to one aspect of the embodiments of this application, a shared self-timing circuit for SRAM read and write is provided, comprising:

[0011] Two frequency multiplier circuits are provided, each of which includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series; each of the frequency multiplier circuits also has a first output terminal and a second output terminal, the output signals of the first output terminal and the second output terminal being inversely related to each other;

[0012] The copy bit unit module has its write bit line input terminal and write bit line complement input terminal connected to the first output terminal and the second output terminal of one of the two frequency multiplier circuits, respectively. The read bit line output terminal of the copy bit unit module outputs a read enable signal REN.

[0013] A complementary XOR gate comprises two XOR gates. The input of one XOR gate is connected to the first output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line output of the copy bit unit module. The input of the other XOR gate is connected to the second output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line complement output of the copy bit unit module.

[0014] The NAND gate has its input connected to the output of the two XOR gates, and the NAND gate outputs a write enable signal WEN.

[0015] According to one aspect of the embodiments of this application, an SRAM memory is provided, including a read / write shared self-timing circuit as described in the above embodiments.

[0016] In some embodiments of this application, the self-timing circuit includes two frequency multiplier circuits, a complementary XOR gate, and a NAND gate. Each frequency multiplier circuit includes a connected PMOS transistor, a rising-edge D flip-flop, and an inverter. Each frequency multiplier circuit also has a first output terminal and a second output terminal, and the output signals of the first output terminal and the second output terminal are inverted. A delay chain is connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits. This delay chain is used to simulate the delay of the address decoder. The complementary XOR gate includes two XOR gates. The input terminal of each XOR gate is connected to the first output terminal of one of the two frequency multiplier circuits and the second output terminal of the other two frequency multiplier circuits. The output terminals of the two XOR gates are connected to the input terminal of the NAND gate. The output terminal of the NAND gate outputs a PULSE signal for control.

[0017] Therefore, by connecting the outputs of two XOR gates to a NAND gate to generate a PULSE signal, the inconsistent time T generated per cycle due to the unbalanced driving capability of the square wave signals output by the two frequency multiplier circuits can be avoided. This allows for accurate simulation of the delay process of the address decoder to generate the corresponding control signal.

[0018] In addition, in the read-write shared self-timing circuit, the method of reading and writing shared copy bit cells can accurately simulate the actual SRAM cell read-write operation delay process to generate corresponding control signals, reduce SRAM power consumption and improve its working efficiency.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0021] Figure 1 A schematic diagram of a self-timing circuit according to an embodiment of this application is shown;

[0022] Figure 2 It shows according to Figure 1 The circuit waveform diagram of the PULSE signal and the square wave signal generated by the two frequency multiplier circuits in the embodiment shown.

[0023] Figure 3 A schematic diagram of a shared self-timing circuit for reading and writing SRAM according to an embodiment of this application is shown.

[0024] Figure 4 It shows according to Figure 2The circuit waveform diagram of the REN and WEN signals with respect to the PULSE signal in the illustrated embodiment is shown. Detailed Implementation

[0025] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0026] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0028] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0029] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0030] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0032] It should be noted that the mainstream circuit architecture of existing SRAN includes SRAM memory cell array, SRAM address line decoder, column selector, SRAM latch-type sensitive amplifier module, input / output module, and SRAM timing control module.

[0033] The SRAM memory cell array typically consists of several 6T or 8T SRAM circuit structures. Each row of SRAM word lines (WL, Word Bitline) is connected, and an address decoder controls whether the word lines of that row are enabled. When enabled, all selected cells in that row can be read or written. Each column of SRAM bit lines (BL, Bitline) is connected. When the word lines are enabled, data is written into the SRAM or read from the bit lines and sent to the next level. The depth of the SRAM can be calculated using the following formula:

[0034] Depth = Number of rows in the SRAM array * (Number of columns in the SRAM array / SRAM data width)

[0035] An SRAM address line decoder typically consists of a two-stage decoder. The first-stage decoder breaks down a number of address signals into multiple 2-to-4, 3-to-8, or 4-to-16 decoders. The second-stage decoder uses AND-OR logic gates to perform a second decoding of the first-stage decoder's result, mapping it to a specific row word line in the SRAM. Generally, only one row word line is selected and enabled during each read / write operation; the data decoded by the decoder corresponds to this enabled row.

[0036] Column selectors and SRAM latch-type sense amplifiers (SAs) modules are used. Because each column in an SRAM cell array shares a read bitline (RBL), the parasitic capacitance on the bitline can be too large, affecting read speed. Using SAs to rapidly amplify the bitline data can significantly improve the overall read and write speed of the SRAM. When the SRAM depth is large but the data bit width is small, the SRAM array will be too thin and narrow, resulting in excessive parasitic capacitance on a single read bitline and limiting performance. In this case, by dividing the SRAM cell into several parts and then horizontally piecing them together, the SRAM array can be made into a rectangle with approximately equal length and width, and the order of magnitude of the parasitic capacitance in the horizontal and vertical directions is basically the same, achieving optimal performance. Column selectors are then used to select different columns, ensuring consistency in read and write operations. Generally, the number of column selectors N = the number of columns in the SRAM array / the SRAM data bit width.

[0037] Input / output modules typically consist of several latches or registers, used to temporarily store data to be written or data read from SRAM during each read / write cycle.

[0038] The SRAM timing control module simulates the delay time required for each step, generating corresponding timing control signals to ensure the correct timing of SRAM read and write operations. Generally, the SRAM write data timing is as follows: external clock edge arrives -> address decoder decodes -> write data is temporarily stored, waiting for the SRAM word line to turn on (i.e., waiting for the address decoder delay to end) -> the corresponding SRAM word line turns on, data is written -> word line turns off, waiting for the next operation instruction. The read data timing is as follows: external clock edge arrives -> address decoder decodes -> SRAM word line turns on -> SAs amplify the corresponding read bit line signal -> the read data is temporarily stored in the output register -> word line and SAs turn off, waiting for the next operation instruction.

[0039] When SAs amplify the read bit lines, an accurate enable signal (SAE) is required to enable them. If the enable signal is too early, a large voltage difference will not be formed on the read bit lines, leading to amplification failure; if the enable signal is too late, additional access time and power consumption will occur. A replica bitline structure is generally used to generate the SAE signal. The replica bitline belongs to the SRAM timing control module and is generally composed of several SRAM cells, but it does not handle access signals. This type of SRAM cell is divided into RC cells and DC (Dummy Cell) cells. The DC cell stores logic "0" signals by default. After the address decoder delay ends, it simultaneously turns on the word lines with the actual SRAM storage cells, and the word lines read out "0" data. The word lines of the RC cell are always off, responsible for simulating the parasitic capacitance on the read bit lines. The signal generated by the read bit lines of the replica bitline is the SAE signal provided to the SAs. The number of RC and DC cells should be designed to accurately simulate the actual read bit line delay time, so that the generated SAE signal meets the above requirements. However, under advanced process conditions, random variations in the device threshold voltage caused by process variations can lead to delay fluctuations in the copy bit cells and the actual SRAM read bit lines. These fluctuations exhibit a Gaussian distribution, which negatively impacts the reliability of the copy bit cells and SAs (Search Engines). To ensure that each SA can correctly amplify the data stored on the SRAM read bit lines, a large timing margin is typically provided for the SAE (Search Engine Emitting) signal generated by the copy bit cells to avoid the aforementioned effects.

[0040] Meanwhile, excessively long read / write operation times lead to additional power consumption. A common way to optimize this problem is to add a self-timing module to generate an accurate self-timing signal, which precisely shuts down the SRAM word lines and other modules after the SRAM completes the read / write operation, thereby reducing leakage current in these modules.

[0041] Some current solutions design a copy bit unit circuit for write operation detection, which realizes global control of write operations and simulates the time consumption of the write operation process through negative feedback, reducing unnecessary write operation time consumption. However, this technology does not combine the copy bit unit of the read operation with its designed copy bit unit circuit for the write operation, thus consuming more circuit area.

[0042] Another approach is to use a tunable pipeline structure to control the current of the RC cells in the copy bit cell, reducing the random variation in SA timing caused by random changes in the threshold voltage. Its main drawbacks are that the additional pipeline structure consumes more circuit area; and it only considers timing control under read operations, without addressing or optimizing for write operations.

[0043] Another approach involves designing separate read operation copy bit cells and write operation self-timing circuits, reducing write current by approximately 25%. By employing embedded built-in self-test (BIST) programmable timing control, it mitigates random delay variations caused by process variations and achieves compact timing control, thereby reducing power consumption. The main drawback of this approach is that the independent self-timing control circuits for read and write operations result in additional area consumption; the write operation self-timing circuit, generated by an inverter chain, cannot accurately simulate the timing of actual SRAM cell write operations under advanced process conditions, leading to additional power consumption and unnecessary time consumption.

[0044] Thus, embodiments of this application provide a self-timing circuit, a shared self-timing circuit for reading and writing SRAM, and an SRAM memory, thereby solving at least one of the above-mentioned problems.

[0045] Figure 1 A schematic diagram of a self-timing circuit according to an embodiment of this application is shown. Figure 1 As shown, the self-timing circuit includes two frequency multiplier circuits, a delay chain, a complementary XOR gate, and a NAND gate.

[0046] Specifically, each frequency multiplier circuit includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series. The PMOS transistor is used to reset either the first or second frequency multiplier circuit to zero after the SRAM global enable signal arrives. Furthermore, each frequency multiplier circuit has a first output terminal and a second output terminal, with the output signals of the first and second output terminals being inverted. In one example, an output can be drawn from the inverter of each frequency multiplier circuit, one before and one after, to serve as the first and second output terminals of that frequency multiplier circuit.

[0047] The delay chain is used to simulate the delay of the address decoder. It is connected between the rising edge D flip-flop and the inverter of one of the two frequency multiplier circuits. That is, one frequency multiplier circuit is connected to the delay chain, and the other frequency multiplier circuit is not connected to the delay chain.

[0048] The complementary XOR gate comprises two XOR gates. The input of each XOR gate is connected to the first output of one of two frequency multiplier circuits and the second output of the other frequency multiplier circuit to form a complementary signal. The outputs of the two XOR gates are connected to the input of a NAND gate, which outputs a corresponding PULSE signal for control purposes.

[0049] In practical use, the logic for generating the PULSE signal is as follows:

[0050] A frequency multiplier circuit without a delay chain generates a square wave signal with the opposite level to the previous cycle each cycle. Its duty cycle is equal to the duty cycle of the external clock signal CLK, and the period Q = 2 * per, where per is the clock period of the external clock signal CLK. If the arrival time of the rising edge of the external clock signal CLK is taken as time 0, then the arrival time T1 of the edge (rising or falling edge) of the square wave signal generated by this frequency multiplier circuit is T1 = Delay. D触发器 +Delay 反相器 .

[0051] For the frequency multiplier circuit connected with a delay chain, other characteristics are the same as the frequency multiplier circuit described above. The difference lies in the edge arrival time of its square wave signal:

[0052] T2 = Delay D触发器 +Delay 反相器 +Delay 延迟链

[0053] Therefore, when the two square wave signals from the two frequency multiplier circuits are used as inputs to an XOR gate, the XOR gate outputs Y = A'B + AB', where A is the square wave signal from the frequency multiplier circuit without a delay chain, and B is the square wave signal from the frequency multiplier circuit with a delay chain. According to the above output, Y is high if and only if A has reached its edge but B has not yet reached its edge; otherwise, Y is low.

[0054] Therefore, the high-level duration of the XOR gate output Y is: T = T2 - T1 = Delay 延迟链 The rising edge arrival time of the PULSE signal = T1 + Delay 异或门 +Delay 与非门 .

[0055] Therefore, by swapping the input ports of the two XOR gates and generating a PULSE signal by connecting the XOR gate output to a NAND gate, the inconsistency in time T per cycle caused by the imbalance in the driving capabilities of ports A and B can be offset. Figure 2 The diagram shows the circuit waveforms of the PULSE signal and the square wave signals generated by the two frequency multiplier circuits.

[0056] Figure 3 A schematic diagram of a shared self-timing circuit for reading and writing SRAM according to an embodiment of this application is shown.

[0057] like Figure 3 As shown, the read / write shared self-timing circuit includes two frequency multiplier circuits, a copy bit unit module, a complementary XOR gate, and a NAND gate.

[0058] Specifically, each frequency multiplier circuit includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series. The PMOS transistor is used to reset either the first or second frequency multiplier circuit to zero after the SRAM global enable signal arrives. Furthermore, each frequency multiplier circuit has a first output terminal and a second output terminal, with the output signals of the first and second output terminals being inverted. In one example, an output can be drawn from the inverter of each frequency multiplier circuit, one before and one after, to serve as the first and second output terminals of that frequency multiplier circuit.

[0059] The write bit line input (WBL in the diagram) and write bit line complement input (WBLB) of the copy bit unit module are connected to the first and second outputs of a frequency multiplier circuit, respectively. This allows WBL and WBLB to be at different levels, one low and the other high, respectively, and both inverted from the previous cycle. The read bit line of the copy bit unit module outputs the read enable signal REN.

[0060] The complementary XOR gate consists of two XOR gates. The input of one XOR gate is connected to the first output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line output of the copy bit unit module (i.e., WBL out in the figure). The input of the other XOR gate is connected to the second output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line complement output of the copy bit unit module (i.e., WBL out B in the figure).

[0061] The input of the NAND gate is connected to the output of two XOR gates, and the NAND gate outputs the corresponding write enable signal WEN.

[0062] It should be noted that the external clock signal used by the first and second frequency multiplier circuits can be the PULSE signal generated by the self-timing circuit in the aforementioned embodiment, whose port is connected to the input terminals of several parallel inverters to reset the drive capability. This signal is inverted from the PULSE signal, and its port is directly connected to the output terminal of the inverters. The frequency multiplier circuit uses the rising edge (i.e., the falling edge of the PULSE signal) for sampling. As mentioned earlier, the delay time of the address decoder in the SRAM architecture can be simulated by adjusting the delay chain. When the sampling time arrives, it indicates that the address decoding signal has reached the WL (Word Bitline) terminal of the SRAM memory cell array from the external port, starting to enable the SRAM memory cell.

[0063] In the read / write shared self-timing circuit of this application, the delay chain in the frequency multiplier circuit is replaced with a copy bit unit module. Since the frequency multiplier circuit can generate a pair of square wave signals that are out of phase with the previous cycle every cycle, it is very suitable for designing a write self-timing circuit with this architecture.

[0064] In one embodiment, the copy bit cell module includes several SRAM cells. Unlike a conventional 6T SRAM, this copy bit cell module uses a 7T SRAM constructed by introducing an additional NMOS transistor. Furthermore, its write bitline (WBL), write bitline bar (WBLB), and read bitline (RBL) are separated, thus allowing write enable and read enable signals to be generated simultaneously without interference.

[0065] In one embodiment, such as Figure 3 As shown, the SRAM cells are divided into two categories: DC and RC. The RC cells are always off, used to simulate the parasitic capacitance on the bit lines of a real SRAM cell array. The DC cells in this architecture are further divided into two types: RDC cells and WDC cells. The write operation terminal of the WDC cell is turned on when the PULSE signal is high. At this time, the complementary signals generated by the frequency multiplier circuit structure on WBL and WBLB can perform a write operation on the WDC cell, and the written data is always opposite to the signal currently stored in the WDC cell (because the signals input through WBL and WBLB in the previous cycle are always out of phase compared to the current cycle). Therefore, this architecture can completely simulate the write operation process of a real SRAM memory cell. It is worth noting that the overwrite operation requires changing the data state stored inside the SRAM, and its delay is greater than the delay of a non-overwrite operation; this delay is the maximum delay during the write operation process.

[0066] If we take the moment when the second frequency multiplier circuit receives the transition edge of the PULSE signal as time 0, after the write operation on the WDC cell is completed, the signal stored inside the WDC cell changes, and at this moment T2 = Delay D触发器 +Delay 反相器 +Delay 复制位单元写操作

[0067] Among them, Delay 复制位单元写操作 =Delay 实际SRAM存储阵列单元写操作

[0068] For the frequency multiplier circuit that is not connected to the replication bit unit module, the square wave transition time T1 = Delay D触发器 +Delay 反相器 .

[0069] Therefore, by connecting one end of the XOR gate to the node storing the signal internally in the WDC unit and the other end to the node of the frequency multiplier circuit that generates T1, the high-level duration of the XOR gate output Y is T = T2 - T1 = Delay. 复制位单元写操作 =Delay 实际SRAM存储阵列单元写操作 .

[0070] The high-level arrival time of Y = T1 = Delay D触发器 +Delay 反相器

[0071] The Y signal serves as the Write Enable (WEN) signal, enabling the actual SRAM memory array to be written. It is connected to the WL port of the SRAM memory array. The SRAM cell in that row is enabled only when the WL port of the corresponding row is high (i.e., the address decoder's decoding structure corresponds to that row) and the WEN signal is high. After the write enable signal returns to low, it indicates that the copy bit cell has completed the write operation. The duration of the high level of Y indicates that the actual SRAM memory cell has also completed the write operation. At this point, the SRAM is turned off, which does not affect the write operation result and eliminates the additional SRAM enable time, reducing unnecessary power consumption.

[0072] In the copy bit cell module, the RDC cell is used to generate the REN signal (i.e., read enable signal). The signal stored internally is connected to ground by an NMOS transistor and is always 0. When the PULSE signal is high, the RDC cell is turned on. At this time, the pre-charge of the read bit line RBL ends. Since the RDC cell always stores a 0 signal, the read bit line RBL will discharge to the RDC cell, and the read bit line RBL will go from high to low. Therefore, the read bit line RBL is low only when the RDC cell is turned on. Since it accurately simulates the read operation of the actual SRAM memory cell, REN = RBL, and the low level enables the read operation.

[0073] Next, the REN signal is connected to the sensitive amplifier module SAs as the enable port of SAs. When it is low, it means that the read bit line of the SRAM memory array has read a signal. At this time, SAs will amplify the signal and finally connect it to the input / output module for storage.

[0074] As mentioned earlier, the waveforms of the REN signal (active low) and the WEN signal (active high) relative to the PULSE signal... Figure 4 As shown.

[0075] Therefore, based on the self-timing circuit provided in this application embodiment, it generates a self-timing signal (i.e., PULSE signal) with analog address decoder delay through a frequency multiplier-XOR circuit, optimizing the instability problem of the self-timing signal at the extreme operating frequency of traditional self-timing circuits, and generating a pair of operation signals that are inverted with the previous cycle each cycle. Based on this frequency multiplier-XOR circuit, by designing a read-write shared self-timing circuit structure for SRAM, while generating the read bit line SAE signal (i.e., REN signal), it can also generate a write enable signal (i.e., WEN signal) to control whether the SRAM word line is turned on through the frequency multiplier-XOR circuit. Compared with the traditional copy bit cell, there is almost no additional area consumption, but by sharing the read and write operations, the power consumption under write operations is reduced. Compared with the write self-timing circuit composed of a traditional inverter chain, the delay uncertainty caused by random changes in the threshold voltage is reduced, and the low power consumption optimization effect of SRAM is achieved.

[0076] In some embodiments of this application, an SRAM memory is also provided, which includes a shared self-timing circuit for reading and writing SRAM as described in the foregoing embodiments.

[0077] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0079] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A self-timing circuit, characterized in that, include: Two frequency multiplier circuits are provided, each of which includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series; each of the frequency multiplier circuits also has a first output terminal and a second output terminal, the output signals of the first output terminal and the second output terminal being inversely related to each other; A delay chain, used to simulate the delay of the address decoder, is connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits; A complementary XOR gate, comprising two XOR gates, wherein the input of each XOR gate is connected to a first output of one of the two frequency multiplier circuits and a second output of the other of the two frequency multiplier circuits; The NAND gate has its input connected to the output of the two XOR gates, and the output of the NAND gate outputs the PULSE signal.

2. A shared self-timing circuit for SRAM read and write, characterized in that, include: Two frequency multiplier circuits are provided, each of which includes a PMOS transistor, a rising-edge D flip-flop, and an inverter connected in series; each of the frequency multiplier circuits also has a first output terminal and a second output terminal, the output signals of the first output terminal and the second output terminal being inversely related to each other; The copy bit unit module has its write bit line input terminal and write bit line complement input terminal connected to the first output terminal and the second output terminal of one of the two frequency multiplier circuits, respectively. The read bit line output terminal of the copy bit unit module outputs a read enable signal REN. A complementary XOR gate comprises two XOR gates. The input of one XOR gate is connected to the first output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line output of the copy bit unit module. The input of the other XOR gate is connected to the second output of the frequency multiplier circuit that is not connected to the copy bit unit module and the write bit line complement output of the copy bit unit module. The NAND gate has its input connected to the output of the two XOR gates, and the NAND gate outputs a write enable signal WEN.

3. The read / write shared self-timing circuit according to claim 2, characterized in that, The copy bit unit module includes several SRAM units, and the SRAM used is 7TSRAM. The write bit line, write bit line complement, and read bit line of the copy bit unit module are separated so that the write enable signal and the read enable signal can be generated at the same time.

4. The read / write shared self-timing circuit according to claim 3, characterized in that, The SRAM cell includes a DC cell and an RC cell. The RC cell is always off to simulate the parasitic capacitance on the bit lines of an actual SRAM cell array. The DC cell includes an RDC cell and a WDC cell. The RDC cell is used to generate a read enable signal, and the WDC cell is used to simulate the write operation process of an actual SRAM memory cell and generate a write enable signal.

5. The read / write shared self-timing circuit according to any one of claims 2-4, characterized in that, The inputs to the two frequency multiplier circuits are signals whose drive capability has been reset by an inverter after the PULSE signal is passed through it.

6. An SRAM memory, characterized in that, Includes a read / write shared self-timing circuit as described in any one of claims 2-5.

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