Channel binding method, device, equipment, medium and program product

Abstract

The present invention relates to the field of high-speed interface technology, and discloses a channel binding method, apparatus, device, medium, and program product. The method is applied to the receiving direction of an FPGA chip, and includes the following steps: obtaining a data transmission protocol and confirming the number of channels according to the data transmission protocol; confirming a primary channel and a secondary channel based on the number of channels; when the primary channel receives target data and confirms the target frame header of the target data, controlling the primary channel to send an alignment signal; and transmitting the alignment signal to the secondary channel via the entire Internet; when the secondary channel receives the alignment signal, adjusting the first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel; after the first-in-first-out queue read pointers corresponding to each secondary channel are adjusted, reading data from the first-in-first-out queue corresponding to the secondary channel and outputting it from the data port in the receiving direction of the physical coding sublayer. The method can adapt to the number of bound channels required by different protocols, greatly increasing the flexibility of channel binding.

Description

Technical Field

[0001] The present invention relates to the field of high-speed interface technology, and in particular to a channel binding method, device, equipment, medium and program product. Background Art

[0002] In the field of high-speed interfaces, different users have different channel bonding requirements. For example, when using the JESD204B protocol, users need to use 10-lane bonding at the PCS layer; when using the Ethernet protocol, users need to use 2-lane / 4-lane / 10-lane bonding at the PCS layer.

[0003] In traditional SoC (System on Chip) design, designers typically design a fixed number of lanes for bonding based on the protocol being used. For example, when designing an Ethernet protocol PCS that uses 4-lane bonding, designers typically only design 4-lane bonding logic. However, in FPGA design, users often require SerDes (Serializer / Deserializer) to be highly flexible, meaning they must support both different protocols and bonding capabilities for varying numbers of lanes.

[0004] Therefore, there is an urgent need for a channel bonding method that can support the channel bonding requirements of different protocols. Summary of the Invention

[0005] In view of this, the present application provides a channel binding method, apparatus, device, medium and program product that can support the channel binding requirements of different protocols. The technical solution is as follows.

[0006] In a first aspect, the present invention provides a channel bonding method, which is applied to the receiving direction of an FPGA chip, wherein the FPGA chip includes a fully interconnected network and a physical coding sublayer, wherein the physical coding sublayer is provided with a plurality of channels, wherein the plurality of channels are isolated by first-in-first-out queues, and the plurality of channels are interconnected through the fully interconnected network, and the method comprises:

[0007] Obtain a data transmission protocol and confirm the number of channels based on the data transmission protocol;

[0008] Based on the number of channels, determine the primary channel and secondary channel;

[0009] When the primary channel receives the target data and confirms the target frame header of the target data, the primary channel is controlled to send an alignment signal; and the alignment signal is transmitted to the secondary channel via the full Internet;

[0010] When the secondary channel receives the alignment signal, it adjusts the first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel;

[0011] When the read pointers of the FIFO queues corresponding to the sub-channels are adjusted, data is read from the FIFO queues corresponding to the sub-channels and output from the data port in the receiving direction of the physical coding sublayer.

[0012] In an optional embodiment, adjusting the read pointer of the first-in-first-out queue corresponding to the secondary channel includes: when the secondary channel receives the alignment signal, obtaining the data stored in the first-in-first-out queue corresponding to the secondary channel; based on the data stored in the first-in-first-out queue and the alignment signal, adjusting the read pointer of the first-in-first-out queue corresponding to the secondary channel.

[0013] In an optional embodiment, aligning the secondary channel with the primary channel includes: controlling a first-in-first-out queue read pointer corresponding to the secondary channel to point to a position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0014] In an optional embodiment, the confirming of the primary channel and the secondary channel includes: determining the primary channel from the channels and determining the remaining channels as secondary channels according to preset channel selection conditions; the preset channel selection conditions include channel number, performance or stability.

[0015] The channel binding method provided by the present invention has the following advantages.

[0016] The present invention discloses a channel binding method, which is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network and a physical coding sublayer. The physical coding sublayer is provided with a plurality of channels, which are isolated by first-in-first-out queues and interconnected by the fully interconnected network. The method first obtains a data transmission protocol and confirms the number of channels according to the protocol. Then, based on the channel number, performance, or stability, one channel is determined from the determined channels as the primary channel, and the remaining channels are secondary channels. The method operates independently on each channel in the receiving direction. When transmitted data is received, the frame header of the data is confirmed, and an alignment signal is sent through the primary channel. The alignment signal is then sent to each secondary channel through the fully interconnected network. When a secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted to align the secondary channel with the primary channel. Specifically, the first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel. After the read pointers of the FIFO queues corresponding to each sub-channel are adjusted, data is read from the FIFO queues corresponding to the sub-channels and output from the data port in the receive direction of the physical coding sublayer. The channel bonding method of the present invention can support the channel bonding requirements of different protocols and can adapt to the number of bonded channels required by different protocols, greatly increasing the flexibility of channel bonding.

[0017] In a second aspect, the present invention provides a channel bonding device, which is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network and a physical coding sublayer. The physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, and the plurality of channels are interconnected through the fully interconnected network. The device includes:

[0018] The protocol acquisition module is used to obtain the data transmission protocol and confirm the number of channels according to the data transmission protocol;

[0019] A primary channel confirmation module, configured to confirm the primary channel and the secondary channel based on the channel quantity;

[0020] An alignment signal sending module is configured to control the primary channel to send an alignment signal when the primary channel receives target data and confirms a target frame header of the target data; and transmit the alignment signal to the secondary channel via the entire Internet;

[0021] a channel alignment module, which adjusts a first-in-first-out queue read pointer corresponding to the secondary channel when the secondary channel receives the alignment signal, so that the secondary channel is aligned with the primary channel;

[0022] The output module is used to read data from the first-in-first-out queue corresponding to each sub-channel after the read pointers of the first-in-first-out queue corresponding to each sub-channel are adjusted, and output data from the data port of the receiving direction of the physical coding sublayer.

[0023] In an optional embodiment, the channel alignment module is specifically configured to:

[0024] When the secondary channel receives the alignment signal, the secondary channel obtains the data stored in the first-in-first-out queue corresponding to the secondary channel;

[0025] Based on the data stored in the FIFO queue and the alignment signal, a FIFO queue read pointer corresponding to the secondary channel is adjusted.

[0026] In an optional embodiment, the channel alignment module is further used to:

[0027] The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0028] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the channel binding method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0029] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the channel binding method of the first aspect or any corresponding embodiment thereof.

[0030] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the channel binding method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 FIG. 1 is a schematic diagram showing a traditional PCS 4-lane bonding solution according to an exemplary embodiment.

[0033] Figure 2The figure is a schematic diagram showing a design of a channel binding method according to an exemplary embodiment.

[0034] Figure 3 The figure is a flow chart of a channel binding method according to an exemplary embodiment.

[0035] Figure 4 The figure is a connection diagram of an 8-lane binding scenario in broadcast mode according to an exemplary embodiment.

[0036] Figure 5 The figure is a connection diagram of an 8-lane daisy chain binding scenario according to an exemplary embodiment.

[0037] Figure 6 is a schematic diagram showing an offset tolerance according to an exemplary embodiment.

[0038] Figure 7 FIG. 4 is a schematic diagram of multi-lane alignment according to an exemplary embodiment.

[0039] Figure 8 FIG. 1 is a schematic diagram of a single-SEQ channel bonding sequence according to an exemplary embodiment.

[0040] Figure 9 FIG. 1 is a schematic diagram of a double-SEQ channel bonding sequence according to an exemplary embodiment.

[0041] Figure 10 It is a structural diagram of a channel binding device provided in an embodiment of the present application.

[0042] Figure 11 It is a structural diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0044] It should be understood that the "indication" mentioned in the embodiments of this application can be a direct indication, an indirect indication, or an indication of an association. For example, "A indicates B" can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association between A and B.

[0045] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0046] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). This application does not limit its specific implementation method.

[0047] First, the terms involved in this application are introduced.

[0048] Channel Bonding: Channel bonding usually works in the Physical Coding Sublayer (PCS), but can also involve the Physical Medium Attachment (PMA) or other related layers.

[0049] 2lane, 10lane, and 16lane refer to the number of data transmission channels. A lane is the basic unit or channel for data transmission. Each lane represents an independent data transmission path, capable of sending and receiving data simultaneously, thereby increasing data throughput and network bandwidth.

[0050] FIFO (First In First Out) is a data structure used to store a series of elements that are removed in the order they were added to the queue. In electronic design, particularly in digital circuits and embedded systems, FIFOs are often implemented as hardware components for data buffering and temporary storage.

[0051] FIFO Read and Write Pointers: The FIFO's read and write pointers are core components of the FIFO. They track the read and write locations of data in the FIFO, respectively. The read pointer indicates the location of the data to be read from the FIFO. When data is read from the FIFO, the read pointer advances to point to the next data item to be read. The initial position of the read pointer is typically set to the FIFO's starting address (i.e., the location of the first data item).

[0052] Chbondo / Chbondi signals: Used to describe input / output (I / O) interfaces or signals related to channel bonding. In channel bonding scenarios, Chbondo / Chbondi signals allow the master transceiver to control clock correction and channel alignment of all bonded transceivers, ensuring that data is transmitted correctly and synchronously across multiple channels.

[0053] In the field of high-speed interfaces, different users have different channel bonding requirements. For example, when using the JESD204B protocol, users need 10-lane bonding at the PCS layer; when using the Ethernet protocol, users need 2-lane, 4-lane, or 10-lane bonding at the PCS layer. In traditional SoC (System on Chip) design, designers design bonding functions with a fixed number of channels based on the protocol in use. For example, when designing a PCS for an Ethernet protocol that uses 4-lane bonding, designers typically only design 4-lane bonding logic.

[0054] Taking 4-lane bonding as an example, the traditional PCS channel bonding design scheme Figure 1 shown.

[0055] In the TX direction (transmit direction), the transmit data will be broadcast to the 4 lanes of the PCS and then sent out separately by the PMA.

[0056] In the RX direction (receive direction), the data received by the PMA in each lane is misaligned. Data misalignment refers to the fact that data transmission on different lanes is not synchronized as expected. This may manifest as misaligned data beats, asynchronous clocks, inconsistent reset states, physical layer issues, or protocol layer issues. This misalignment can affect the correct reception and interpretation of data, leading to communication failures or system instability. Therefore, FIFO isolation is required. The FIFO read pointer is given by the read pointer of a specific lane. After alignment, the data of the four lanes is read from the FIFO, merged, and ultimately output from the PCS RX direction data port.

[0057] In FPGA design, users often require SerDes (Serializer / Deserializer) to be highly flexible, that is, it must be able to support different protocols and have the ability to support binding of different channel quantities.

[0058] Therefore, based on the flexible configuration characteristics of FPGA technology, an embodiment of the present invention provides a channel binding method that can support the channel binding requirements of different protocols. The method is applied to the receiving direction of the FPGA chip. The FPGA chip includes a fully interconnected network (PMA) and a physical coding sublayer (SWH). The physical coding sublayer is provided with a plurality of channels. The plurality of channels are isolated by a first-in-first-out queue. The plurality of channels are interconnected through the fully interconnected network. Still taking 4-lane binding as an example, the structural diagram of the channel binding method provided by this embodiment is as follows: Figure 2 As shown in the figure, compared with the traditional channel bonding strategy, the periphery of the FPGA design is equipped with a configurable fully interconnected network (SWH) to achieve arbitrary port interconnection under timing constraints.

[0059] The channel bonding method provided in this embodiment is no different from the traditional solution in the TX direction. TX data is broadcast to each lane in the PCS and is eventually sent out by the PMA.

[0060] In the RX direction, this solution will operate each lane independently, that is, add control logic outside each FIFO to enable it to independently output the chbondo signal to indicate that the channel bonding of the channel has been completed. The specific process is as follows Figure 3 As shown, the following steps are included.

[0061] S301: Obtain a data transmission protocol, and confirm the number of channels according to the data transmission protocol.

[0062] Specifically, different data transmission protocols have different channel binding requirements. Before performing channel binding, the number of channels that need to be channel bound needs to be extracted from the data transmission protocol.

[0063] S302: Based on the number of channels, confirm the primary channel and the secondary channel.

[0064] Optionally, based on the number, performance or stability of the channels, one channel may be determined as the primary channel from among the channels, and the remaining channels may be determined as secondary channels.

[0065] S303: When the primary channel receives the target data and confirms the target frame header of the target data, the primary channel is controlled to send an alignment signal; and the alignment signal is transmitted to the secondary channel through the entire Internet.

[0066] Specifically, after the main channel receives the data, it will send a chbondo signal, which is an alignment signal, and transmit the alignment signal to each secondary channel through broadcasting based on the entire Internet.

[0067] S304 : When the secondary channel receives the alignment signal, the read pointer of the FIFO queue corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the primary channel.

[0068] Specifically, each secondary channel receives the chbondo signal sent by the primary channel through the chbondi interface, and then aligns the secondary channel with the primary channel through the read pointer of the FIFO of each secondary channel.

[0069] S305: After the read pointers of the FIFO queues corresponding to the respective secondary channels are adjusted, data is read from the FIFO queues corresponding to the respective secondary channels and output from the data port in the receiving direction of the physical coding sublayer.

[0070] Specifically, when all secondary channels have completed alignment with the primary channel, that is, the entire channel bonding requirement is completed, data can be output from the data port in the receiving direction of the physical coding sublayer.

[0071] Optionally, in step S304, when the secondary channel receives the alignment signal, the data stored in the FIFO queue corresponding to the secondary channel is obtained; based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

[0072] In the above steps, the FIFO queue read pointer corresponding to the secondary channel can be controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0073] For example, Figure 4 A schematic diagram of an 8-lane binding network is given. Figure 4 Lane 0 of SerDes0 is the master lane. The master lane sends chbondo to notify other lanes that they need to be aligned with this lane. After other lanes receive the alignment information through chbondi, they adjust the FIFO read pointer to find the frame header of this lane and output RX data. This process can achieve the alignment of each lane.

[0074] Figure 4 In the fully interconnected network, the chbondo signal of any master lane can be connected to the chbondi signal of any lane. Therefore, if the external timing does not allow a lane to broadcast the chbondo signal, this embodiment also provides a daisy chain method to help any number of lanes complete the reception of the chbondo signal. Figure 5The diagram shows the connection diagram of an 8-lane daisy-chain bonding scenario. Specifically, lane 0 of SerDes0 is the first lane to send the chbondo signal, which is connected to the chbondi of lane 1 of SerDes0. Then, lane 1 of SerDes0 sends the chbondo signal to lane 2 of SerDes0, and so on. Finally, all eight lanes of the two SerDes can receive the channel bonding indication signal.

[0075] In addition, similar to the traditional design scheme, the channel bonding method provided in this embodiment needs to consider factors such as the data transmission rate in actual applications, the actual physical distance between channels, and the signal propagation delay when setting the maximum offset tolerance of the channel bonding sequence to ensure that there are no data errors or synchronization problems, such as Figure 6 As shown in Figure 1, if the actual channel skew exceeds the set maximum offset tolerance, it may cause data reception errors.

[0076] Taking 16-lane bonding as an example, the channel bonding method provided in this embodiment has a maximum skew tolerance of ±14 symbols (one symbol is 8 bits). Because each lane has inconsistent SERDES and PCS routing, the arrival time at the destination varies. The receiving end uses the FIFO to adjust the read pointer and receive data uniformly. The FIFO watermark is adjustable, thus offsetting jitter of ±14 symbols.

[0077] The multi-lane alignment diagram is as follows Figure 7 As shown, due to different protocols, the channel bonding sequence is different. In order to be compatible with the requirements of different protocols, the channel bonding method provided in this embodiment is designed to have a configurable channel bonding sequence. Figure 8 Shows a single SEQ channel bonding sequence, Figure 9 The dual-SEQ channel bonding sequence is shown, where SEQ0 to N, each SEQ is 8 bits, and the sequence in the 8 bits can be replaced with different sequences according to protocol requirements.

[0078] In summary, the channel bonding method provided by an embodiment of the present invention is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network and a physical coding sublayer. The physical coding sublayer is provided with a plurality of channels, which are isolated by first-in-first-out queues. The plurality of channels are interconnected through the fully interconnected network. The method first obtains a data transmission protocol and confirms the number of channels according to the protocol. Then, based on the channel number, performance or stability, one channel is determined from the determined channels as the main channel, and the remaining channels are secondary channels. The method operates independently on each channel in the receiving direction. When the transmitted data is received, the frame header of the data is confirmed, and an alignment signal is sent through the main channel. The alignment signal is then sent to each secondary channel through the full internet. After the secondary channel receives the alignment signal, the first-in-first-out queue read pointer corresponding to the secondary channel is adjusted so that the secondary channel is aligned with the main channel. Specifically, the first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header so that the output data of the secondary channel is aligned with the target data of the main channel. After the read pointers of the FIFO queues corresponding to each sub-channel are adjusted, data is read from the FIFO queues corresponding to the sub-channels and output from the data port in the receive direction of the physical coding sublayer. The channel bonding method of the present invention can support the channel bonding requirements of different protocols and can adapt to the number of bonded channels required by different protocols, greatly increasing the flexibility of channel bonding.

[0079] In the embodiments of the present application, a channel binding device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be repeated here. As used below, the term "module" can implement a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0080] The embodiment of the present application provides a channel binding device, Figure 10 This is a schematic diagram of the structure of a channel bonding device provided in an embodiment of the present application. The device is applied to the receiving direction of an FPGA chip. The FPGA chip includes a fully interconnected network and a physical coding sublayer. The physical coding sublayer is provided with a plurality of channels. The plurality of channels are isolated by a first-in-first-out queue. The plurality of channels are interconnected through the fully interconnected network. The device includes:

[0081] The protocol acquisition module 1001 is used to acquire a data transmission protocol and confirm the number of channels according to the data transmission protocol;

[0082] A primary channel confirmation module 1002 is configured to confirm a primary channel and a secondary channel based on the number of channels;

[0083] An alignment signal issuing module 1003 is configured to control the primary channel to issue an alignment signal when the primary channel receives the target data and confirms the target frame header of the target data; and transmit the alignment signal to the secondary channel via the entire Internet;

[0084] The channel alignment module 1004 adjusts the first-in-first-out queue read pointer corresponding to the secondary channel when the secondary channel receives the alignment signal, so that the secondary channel is aligned with the primary channel;

[0085] The output module 1005 is used to read data from the FIFO queue corresponding to each sub-channel after the read pointer of the FIFO queue corresponding to each sub-channel is adjusted, and output the data from the data port of the receiving direction of the physical coding sublayer.

[0086] In an optional embodiment, the channel alignment module 1004 is specifically configured to:

[0087] When the secondary channel receives the alignment signal, the secondary channel obtains the data stored in the first-in-first-out queue corresponding to the secondary channel;

[0088] Based on the data stored in the FIFO queue and the alignment signal, a FIFO queue read pointer corresponding to the secondary channel is adjusted.

[0089] In an optional embodiment, the channel alignment module 1004 is further configured to:

[0090] The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

[0091] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0092] The channel binding device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0093] The embodiment of the present invention also provides a computer device having the above Figure 10 Channel bonding device shown.

[0094] See also Figure 11 , Figure 11 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 11As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information in the graphical user interface on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 11 A processor 10 is taken as an example.

[0095] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0096] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0097] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0098] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0099] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 11 The bus connection is taken as an example.

[0100] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0101] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0102] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A channel binding method, characterized in that: The method is applied to a receiving direction of an FPGA chip, wherein the FPGA chip includes a fully interconnected network and a physical coding sublayer, wherein the physical coding sublayer is provided with a plurality of channels, wherein the plurality of channels are isolated by a first-in-first-out queue, and wherein the plurality of channels are interconnected through the fully interconnected network. The method includes: Obtaining a data transmission protocol, and confirming the number of channels according to the data transmission protocol; Based on the number of channels, determining a primary channel and a secondary channel; When the primary channel receives the target data and confirms the target frame header of the target data, controlling the primary channel to send an alignment signal; and transmitting the alignment signal to the secondary channel through the full Internet; When the secondary channel receives the alignment signal, the secondary channel adjusts the first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel; After the read pointers of the FIFO queues corresponding to the sub-channels are adjusted, data are read from the FIFO queues corresponding to the sub-channels and output from the data port in the receiving direction of the physical coding sublayer.

2. The method according to claim 1, characterized in that The adjusting the first-in-first-out queue read pointer corresponding to the secondary channel includes: When the secondary channel receives the alignment signal, the secondary channel obtains data stored in the first-in-first-out queue corresponding to the secondary channel; Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

3. The method according to claim 2, characterized in that The step of aligning the secondary channel with the primary channel comprises: The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

4. The method according to claim 3, characterized in that The confirmation of the primary channel and the secondary channel includes: According to preset channel selection conditions, a primary channel is determined from the channels, and the remaining channels are determined as secondary channels; the preset channel selection conditions include channel number, performance or stability.

5. A channel binding device, characterized in that: The device is applied to the receiving direction of an FPGA chip, the FPGA chip includes a fully interconnected network and a physical coding sublayer, the physical coding sublayer is provided with a plurality of channels, the plurality of channels are isolated by a first-in-first-out queue, and the plurality of channels are interconnected through the fully interconnected network, the device includes: A protocol acquisition module is used to acquire a data transmission protocol and confirm the number of channels according to the data transmission protocol; A primary channel confirmation module, configured to confirm a primary channel and a secondary channel based on the number of channels; An alignment signal issuing module is configured to control the primary channel to issue an alignment signal when the primary channel receives target data and confirms a target frame header of the target data; and transmit the alignment signal to the secondary channel via the full Internet; a channel alignment module, which adjusts a first-in-first-out queue read pointer corresponding to the secondary channel when the secondary channel receives the alignment signal, so that the secondary channel is aligned with the primary channel; The output module is used to read data from the first-in-first-out queue corresponding to each sub-channel after the read pointers of the first-in-first-out queue corresponding to each sub-channel are adjusted, and output the data from the data port of the receiving direction of the physical coding sublayer.

6. The device according to claim 5, characterized in that The channel alignment module is specifically used to: When the secondary channel receives the alignment signal, the secondary channel obtains data stored in the first-in-first-out queue corresponding to the secondary channel; Based on the data stored in the FIFO queue and the alignment signal, the FIFO queue read pointer corresponding to the secondary channel is adjusted.

7. The device according to claim 6, characterized in that The channel alignment module is further used to: The first-in-first-out queue read pointer corresponding to the secondary channel is controlled to point to the position corresponding to the target frame header, so that the output data of the secondary channel is aligned with the target data of the primary channel.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the channel binding method according to any one of claims 1 to 4 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the channel bonding method according to any one of claims 1 to 4.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the channel bonding method according to any one of claims 1 to 4.

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