High synchronization control device and method for IGBT series valve driving signal

Abstract

The invention belongs to the technical field of power electronics, and particularly relates to a high-synchronization control device and method for IGBT series valve driving signals, and the device comprises a main control case which is used for issuing an unlocking instruction and a modulation wave to a valve control main control board when all IGBT series valves are powered on; the valve control master control board is used for modulating the modulation wave to obtain a PWM signal and sending the PWM signal to the valve control slave control board; after a handshake signal responded by the valve control slave control board is received, an unlocking instruction is sent to the valve control slave control board; the valve control slave control board is used for responding a handshake signal to the valve control master control board when receiving the PWM signal; and after an unlocking instruction is received, the IGBT series valve is controlled to act through the control subunit controller according to the PWM signal. According to the technical scheme provided by the invention, the synchronism of PWM signal modulation is ensured, the high synchronism requirement of all IGBT devices is met, and the control precision of the IGBT series valve is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and particularly relates to a high-synchronization control device and method for IGBT series valve drive signals. Background Art

[0002] IGBT series technology is the most direct technical means to increase the capacity and voltage level of power electronic converters. It has simple and reliable control, and can greatly reduce the floor area and cost of converter valves, and is applicable to scenarios such as flexible DC transmission and high-voltage large-capacity STATCOM. Traditional converter valves use single-module IGBTs, and each IGBT device is equipped with a sub-unit controller. The superior of the sub-unit controller is the valve base controller. The valve base controller realizes the modulation function, packs the generated PWM signal group after modulation and sends it to each sub-unit controller through optical fiber. The sub-unit controller receives the data of the valve base controller, parses it and generates a PWM signal to trigger the corresponding IGBT.

[0003] This method is not applicable to IGBT series valves. The purpose of IGBT series valves is to meet the high-voltage level scenarios by series voltage division of multiple IGBT devices. In high-voltage level applications, it is necessary to have a good voltage sharing effect among the IGBT devices in the same string to avoid damage to a certain device due to high voltage. The drive signals of IGBT series valves require very high synchronization and very high control accuracy. However, the traditional sub-unit controller and valve base controller communicate through a serial protocol. Due to the crystal oscillator deviation between different sub-unit controllers, it is difficult to achieve precise control. Low control accuracy in the series valve will result in poor voltage sharing effect among the IGBTs in the same string, which will cause a certain device to be damaged due to high voltage. At the same time, the serial communication protocol has a low rate and a slow communication cycle, and the switching frequency of the device will also be limited. Summary of the Invention

[0004] To overcome the problems existing in the above related technologies, the present invention provides a high-synchronization control device and method for IGBT series valve drive signals.

[0005] According to the first aspect of the embodiment of the present invention, a high-synchronization control device for IGBT series valve drive signals is provided, including: a main control chassis, a main valve base control chassis, and a plurality of slave valve base control chassis; the main valve base control chassis includes: a valve control main control board; each slave valve base control chassis includes: a valve control slave control board;

[0006] The valve control main control board is respectively connected to the main control chassis and each valve control slave control board, and each valve control slave control board is connected to the IGBT series valve through a sub-unit controller;

[0007] The main control chassis is configured to issue an unlocking instruction and a modulation wave to the valve control main control board when all IGBT series valves are powered on;

[0008] The valve control main control board is used to modulate the modulation wave to obtain a PWM signal and send the PWM signal to the valve control slave control board; and after receiving the handshake signal replied by the valve control slave control board, send an unlocking instruction to the valve control slave control board.

[0009] The valve control slave control board is used to reply a handshake signal to the valve control main control board when receiving the PWM signal; and after receiving the unlocking instruction, control the IGBT series valve to act according to the PWM signal by controlling the sub-unit controller.

[0010] Preferably, the main valve base control chassis further includes: a first backplane, a first power supply board, and a plurality of first optical head interface boards;

[0011] The plurality of first optical head interface boards are arranged on the first backplane in a plug-in card manner, and the first power supply board is respectively connected to the valve control main control board and the first backplane;

[0012] The first backplane is used to provide communication between the plurality of first optical head interface boards and the valve control main control board, and supply power to the plurality of first optical head interface boards;

[0013] The plurality of first optical head interface boards are used for external communication of the valve control main control board;

[0014] The first power supply board is used to supply power to the valve control main control board and the first backplane.

[0015] Preferably, the slave valve base control chassis further includes: a second backplane, a second power supply board, and a plurality of second optical head interface boards;

[0016] The plurality of second optical head interface boards are arranged on the second backplane in a plug-in card manner, the plurality of second optical head interface boards are connected to the valve control slave control board, the second power supply board is respectively connected to the valve control slave control board and the second backplane, and the second optical head interface board is connected to the first optical head interface board;

[0017] The second backplane is used to provide communication between the plurality of second optical head interface boards and the valve control slave control board, and supply power to the plurality of second optical head interface boards;

[0018] The plurality of second optical head interface boards are used for external communication of the valve control slave control board;

[0019] The second power supply board is used to supply power to the valve control slave control board and the second backplane.

[0020] Preferably, the first optical head interface board is connected to the main control chassis and the second optical head interface board through optical fibers;

[0021] The valve control main control board is connected to all the valve control slave control boards through optical fibers, and the valve control slave control boards are connected to each other through optical fibers to form a fault blocking bus.

[0022] Preferably, the main control chassis is further configured to:

[0023] After the main control chassis, the valve control main control board and all the valve control slave control boards are powered on, send a reset command to the valve control main control board;

[0024] And after receiving the power-on status of all the IGBT series valves, if all the IGBT series valves are powered on, send an unlocking command and a modulation wave to the valve control main control board; if all the IGBT series valves are not powered on, then issue a fault alarm.

[0025] Preferably, the valve control main control board is further configured to send the reset command to all the valve control slave control boards; and feedback the power-on status of the IGBT series valves to the main control chassis;

[0026] The valve control slave control board is further configured to, after receiving the reset command, detect the power-on status of its corresponding IGBT series valve and feedback the power-on status of the IGBT series valve to the valve control main control board.

[0027] Preferably, the valve control main control board is specifically configured to:

[0028] Modulate the modulation wave with a pre-generated triangular carrier wave to obtain an initial signal;

[0029] Perform pulse width processing and dead zone processing on the initial signal to obtain the PWM signal.

[0030] Preferably, the valve control slave control board is specifically configured to:

[0031] Perform dead zone processing on the PWM signal to obtain a processed PWM signal;

[0032] Send the processed PWM signal to the sub-unit controller so that the sub-unit controller controls the action of the IGBT series valve according to the processed PWM signal.

[0033] Preferably, the slave valve control board is further configured to, after receiving the fault information of the IGBT series valve reported by the sub-unit controller, send the fault information to the master valve control board and other slave valve control boards respectively, so that all the slave valve control boards perform synchronous locking and tripping; and after performing synchronous locking and tripping, feedback the information indicating the completion of synchronous locking and tripping to the master valve control board.

[0034] The master valve control board is further configured to, when receiving the fault information and the information indicating the completion of synchronous locking and tripping, send the fault information and the information indicating the completion of synchronous locking and tripping to the main control chassis.

[0035] Preferably, both the master valve control board and the slave valve control boards adopt FPGA.

[0036] According to the second aspect of the embodiments of the present invention, a high-synchronization control method for IGBT series valve drive signals is provided, which is applied to the high-synchronization control device for IGBT series valve drive signals, and includes:

[0037] When all the IGBT series valves are powered on, the main control chassis is used to send an unlocking command and a modulation wave to the master valve control board.

[0038] The master valve control board modulates the modulation wave to obtain a PWM signal, and sends the PWM signal to the slave valve control boards.

[0039] When the slave valve control board receives the PWM signal, it responds to the master valve control board with a handshake signal.

[0040] After receiving the handshake signal responded by the slave valve control board, the master valve control board sends an unlocking command to the slave valve control board, so that after receiving the unlocking command, the slave valve control board controls the IGBT series valve to act according to the PWM signal by controlling the sub-unit controller.

[0041] Preferably, the method further includes:

[0042] When the main control chassis, the master valve control board and all the slave valve control boards are powered on, the main control chassis is used to send a reset command to the master valve control board, so that the master valve control board sends the reset command to all the slave valve control boards.

[0043] After receiving the reset command, the slave valve control board detects the power-on state of its corresponding IGBT series valve by using the slave valve control board, and feeds back the power-on state of the IGBT series valve to the master valve control board, so that the master valve control board feeds back the power-on state of the IGBT series valve to the main control chassis.

[0044] After the main control chassis receives the power-on states of all IGBT series valves, if all IGBT series valves are powered on, the main control chassis is used to send an unlocking instruction and a modulation wave to the valve control main control board; if not all IGBT series valves are powered on, the main control chassis is used to issue a fault warning.

[0045] Preferably, modulating the modulation wave by the valve control main control board to obtain a PWM signal includes:

[0046] Modulating the modulation wave by a pre-generated triangular carrier wave to obtain an initial signal;

[0047] Performing pulse width processing and dead zone processing on the initial signal to obtain the PWM signal.

[0048] Preferably, according to the PWM signal, controlling the IGBT series valve to act by controlling the sub-unit controller includes:

[0049] Performing dead zone processing on the PWM signal to obtain a processed PWM signal;

[0050] Sending the processed PWM signal to the sub-unit controller so that the sub-unit controller controls the IGBT series valve to act according to the processed PWM signal.

[0051] Preferably, the method further includes:

[0052] When the valve control slave control board receives the fault information of the IGBT series valve reported by the sub-unit controller, the valve control slave control board is used to send the fault information to the valve control main control board;

[0053] After the valve control main control board receives the fault information, the valve control main control board is used to send a synchronous locking instruction to all the valve control slave control boards;

[0054] When the valve control slave control board receives the synchronous locking instruction, the valve control slave control board is used to control the IGBT series valve to perform a locking trip by controlling the sub-unit controller.

[0055] According to the third aspect of the embodiments of the present invention, an electronic device is provided, including: at least one processor and a memory; the memory and the processor are connected by a bus;

[0056] The memory is used to store one or more programs;

[0057] When the one or more programs are executed by the at least one processor, the method described above is implemented.

[0058] According to a fourth aspect of an embodiment of the present invention, there is provided a readable storage medium having a program stored thereon, and when the program is executed, the method described above is implemented.

[0059] The technical solution provided by the present invention has the following beneficial effects:

[0060] The present invention provides a high-synchronization control device and method for IGBT series valve drive signals, including: a main control chassis, a main valve base control chassis, and a plurality of slave valve base control chassis; the main valve base control chassis includes: a valve control main control board; each slave valve base control chassis includes: a valve control slave control board; the valve control main control board is respectively connected to the main control chassis and each valve control slave control board, and each valve control slave control board is connected to the IGBT series valve through a sub-unit controller; the main control chassis is configured to, when all IGBT series valves are powered on, send an unlocking instruction and a modulation wave to the valve control main control board; the valve control main control board is configured to modulate the modulation wave to obtain a PWM signal and send the PWM signal to the valve control slave control board; and after receiving the handshake signal responded by the valve control slave control board, send an unlocking instruction to the valve control slave control board; the valve control slave control board is configured to, when receiving the PWM signal, respond with a handshake signal to the valve control main control board; and after receiving the unlocking instruction, control the IGBT series valve to act according to the PWM signal by controlling the sub-unit controller. The technical solution provided by the present invention adopts a master-slave chassis architecture and performs modulation within one chassis, which can ensure the synchronization of modulation; adopts the method of directly connecting optical ports to send PWM pulse communication to achieve multi-chassis expansion, which can not only meet the IGBT requirements of different quantities but also meet the high-synchronization requirements of all IGBT devices; adopts the slave valve base control chassis to distribute IGBT trigger signals, which can flexibly meet the IGBT series valve scenarios with different requirements and ensure the consistency of triggering of different IGBT devices; thereby improving the control accuracy of the IGBT series valve. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0062] Figure 1 is a structural block diagram of a high-synchronization control device for IGBT series valve drive signals provided by an embodiment of the present invention;

[0063] Figure 2 is a schematic diagram of the core board card interface configuration of the valve base control chassis provided by an embodiment of the present invention;

[0064] Figure 3It is a schematic diagram of the valve base control chassis expansion architecture provided by an embodiment of the present invention;

[0065] Figure 4 It is a topology diagram of a three-phase bridge circuit and a valve base control box provided by an embodiment of the present invention;

[0066] Figure 5 It is a processing flow chart of the valve base control chassis provided by an embodiment of the present invention;

[0067] Figure 6 It is a flow chart of a high synchronization control method for IGBT series valve drive signals provided by an embodiment of the present invention;

[0068] Figure 7 It is a structural block diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0069] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the following embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention fall within the scope of protection of the present invention.

[0070] Embodiment 1

[0071] The present invention provides a high synchronization control device for IGBT series valve drive signals. As Figure 1 shown, it includes: a main control chassis, a main valve base control chassis, and multiple slave valve base control chassis; the main valve base control chassis includes: a valve control main control board; each slave valve base control chassis includes: a valve control slave control board;

[0072] The valve control main control board is respectively connected to the main control chassis and each valve control slave control board, and each valve control slave control board is connected to the IGBT series valve through a sub-unit controller;

[0073] The main control chassis is used for, when all IGBT series valves are powered on, sending an unlocking instruction and a modulation wave to the valve control main control board;

[0074] The valve control main control board is used for modulating the modulation wave to obtain a PWM signal and sending the PWM signal to the valve control slave control board; and after receiving the handshake signal replied by the valve control slave control board, sending an unlocking instruction to the valve control slave control board;

[0075] The valve control slave control board is used for, when receiving the PWM signal, replying a handshake signal to the valve control main control board; and after receiving the unlocking instruction, controlling the IGBT series valve to act according to the PWM signal by controlling the sub-unit controller.

[0076] It can be understood that the main valve base control chassis of the present invention serves as the core processing unit for all modulation algorithms. The single-clock processing ensures the synchronization of PWM signals and simplifies the timing. As the PWM signal distribution and execution unit, the valve base control chassis can achieve the expansion of driving signals for large-scale IGBT series valves and can realize the real-time and rapid adjustment of the equalizing parameters of IGBTs in the same string.

[0077] Between the main control board and the slave control board of the valve control of the present invention, a pulse edge handshake method is adopted. The main control board of the valve control issues a PWM pulse waveform, and when the slave control board of the valve control receives the PWM pulse waveform and encounters an edge, it returns a handshake signal to ensure the reliability of communication between the master and the slave.

[0078] Based on the characteristics of IGBT series valves and the application scenarios of IGBT series valves, in order to meet the requirements of highly synchronous triggering of large-scale IGBTs, the present invention designs a master-slave chassis-type valve base control architecture. The valve base control chassis directly triggers in a pulse manner to achieve high synchronization of driving signals. The function boards of the master and slave valve base control chassis are configured identically, and the difference lies in the number of configured optical head interface boards. According to the number of IGBT devices required in the actual project, different numbers of slave valve base control chassis and the number of optical head interface boards of the main valve base controller are configured. Further, the main valve base control chassis further includes: a first backplane, a first power supply board, and a plurality of first optical head interface boards;

[0079] The plurality of first optical head interface boards are arranged on the first backplane in a plug-in card manner, and the first power supply board is respectively connected to the main control board of the valve control and the first backplane;

[0080] The first backplane is used to provide communication between the plurality of first optical head interface boards and the main control board of the valve control and to supply power to the plurality of first optical head interface boards;

[0081] The plurality of first optical head interface boards are used for external communication of the main control board of the valve control;

[0082] The first power supply board is used to supply power to the main control board of the valve control and the first backplane.

[0083] Further, the slave valve base control chassis further includes: a second backplane, a second power supply board, and a plurality of second optical head interface boards;

[0084] The plurality of second optical head interface boards are arranged on the second backplane in a plug-in card manner. The plurality of second optical head interface boards are connected to the slave control board of the valve control. The second power supply board is respectively connected to the slave control board of the valve control and the second backplane. The second optical head interface boards are connected to the first optical head interface boards;

[0085] The second backplane is used to provide communication between the plurality of second optical head interface boards and the slave control board of the valve control and to supply power to the plurality of second optical head interface boards;

[0086] Multiple second optical head interface boards for external communication of the valve-controlled slave control board;

[0087] The second power supply board for powering the valve-controlled slave control board and the second backplane.

[0088] It can be understood that the number of optical head interface boards can be designed according to project requirements and chassis size, and multiple channel configurations can be achieved through plug-in cards.

[0089] It should be noted that the optical head interface board is pluggable, inserted into the chassis backplane and connected to the main control board. The transceiver data is all electrical signals. The other end of the optical head interface board can be but is not limited to an ST optical port, communicating with external devices through optical fibers. The optical head interface board realizes optical-electrical conversion through hardware, and there is no control chip on the optical head interface board.

[0090] The present invention adopts the method of directly connecting the optical port to send PWM pulse communication to realize multi-chassis expansion. This architecture can not only meet the IGBT requirements of different quantities but also meet the high synchronization requirements of all IGBT devices.

[0091] Furthermore, the first optical head interface board is connected to the main control chassis and the second optical head interface board through optical fibers;

[0092] The valve-controlled main control board is connected to all valve-controlled slave control boards through optical fibers, and the valve-controlled slave control boards are connected to each other through optical fibers to form a fault blocking bus.

[0093] It should be noted that the valve base control chassis uses optical fiber communication to send the PWM signal to the sub-unit controller in a pulse direct-through manner, which can achieve long-distance signal transmission, reduce interference. The sub-unit controller then converts the optical signal into an electrical signal to trigger the IGBT. The valve base control chassis directly sending the PWM signal improves the control accuracy and the switching frequency. The fault blocking bus between valve base control chassis is realized in a series manner, saving channel numbers, sharing data through internal mapping, and ensuring fast response to fault blocking through optical fiber pulse mode to ensure the safety of the device.

[0094] Furthermore, the valve-controlled main control board and the valve-controlled slave control board can be but are not limited to using FPGA to realize the internal logic and timing of the valve base controller.

[0095] In some embodiments, such as Figure 2 shown, the external interface of the optical head interface board can be but is not limited to using an ST optical head for expanding the drive interface of the control board. The number of optical ports of one optical head interface board can be designed differently according to actual project requirements. The first optical head interface board receives the PMW signal from the control board through the backplane, converts it into an optical signal and sends it to the slave valve base control chassis or the IGBT drive board through the optical port respectively. The control board can also be but is not limited to using an ST optical head to connect to the optical head interface board and other control boards.

[0096] The present invention is mainly applied to the synchronous control of multiple valve base controllers of a large-scale press-fit type IGBT series valve. The series IGBT is more suitable for high voltage levels and large capacity scenarios by equalizing voltage through the series connection of multiple IGBT devices. Each IGBT device in the IGBT series valve is independently controlled by a valve base controller, and it can ensure the synchronous turn-on and turn-off of each IGBT. The present invention adopts a master-slave valve base control architecture design, uses the master valve base control chassis to complete modulation, and the slave valve base control chassis to realize the distribution of PWM signals to achieve the synchronous control of all IGBT devices, thereby realizing the drive interface configuration of different numbers of IGBT series valves.

[0097] Furthermore, the master control chassis is also used for:

[0098] After the master control chassis, the valve control main control board, and all valve control slave control boards are powered on, sending a reset instruction to the valve control main control board;

[0099] And after receiving the power-on status of all IGBT series valves, if all IGBT series valves are powered on, sending an unlock instruction and a modulation wave to the valve control main control board; if not all IGBT series valves are powered on, then issuing a fault alarm.

[0100] Furthermore, the valve control main control board is also used for sending the reset instruction to all valve control slave control boards; and feeding back the power-on status of the IGBT series valve to the master control chassis;

[0101] The valve control slave control board is also used for, after receiving the reset instruction, detecting the power-on status of its corresponding IGBT series valve and feeding back the power-on status of the IGBT series valve to the valve control main control board.

[0102] Furthermore, the valve control main control board is specifically used for:

[0103] Modulating the modulation wave with a pre-generated triangular carrier wave to obtain an initial signal;

[0104] Performing pulse width processing and dead zone processing on the initial signal to obtain a PWM signal.

[0105] In some embodiments, the valve control main control board receives the instruction and modulation wave sent by the master control chassis through one-way optical input. The valve control main control board sends the received master control instruction to all valve control slave control boards through the optical head interface board for optical head synchronous forwarding. The valve control main control board also receives the instruction status responses of all valve control slave control boards through the receiving optical head of the optical head interface board, and after summarizing and analyzing, reports back to the master through one-way optical output.

[0106] It should be noted that the method of "generating a triangular carrier wave" involved in the embodiments of the present invention is well-known to those skilled in the art. Therefore, its specific implementation method will not be described in detail. A triangular carrier wave is a periodic signal, and its amplitude changes linearly within one period. A counter is used to generate the triangular carrier wave. The counting clock and amplitude of the triangular carrier wave should be set according to the switching frequency of the IGBT series valve, and it increases (or decreases) in each clock cycle. When the counter reaches a set maximum or minimum amplitude, the counting direction is changed, and thus a triangular carrier wave signal can be obtained.

[0107] Further, the valve control slave control board is specifically used for:

[0108] Perform dead-time processing on the PWM signal to obtain the processed PWM signal;

[0109] Send the processed PWM signal to the sub-unit controller, so that the sub-unit controller controls the operation of the IGBT series valve according to the processed PWM signal.

[0110] In the present invention, the valve control master control board modulates the PWM signals of different phases or different three-phase bridges according to the actual topology. After the generated PWM signals are processed by pulse width, the PWM signals are synchronously sent to the valve control slave control board through the optical head interface board ST optical head. Using a single controller for modulation ensures the synchronization of modulation. The valve control slave control board does not perform modulation internally. After receiving the PWM signal from the valve control master control board, it performs pulse width and dead-time processing internally, and then distributes it to the IGBT series valves of the corresponding phases in a pulse manner to ensure the synchronous control of the IGBTs in the same string and meet the requirement of fast voltage equalization.

[0111] Further, the valve control slave control board is also used for, after receiving the fault information of the IGBT series valve reported by the sub-unit controller, sending the fault information to the valve control master control board and other valve control slave control boards respectively, so that all valve control slave control boards perform synchronous lockout tripping; and after performing synchronous lockout tripping, feeding back the information indicating the completion of synchronous lockout tripping to the valve control master control board;

[0112] The valve control master control board is also used for, when receiving the fault information and the information indicating the completion of synchronous lockout tripping, sending the fault information and the information indicating the completion of synchronous lockout tripping to the main control chassis.

[0113] It should be noted that the valve control slave control board can detect the status of all received optical fibers and packet faults. The valve control slave control board can analyze the fault information reported by the sub-unit controller. After all valve control slave control boards detect a fault, they can perform synchronous lockout tripping. All valve control slave control boards are connected in series through a pair of optical fibers to form a fault lockout bus, and the fault is quickly responded to in a pulse manner to ensure the synchronization of lockout at the fault moment and prevent the IGBT series valve from being damaged due to high voltage.

[0114] In the present invention, a PWM signal is generated by a valve base controller and directly sent to a lower-level subunit controller through an optical port, without adopting the traditional protocol mode. The use of direct PWM avoids communication jitter and ensures control accuracy. The use of optical fiber transmission also avoids the problem that long lines are easily interfered. The lower-level subunit controller is responsible for converting the received PWM optical signal into an electrical signal to directly trigger the IGBT. At the same time, the subunit controller can also detect IGBT module faults in real time and quickly report them to the valve base controller in a pulse manner to achieve fast locking and tripping of faults.

[0115] To further illustrate the above high-synchronization control device for IGBT series valve drive signals, the present invention provides a specific example, such as Figure 3 As shown, taking a three-phase bridge with 21 IGBT devices as a series valve as an example, each half-bridge of the three-phase bridge has a series of series valves, and there are a total of 6 series valves in the three-phase bridge, that is, 126 IGBT devices. Each IGBT requires 1 trigger signal. The valve base controller needs to synchronously control 126 IGBTs, and each valve base control chassis can control 42 IGBT devices. A total of 1 main control chassis, 1 main valve base control chassis, and 3 slave valve base control chassis need to be configured, which are respectively named the main control chassis, the main valve base control chassis, the A-phase slave valve base control chassis, the B-phase slave valve base control chassis, and the C-phase slave valve base control chassis. The main control chassis issues the modulation wave, the main valve base control chassis is responsible for modulation and data forwarding, and the slave valve base control chassis synchronously controls the IGBTs of the ABC three-phase bridge arms respectively.

[0116] The main valve base control chassis uses 4 pairs of optical fibers as data communication channels. Among them, 1 pair of optical fibers communicates with the main control chassis, the second pair of optical fibers communicates with the A-phase slave valve base control chassis for data, the third pair of optical fibers communicates with the B-phase slave valve base control chassis for data, and the fourth pair of optical fibers communicates with the C-phase slave valve base control chassis for data.

[0117] The main valve base control chassis uses 3 pairs of optical fibers as PWM issuing channels, which are respectively connected to 3 slave valve base control chassis. The PWM signal issues 3-phase PWM signals in a pulse manner, that is, the main valve base control chassis and the slave valve base control chassis achieve function expansion through a pulse manner. The slave valve base control chassis, as the receiving end, adopts an edge handshake mechanism to respond, and responds with a handshake pulse signal at the edge of each PWM signal pulse to ensure the reliability and real-time performance of the transmission.

[0118] Such as Figure 4As shown in the figure, the upper and lower bridge arms of phase A of the two IGBT series valves are controlled by the valve base control chassis for phase A. The upper and lower bridge arms of phase B of the two IGBT series valves are controlled by the valve base control chassis for phase B. The upper and lower bridge arms of phase C of the two IGBT series valves are controlled by the valve base control chassis for phase C. Among them, Q1 is the 21 IGBT series valves of the upper bridge arm of phase A, Q4 is the 21 IGBT series valves of the lower bridge arm of phase A, Q3 is the 21 IGBT series valves of the upper bridge arm of phase B, Q6 is the 21 IGBT series valves of the lower bridge arm of phase B, Q5 is the 21 IGBT series valves of the upper bridge arm of phase C, Q2 is the 21 IGBT series valves of the lower bridge arm of phase C, and C1 is the DC capacitor.

[0119] The fault channel bus is realized by the chassis series connection method. The main valve base control chassis is connected to the valve base control chassis for phase A through a pair of optical fibers. The valve base control chassis for phase A is connected to the valve base control chassis for phase B through a pair of optical fibers. The valve base control chassis for phase B is connected to the valve base control chassis for phase C through a pair of optical fibers, forming a series fault channel bus. The internal fault code is designed through the pulse protocol to realize the synchronous locking and tripping of all slave valve base control chassis.

[0120] In the example provided above, the control processing flow of the valve base control chassis is as Figure 5 shown, including the following steps:

[0121] Step 21: After all valve base control chassis and the main control chassis are powered on, the main control chassis issues a reset command to check whether all communication optical fibers are normal;

[0122] Step 22: The main valve base control chassis generates a triangular carrier wave and modulates it with the three-phase modulation wave issued by the main control chassis. The generated PWM signal is processed for pulse width to ensure that there is no narrow pulse width less than the dead time. The main valve base controller does not issue a PWM signal in the non-unlocked state;

[0123] Step 23: The slave valve base control chassis detects the power-on status of all series valves to ensure that all series valves are powered on normally and have the unlocking condition;

[0124] Step 24: Ensure that the device is fault-free and in the ready state, and issue an unlocking command through the main control chassis;

[0125] Step 25: After receiving the unlocking command from the main control chassis, the main valve base control chassis synchronously forwards the command to all slave valve base control chassis through the optical head interface board and starts to issue a PWM signal;

[0126] Step 26: After receiving the PWM signal, the slave valve base control chassis responds with a handshake signal to the main valve base control chassis. The slave valve base control chassis internally performs dead time processing on the received PWM signal and distributes the PWM signal to all output pins, and starts to issue a PWM signal after receiving the unlocking command;

[0127] Step 27: After unlocking, detect the fault information reported by the sub-unit controller of the valve base control chassis in real time. When fault information is received from any valve base control chassis, directly lock it and send the fault code to the fault bus channel;

[0128] Step 28: All valve base control chassis can receive the fault code and immediately respond to lock when the fault code is received;

[0129] Step 29: After locking, all valve base control chassis will no longer send PWM signals and wait for the fault to be eliminated before resetting and unlocking again.

[0130] A high-synchronization control device for IGBT series valve drive signals provided by the present invention, by adopting a master-slave chassis architecture, the modulation can ensure the synchronization of modulation within one chassis; by using the slave valve base control chassis to distribute IGBT trigger signals, it can flexibly meet the IGBT series valve scenarios with different requirements and ensure the consistency of triggering of different IGBT devices; through the fault channel bus method, all valve base controllers can be synchronously locked quickly to ensure the safety of the devices; by using the valve base control chassis pulse method to directly send PWM signals, it realizes the fast response of the devices and can also increase the switching frequency; the master valve base control chassis and the slave valve base control chassis adopt a pulse edge handshake mechanism to detect the channel state in real time to ensure the reliable transmission of PWM signals; the valve base control chassis of the present invention adopts a backplane communication method, which realizes the flexible configuration of the output port by the control board through the backplane and the plug-in card of the optical head interface board, and the shape of the valve base controller can be more standardized; the valve base control adopts a multi-chassis architecture to meet the synchronous control requirements of different topological structures. Through experiments, it is proved that the valve base control architecture of the present invention realizes that the on-off synchronization delay error of IGBT devices in the IGBT series valve is less than 1 us.

[0131] Embodiment 2

[0132] The present invention also provides a high-synchronization control method for IGBT series valve drive signals, which is applied to the high-synchronization control device of the IGBT series valve drive signals as Figure 6 shown, and includes the following steps:

[0133] Step 11: When all IGBT series valves are powered on, use the master control chassis to send an unlocking instruction and a modulation wave to the valve control main control board;

[0134] Step 12: Use the valve control main control board to modulate the modulation wave to obtain a PWM signal and send the PWM signal to the valve control slave control board;

[0135] Step 13: When the valve control slave control board receives the PWM signal, send a handshake signal to the valve control main control board;

[0136] Step 14: After receiving the handshake signal replied by the valve control slave control board, the valve control master control board sends an unlocking instruction to the valve control slave control board, so that after receiving the unlocking instruction, the valve control slave control board controls the IGBT series valve to act according to the PWM signal through the control sub-unit controller.

[0137] Further, the method further includes: Step 10:

[0138] After the main control chassis, the valve control master control board and all valve control slave control boards are powered on, the main control chassis is used to send a reset instruction to the valve control master control board, so that the valve control master control board issues the reset instruction to all valve control slave control boards;

[0139] After the valve control slave control board receives the reset instruction, the valve control slave control board is used to detect the power-on state of its corresponding IGBT series valve and feedback the power-on state of the IGBT series valve to the valve control master control board, so that the valve control master control board feeds back the power-on state of the IGBT series valve to the main control chassis;

[0140] After the main control chassis receives the power-on states of all IGBT series valves, if all IGBT series valves are powered on, the main control chassis is used to send an unlocking instruction and a modulation wave to the valve control master control board; if all IGBT series valves are not all powered on, the main control chassis issues a fault alarm.

[0141] Further, Step 12 includes:

[0142] Step 121: Modulate the modulation wave with a pre-generated triangular carrier wave to obtain an initial signal;

[0143] Step 122: Perform pulse width processing and dead zone processing on the initial signal to obtain a PWM signal.

[0144] Further, in Step 14, controlling the IGBT series valve to act according to the PWM signal includes:

[0145] Step 141: Perform dead zone processing on the PWM signal to obtain a processed PWM signal;

[0146] Step 142: Send the processed PWM signal to the sub-unit controller, so that the sub-unit controller controls the IGBT series valve to act according to the processed PWM signal.

[0147] Further, the method further includes: Step 15:

[0148] After the valve control slave control board receives the fault information of the IGBT series valve reported by the sub-unit controller, the valve control slave control board is used to send the fault information to the valve control master control board;

[0149] After the valve control main control board receives the fault information, it uses the valve control main control board to send a synchronization lockout command to all valve control slave control boards;

[0150] When the valve control slave control board receives the synchronization lockout command, it uses the valve control slave control board to control the IGBT series valve to perform a lockout trip through the control sub-unit controller.

[0151] It can be understood that the method embodiments provided above correspond to the device embodiments above, and the corresponding specific contents can be referred to each other, and will not be elaborated here.

[0152] It can be understood that the same or similar parts in the above embodiments can be referred to each other, and the content not described in detail in some embodiments can be referred to the same or similar content in other embodiments.

[0153] Embodiment III

[0154] As Figure 7 shown, the present invention also provides an electronic device, which may be a computer device, a single-chip microcomputer device, a smart mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, the processor, and the transceiver component are connected through a bus; the memory can be used to store an execution program, and an exemplary execution program may include instructions; the processor is used to execute the instructions stored in the memory. The memory can also be used to store data, and this data can be called and / or modified when the instructions are executed.

[0155] The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of a high synchronization control method for an IGBT series valve drive signal in the above embodiments.

[0156] Embodiment IV

[0157] Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device-readable storage medium (Memory). The electronic device-readable storage medium is a memory device in the electronic device, used to store programs and data. It can be understood that the storage medium here can include both the built-in storage medium in the electronic device and, of course, the extended storage medium supported by the electronic device. The storage medium provides a storage space, and this storage space stores the operating system of the terminal. Moreover, in this storage space, there is also stored one or more instructions suitable for being loaded and executed by the processor. These instructions can be one or more executable programs (including program codes). It should be noted that the storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. By the processor loading and executing one or more instructions stored in the storage medium, the steps of a high-synchronization control method for an IGBT series valve drive signal in the above embodiments can be implemented.

[0158] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0159] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0160] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device realizes the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1The functions specified in one or more boxes.

[0161] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in Figure 1 one process or more processes and / or boxes Figure 1 the functions specified in one box or more boxes.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A high-synchronous control device for an IGBT series valve drive signal, characterized in that: include: A master control chassis, a master valve base control chassis and a plurality of slave valve base control chassis; The main valve base control chassis includes: a valve-controlled main control board; each of the slave valve base control chassis includes: a valve-controlled slave control board; The valve-controlled main control board is connected to the main control chassis and each valve-controlled slave control board respectively, and each valve-controlled slave control board is connected to the IGBT series valve through a subunit controller; The main control chassis is used to send an unlocking instruction and a modulation wave to the valve control main control board when all IGBT series valves are powered on; The valve control master control board is used to modulate the modulation wave to obtain a PWM signal, and send the PWM signal to the valve control slave control board; and after receiving a handshake signal responded by the valve control slave control board, send an unlocking instruction to the valve control slave control board; The valve control slave control board is used to respond a handshake signal to the valve control master control board when receiving the PWM signal; and after receiving the unlocking instruction, control the action of the IGBT series valve by controlling the sub-unit controller according to the PWM signal.

2. The device according to claim 1, characterized in that The main valve base control chassis also includes: a first backplane, a first power supply board and a plurality of first optical head interface boards; The plurality of first optical head interface boards are arranged on the first backplane in a plug-in card manner, and the first power board is connected to the valve control main control board and the first backplane respectively; The first backplane is used to provide communication between the plurality of first optical head interface boards and the valve control main control board, and to supply power to the plurality of first optical head interface boards; The plurality of first optical head interface boards are used for external communication of the valve control main control board; The first power board is used to supply power to the valve-controlled main control board and the first backplane.

3. The device according to claim 2, characterized in that The slave valve base control chassis further includes: a second backplane, a second power supply board and a plurality of second optical head interface boards; The plurality of second optical head interface boards are arranged on the second backplane in a plug-in card type, the plurality of second optical head interface boards are connected to the valve-controlled slave control board, the second power board is respectively connected to the valve-controlled slave control board and the second backplane, and the second optical head interface board is connected to the first optical head interface board; The second backplane is used to provide communication between the plurality of second optical head interface boards and the valve control slave control board, and to supply power to the plurality of second optical head interface boards; The plurality of second optical head interface boards are used for external communication of the valve control slave control board; The second power supply board is used to supply power to the valve-controlled slave control board and the second backplane.

4. The device according to claim 3, characterized in that The first optical head interface board is connected to the main control box and the second optical head interface board through optical fibers; The valve-controlled main control board is connected to all the valve-controlled slave control boards through optical fibers, and the valve-controlled slave control boards are connected to each other through optical fibers to form a fault-locking bus.

5. The device according to claim 1, characterized in that The main control chassis is also used for: After the main control chassis, the valve control main control board and all the valve control slave control boards are powered on, a reset instruction is sent to the valve control main control board; And after receiving the power-on status of all IGBT series valves, if all the IGBT series valves are powered on, an unlocking instruction and a modulation wave are sent to the valve control main control board; if all the IGBT series valves are not powered on, a fault alarm is issued.

6. The device according to claim 5, characterized in that The valve control main control board is also used to send the reset instruction to all the valve control slave control boards; and to feed back the power-on status of the IGBT series valve to the main control chassis; The valve-controlled slave control board is also used to detect the power-on state of the corresponding IGBT series valve after receiving the reset instruction, and feed back the power-on state of the IGBT series valve to the valve-controlled master control board.

7. The device according to claim 1, characterized in that The valve control main control board is specifically used for: Modulating the modulated wave using a pre-generated triangular carrier wave to obtain an initial signal; The initial signal is subjected to pulse width processing and dead zone processing to obtain the PWM signal.

8. The device according to claim 1, characterized in that The valve control slave control panel is specifically used for: Performing dead zone processing on the PWM signal to obtain a processed PWM signal; The processed PWM signal is sent to the sub-unit controller, so that the sub-unit controller controls the action of the IGBT series valve according to the processed PWM signal.

9. The device according to claim 1, characterized in that The valve-controlled slave control board is also used to send the fault information of the IGBT series valve reported by the sub-unit controller to the valve-controlled master control board and other valve-controlled slave control boards respectively after receiving the fault information of the IGBT series valve reported by the sub-unit controller, so that all the valve-controlled slave control boards perform synchronous locking and tripping; and feeding back information on the completion of the synchronous locking tripping to the valve control main control board after executing the synchronous locking tripping; The valve control main control board is also used to send the fault information and the information of completing the synchronous locking and tripping to the main control chassis when receiving the fault information and the information of completing the synchronous locking and tripping.

10. The device according to claim 1, characterized in that The valve-controlled main control board and the valve-controlled slave control board both adopt FPGA.

11. A high-synchronous control method for an IGBT series valve drive signal, applied to the high-synchronous control device for an IGBT series valve drive signal according to any one of claims 1 to 10, characterized in that: include: When all IGBT series valves are powered on, the main control chassis sends unlocking instructions and modulation waves to the valve control main control board; The modulation wave is modulated by a valve-controlled main control board to obtain a PWM signal, and the PWM signal is sent to a valve-controlled slave control board; When the valve control slave control board receives the PWM signal, it responds with a handshake signal to the valve control main control board; After receiving the handshake signal from the valve-controlled slave control board, the valve-controlled main control board sends an unlocking instruction to the valve-controlled slave control board, so that after receiving the unlocking instruction, the valve-controlled slave control board controls the action of the IGBT series valve by controlling the sub-unit controller according to the PWM signal.

12. The method according to claim 11, characterized in that Also includes: When the main control chassis, the valve control main control board and all the valve control slave control boards are powered on, the main control chassis is used to send a reset instruction to the valve control main control board, so that the valve control main control board sends the reset instruction to all the valve control slave control boards; When the valve control slave control board receives the reset instruction, the valve control slave control board is used to detect the power-on state of the corresponding IGBT series valve, and the power-on state of the IGBT series valve is fed back to the valve control main control board, so that the valve control main control board feeds back the power-on state of the IGBT series valve to the main control chassis; After the main control chassis receives the power-on status of all IGBT series valves, if all the IGBT series valves are powered on, the main control chassis is used to send an unlocking instruction and a modulation wave to the valve control main control board; if all the IGBT series valves are not powered on, the main control chassis is used to issue a fault alarm.

13. The method according to claim 11, characterized in that The method of modulating the modulation wave by using the valve-controlled main control board to obtain a PWM signal includes: Modulating the modulated wave using a pre-generated triangular carrier wave to obtain an initial signal; The initial signal is subjected to pulse width processing and dead zone processing to obtain the PWM signal.

14. The method according to claim 11, characterized in that The controlling the action of the IGBT series valve by controlling the sub-unit controller according to the PWM signal comprises: Performing dead zone processing on the PWM signal to obtain a processed PWM signal; The processed PWM signal is sent to the sub-unit controller, so that the sub-unit controller controls the action of the IGBT series valve according to the processed PWM signal.

15. The method according to claim 11, characterized in that Also includes: When the valve control slave control board receives the fault information of the IGBT series valve reported by the sub-unit controller, the valve control slave control board is used to send the fault information to the valve control master control board; After the valve control main control board receives the fault information, the valve control main control board is used to send a synchronous locking instruction to all the valve control slave control boards; When the valve control slave control board receives a synchronous locking instruction, the valve control slave control board controls the sub-unit controller to control the IGBT series valve to lock and trip.

16. An electronic device, characterized in that: include: at least one processor and memory; The memory and the processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the high synchronization control method of the IGBT series valve driving signal according to any one of claims 11 to 15 is implemented.

17. A readable storage medium, characterized in that: An execution program is stored thereon, and when the execution program is executed, the high synchronization control method of the IGBT series valve driving signal according to any one of claims 11 to 15 is implemented.

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