Power optimization in electronic circuits based on root clock throttling

Abstract

Various example embodiments for supporting power optimization for electronic circuits are presented. Various example embodiments for supporting power optimization for electronic circuits may be configured to support power optimization for blocks of electronic circuits. Various example embodiments for supporting power optimization of a block of an electronic circuit may be configured to support power consumption reduction through a clock distribution tree of a block of an electronic circuit. Various example embodiments for supporting power consumption reduction through a clock distribution tree of a block of an electronic circuit may be configured to reduce power consumption through a clock distribution tree of a block of an electronic circuit by supporting root clock throttling for a block of an electronic circuit based on a workload on the block of an electronic circuit, to reduce power consumption of a clock distribution tree through a block of an electronic circuit.

Description

Technical Field

[0001] Various example embodiments generally relate to electronic circuits, and more specifically but not limited to supporting power optimization in electronic circuits. Background Art

[0002] An important design aspect for electronic circuits is power dissipation. In an application specific integrated circuit (ASIC), power is typically dissipated by block logic. Low-power ASIC designs are becoming increasingly common, especially for companies designing battery-operated devices such as laptop computers, smart phones, etc. Thus, there is a continuing need to support power optimization in ASICs and in electronic circuits generally. Summary of the Invention

[0003] In at least some example embodiments, a device includes: a block, wherein the block includes a clock distribution tree configured to distribute a clock signal within the block, and wherein the block is configured to control which clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block based on information indicating a workload on the block. In at least some example embodiments, a fraction of the clock pulses of the clock signal allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is controlled to remain within a range between a non-zero minimum value and a maximum value based on the clock signal of the block. In at least some example embodiments, when the information indicating the workload on the block indicates that activity is presented at an input interface to the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicating the workload on the block indicates that no activity is presented at an input interface to the block, clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicating the workload on the block indicates that activity is available at an output interface from the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicating the workload on the block indicates that no activity is available at an output interface from the block, clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicating the workload on the block indicates that a measurement of an internal state of the block indicates work presented to the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, the measurement of the internal state is based on at least one of the following: a measurement of the occupancy of a work queue of the block, or a measurement of the number of active threads of the block. In at least some example embodiments, the number of clock pulses of the clock signal of the block allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is based on a measurement of the internal state of the block. In at least some example embodiments, the number of clock pulses of the clock signal of the block allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses that will be allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, the clock pulses of the clock signal of the block allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block are synchronized with the clock signal of the block at a leaf level of the clock distribution tree of the block.In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree, and a clock modulator configured to control the passing of clock pulses of the block's clock signal from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree based on the clock control signal. In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree, and a clock modulator including: a clock input configured to receive the block's clock signal, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output clock pulses of the block's clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the block includes an interface configured to support communication between a first portion of the block's clock distribution tree and a second portion of the block's clock distribution tree. In at least some example embodiments, the interface includes a pseudo-synchronous first-in-first-out queue. In at least some example embodiments, the interface includes at least one of the following: a pulse crosser, or a pulse conversion pulse module. In at least some example embodiments, the block includes a processor and a memory. In at least some example embodiments, the device is a device including an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an integrated circuit, and the block is placed on the integrated circuit. In at least some example embodiments, the device is an application-specific integrated circuit, and the block is placed on the application-specific integrated circuit.

[0004] In at least some example embodiments, a non-transitory computer-readable medium stores computer program instructions that, when executed by a device, cause the device to at least: obtain information indicative of a workload on a block by a block including a clock distribution tree configured to distribute a clock signal within the block, and based on the information indicative of the workload on the block, control which clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block. In at least some example embodiments, a fraction of the clock pulses of the clock signal allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is controlled to remain within a range between a non-zero minimum value and a maximum value based on the clock signal of the block. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is presented at an input interface to the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is presented at an input interface to the block, clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is available at an output interface from the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is available at an output interface from the block, clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, when the information indicative of the workload on the block indicates that a measurement of an internal state of the block indicates that work is presented to the block, clock pulses of the clock signal of the block are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, the measurement of the internal state is based on at least one of the following: a measurement of the occupancy of a work queue of the block, or a measurement of the number of active threads of the block. In at least some example embodiments, the number of clock pulses of the clock signal of the block allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is based on a measurement of the internal state of the block. In at least some example embodiments, the number of clock pulses of the clock signal of the block allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses that will be allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block.In at least some example embodiments, clock pulses of a clock signal of a block that are allowed to be passed from a first portion of a clock distribution tree of the block to a second portion of the clock distribution tree of the block are synchronized with the clock signal of the block at a leaf level of the clock distribution tree of the block. In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of the clock signal are allowed to be passed from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block, and a clock modulator configured to control the passing of the clock pulses of the clock signal of the block from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block based on the clock control signal. In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of the clock signal are allowed to be passed from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block, and a clock modulator including: a clock input configured to receive the clock signal of the block, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output the clock pulses of the clock signal of the block that are allowed to be passed from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, the block includes an interface configured to support communication between the first portion of the clock distribution tree of the block and the second portion of the clock distribution tree of the block. In at least some example embodiments, the interface includes a pseudo-synchronous first-in first-out queue. In at least some example embodiments, the interface includes at least one of the following: a pulse crosser, or a pulse conversion pulse module. In at least some example embodiments, the block includes a processor and a memory. In at least some example embodiments, the device is a device including an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an integrated circuit, and the block is placed on the integrated circuit. In at least some example embodiments, the device is an application specific integrated circuit, and the block is placed on the application specific integrated circuit.

[0005] In at least some example embodiments, a method includes: obtaining, by a block including a clock distribution tree configured to distribute a clock signal within the block, information indicative of a workload on the block; and based on the information indicative of the workload on the block, controlling which clock pulses of the clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree. In at least some example embodiments, a fraction of the clock pulses of the clock signal allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is controlled to remain within a range between a non-zero minimum value and a maximum value based on the block's clock signal. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is presented at an input interface to the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is presented at an input interface to the block, clock pulses of the block's clock signal are blocked from passing from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is available at an output interface from the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is available at an output interface from the block, clock pulses of the block's clock signal are blocked from passing from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that a measurement of an internal state of the block indicates that work is presented to the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the measurement of the internal state is based on at least one of: a measurement of an occupancy rate of a work queue of the block, or a measurement of a number of active threads of the block. In at least some example embodiments, the number of clock pulses of the block's clock signal allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is based on a measurement of the internal state of the block. In at least some example embodiments, the number of clock pulses of the block's clock signal allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses that are to be allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the clock pulses of the block's clock signal allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree are synchronized with the block's clock signal at a leaf level of the block's clock distribution tree.In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are permitted to pass from a first portion of a clock distribution tree of the block to a second portion of the clock distribution tree of the block, and a clock modulator configured to control the passing of clock pulses of the clock signal of the block from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block based on the clock control signal. In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are permitted to pass from a first portion of a clock distribution tree of the block to a second portion of the clock distribution tree of the block, and a clock modulator including: a clock input configured to receive the clock signal of the block, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block. In at least some example embodiments, the block includes an interface configured to support communication between a first portion of a clock distribution tree of the block and a second portion of the clock distribution tree of the block. In at least some example embodiments, the interface includes a pseudo-synchronous first-in first-out queue. In at least some example embodiments, the interface includes at least one of the following: a pulse crosser, or a pulse conversion pulse module. In at least some example embodiments, the block includes a processor and a memory. In at least some example embodiments, the device is an apparatus including an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an integrated circuit, and the block is placed on the integrated circuit. In at least some example embodiments, the device is an application specific integrated circuit, and the block is placed on the application specific integrated circuit.

[0006] In at least some example embodiments, an apparatus includes components for: obtaining information indicative of a workload on a block from a block including a clock distribution tree, the clock distribution tree being configured to distribute a clock signal within the block, and based on the information indicative of the workload on the block, controlling which clock pulses of the clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree. In at least some example embodiments, a fraction of the clock pulses of the clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is controlled to remain within a range between a non-zero minimum value and a maximum value based on the block's clock signal. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is presented at an input interface to the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is presented at an input interface to the block, clock pulses of the block's clock signal are blocked from passing from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that activity is available at an output interface from the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that no activity is available at an output interface from the block, clock pulses of the block's clock signal are blocked from passing from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, when the information indicative of the workload on the block indicates that a measurement of the block's internal state indicates work presented to the block, clock pulses of the block's clock signal are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the measurement of the internal state is based on at least one of: a measurement of the occupancy of the block's work queue, or a measurement of the number of active threads of the block. In at least some example embodiments, the number of clock pulses of the block's clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is based on a measurement of the block's internal state. In at least some example embodiments, the number of clock pulses of the block's clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses that are to be allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the clock pulses of the block's clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree are synchronized with the block's clock signal at a leaf level of the block's clock distribution tree.In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree, and a clock modulator configured to control the passing of clock pulses of the block's clock signal from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree based on the clock control signal. In at least some example embodiments, the block includes: a controller configured to generate a clock control signal based on information indicative of a workload on the block, the clock control signal being configured to control which clock pulses of a clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree, and a clock modulator including: a clock input configured to receive the block's clock signal, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output clock pulses of the block's clock signal that are allowed to pass from the first portion of the block's clock distribution tree to the second portion of the block's clock distribution tree. In at least some example embodiments, the block includes an interface configured to support communication between a first portion of the block's clock distribution tree and a second portion of the block's clock distribution tree. In at least some example embodiments, the interface includes a pseudo-synchronous first-in-first-out queue. In at least some example embodiments, the interface includes at least one of the following: a pulse crosser, or a pulse conversion pulse module. In at least some example embodiments, the block includes a processor and a memory. In at least some example embodiments, the device is an apparatus including an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an electronic circuit, and the block is placed on the electronic circuit. In at least some example embodiments, the device is an integrated circuit, and the block is placed on the integrated circuit. In at least some example embodiments, the device is an application specific integrated circuit, and the block is placed on the application specific integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The teachings herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 Example embodiments of an application specific integrated circuit are depicted that include a block set including a block configured to support root clock throttling as a function of the workload of the block;

[0009] Figure 2 Example embodiments for root clock throttling of a block as a function of the workload of the block are depicted;

[0010] Figure 3 Example embodiments of a root clock throttling technique for forming a throttled clock in a manner that preserves the timing of the root clock in synchronization with the timing of the throttled clock by gating the root clock are depicted;

[0011] Figure 4 depicts an example embodiment of a root clock throttling technique for forming a throttled clock in a manner such that more useful work will be performed by blocks based on the throttled clock, based on a gated root clock;

[0012] Figure 5 depicts an example embodiment of a method for use by blocks of an application specific integrated circuit to support root clock throttling;

[0013] Figure 6 depicts an example embodiment of a method for use by a controller of a block of an electronic circuit to support root clock throttling; and

[0014] Figure 7 depicts an example embodiment of a computer suitable for performing the various functions presented herein.

[0015] For ease of understanding, the same reference numerals are used herein as much as possible to denote the same elements common to the various figures. Detailed Description

[0016] Various example embodiments for supporting power optimization for an electronic circuit are presented herein.

[0017] Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization for an electronic circuit based on support for power optimization of blocks of the electronic circuit. Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization of blocks of the electronic circuit by supporting reduction of power consumption of the clock distribution tree of the blocks of the electronic circuit. Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization of blocks of the electronic circuit by supporting root clock throttling of the blocks of the electronic circuit so as to reduce power consumption through the clock distribution tree of the blocks of the electronic circuit. Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization of blocks of the electronic circuit by supporting root clock throttling of the blocks of the electronic circuit so as to reduce power consumption through the clock distribution tree of the blocks of the electronic circuit while still supporting standard timing within the electronic circuit. Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization of blocks of the electronic circuit for various types of electronic circuits (e.g., integrated circuits (ICs), application specific integrated circuits (ASICs), etc.). It will be understood that these and various other example embodiments of root clock throttling of blocks of an electronic circuit can be further understood by further considering the use of such power optimization in an ASIC, as further discussed below.

[0018] Various example embodiments for supporting power optimization for an electronic circuit can be configured to support power optimization for an application specific integrated circuit (ASIC). Various example embodiments for supporting power optimization for an ASIC can be configured to support power optimization for a block of the ASIC. Various example embodiments for supporting power optimization for an ASIC can be configured to support power optimization for a block of the ASIC by supporting a reduction in power consumption in the clock distribution tree of the block of the ASIC. Various example embodiments for supporting power optimization for an ASIC can be configured to support power optimization for a block of the ASIC by supporting root clock throttling for the block of the ASIC in order to reduce the power consumption in the clock distribution tree of the block of the ASIC. Various example embodiments for supporting power optimization for an ASIC can be configured to support power optimization for a block of the ASIC by supporting root clock throttling for the block of the ASIC in order to reduce the power consumption through the clock distribution tree of the block of the ASIC while still supporting standard ASIC timing within the ASIC (e.g., such that standard ASIC flows can be employed to evaluate and verify timing). It will be understood that these and various other example embodiments for root clock throttling for a block of the ASIC can be further understood by first considering various more general aspects of power optimization in an ASIC, as further discussed below.

[0019] An ASIC is an integrated circuit chip that is custom-designed for a specific purpose. For example, an ASIC can be designed and used for various applications and devices, such as for smartphones, network devices (e.g., routers, satellite communication devices, etc.), digital watches, artificial intelligence (AI) programs, etc. In ASIC design, power is dissipated by block logic. There are typically four main components of this power: leakage, clock tree, flip-flop load, and random logic. The proportions of these power dissipation sources typically vary by technology and function. In the past, the fraction of power lost due to leakage was relatively high compared to other power components. However, the recent trend is that the fraction of power lost due to leakage has decreased, while the fraction of power consumed by the clock tree has increased and is expected to further increase in the future. For example, for certain technologies and functions, at 7 nanometers (nm), the clock tree can be more than 30% of the dynamic power, and as mentioned above, this percentage may be even higher in the future. Current clock gating techniques mainly focus on leaf clock gating (which is the clock loading for leaf flip-flops) or completely turning off the function by completely turning off the clock to the leaf flip-flops; however, in both cases, the clock tree is still running, so the clock tree still consumes power.

[0020] Low-power ASIC design, which is a set of techniques aimed at reducing the overall power consumption for ASICs, remains an important part of the ASIC design process. Companies designing ASICs for devices operating on battery power, such as smartphones, laptops, etc., have invested heavily in various aspects of low-power ASIC design as it affects the battery life of such devices, which in turn directly impacts customers and their purchasing decisions. Most of the work in such low-power ASIC design focuses on the ability to turn off modules or components when not in use, and having the hardware and other support to allow applications to be designed to take advantage of this ability to turn off modules or components when not in use. Sometimes there is the ability to completely turn off a module or component, while other times the clock is turned off at the module or component level to stop activity and save power. Then the module or component can be woken up or started periodically or when needed. While power savings can be achieved in this way, there are various applications that are not suitable for such an ability to turn off modules or components because there is always at least a certain amount of work to be done (e.g., a network is not suitable for turning off modules or components because there is usually at least some low-level background traffic, such as keep-alive messages, that need to be processed without excessive delay).

[0021] As described above, various example embodiments for supporting power optimization for ASICs can be configured to support power optimization for blocks of an ASIC based on throttling the root clock of the blocks for the ASIC. Throttling the root clock of a block for an ASIC can be performed by dynamically throttling the clock rate of the clocks within at least a portion of the clock distribution tree for the block of the ASIC, so as to reduce the power consumption through the clock distribution tree of the block of the ASIC (e.g., throttling of the root clock of the root clock can be applied to any appropriate layer level of the clock distribution tree that is above the leaf level of the clock distribution tree, which includes the clock receivers of the block of the ASIC). Throttling the root clock of a block for an ASIC can be performed by dynamically controlling the propagation of the root clock of the block within the clock distribution tree of the block of the ASIC (e.g., controlling which clock pulses of the root clock of the block are allowed to propagate within at least a portion of the clock distribution tree of the block, which can be applied to the various layers of the clock distribution tree of the block). Throttling the root clock of a block for an ASIC can be performed by dynamically controlling the entry of the root clock of the block into at least a portion of the clock distribution tree of the block of the ASIC (e.g., controlling which clock pulses of the root clock of the block are allowed to enter at least a portion of the clock distribution tree of the block, which can be applied to the various layers of the clock distribution tree of the block). It will be understood that these example embodiments as well as various other example embodiments will be further discussed below.

[0022] Various example embodiments can be configured to support root clock throttling for a root clock of an ASIC block by throttling the root clock of the block as a function of the workload on the block. Root clock throttling for a block of an ASIC can be performed by throttling the root clock of the block based on information indicating the workload on the block of the ASIC (e.g., one or more of information indicating the input activity of the block, information indicating the output activity of the block, information indicating the work to be processed within the block, etc., and various combinations thereof). Root clock throttling for a block of an ASIC can be performed by determining a measurement of the workload on the block (e.g., based on information indicating the workload on the block, such as one or more of information indicating the input activity of the block, information indicating the output activity of the block, information indicating the work to be processed within the block, etc.) and throttling the root clock of the block based on the measurement of the workload on the block (e.g., increasing the clock rate of the throttled clock based on a determination that the measurement of the workload increases or meets a threshold, decreasing the clock rate of the throttled clock based on a determination that the measurement of the workload decreases or meets a threshold, etc., and various combinations thereof). As a function of the workload on the block, root clock throttling for a root clock of an ASIC block can be performed in various ways, depending on the information indicating the workload on the block, the interpretation of the information indicating the workload on the block, etc., and various combinations thereof.

[0023] Various example embodiments can be configured to support root clock throttling for a root clock of an ASIC block by controlling the propagation of clock pulses of the root clock of the block between portions of the clock distribution tree of the block. Root clock throttling for a block of an ASIC can be performed by modulating the fraction of clock pulses from the root clock that are allowed to propagate between portions of the clock distribution tree of the block as a function of the workload on the block of the ASIC, such as by increasing the clock rate of the throttled clock as the workload on the block increases (e.g., allowing more root clock pulses to enter the clock distribution tree), and decreasing the clock rate of the throttled clock as the workload on the block decreases (e.g., allowing fewer root clock pulses to enter the clock distribution tree). Root clock throttling for a block of an ASIC can be performed by throttling the root clock to provide a throttled clock that operates between a non-zero minimum clock rate and an un-throttled maximum clock rate (which is equivalent to the root clock since the root clock is allowed to operate without throttling as a free-running root clock). Root clock throttling for a block of an ASIC can be performed by controlling the fraction of clock pulses from the root clock that are allowed to propagate as the throttled clock between portions of the clock distribution tree of the block (where the fraction can be any suitable fraction between (a) a non-zero minimum fraction and (b) a fraction equal to "1", where the root clock is allowed to propagate freely from a first portion of the clock distribution tree (where the clock distribution tree supports the propagation of the root clock) and a second portion of the clock distribution tree (where root clock throttling can be supported)).

[0024] Various example embodiments may be configured to support root clock throttling for a root clock of an ASIC block in a manner that ensures the clock always runs within the block of the ASIC and the block of the ASIC does not need to be powered down. Root clock throttling may be provided in a manner that achieves a significant power reduction for the ASIC block without powering down the ASIC block. Root clock throttling may be provided in a manner that enables a reduction in power consumption when the workload on the ASIC block is relatively low, while ensuring the clock always runs at least at some minimum level for the ASIC block (e.g., for handling background traffic in a network context). Root clock throttling may be provided while also supporting communication between ASIC blocks that are throttled at different clock rates. It should be noted that dynamically modulating the clock rate within an ASIC block based on the workload on the block has the effect of keeping the ASIC block pipeline fully loaded, so as to allow more useful work to be completed per clock cycle, while also keeping the timing of the root clock synchronized with the timing of the throttled clock (thus, avoiding introducing asynchronous timing domains and allowing the use of standard ASIC timing flows). Root clock throttling for a block of an ASIC may be performed in a manner that ensures full synchronization between the free-running root clock and the throttled clock within the block of the ASIC, thereby eliminating the need for asynchronous clock domains and allowing standard ASIC processes to be employed to evaluate and verify timing.

[0025] It will be understood that these example embodiments, as well as various other example embodiments, may be further understood by considering an ASIC that includes blocks configured to support root clock throttling based on workload, as shown with respect to Figure 1 shown.

[0026] Figure 1 An example embodiment of an application-specific integrated circuit is depicted that includes a set of blocks that includes blocks configured to support root clock throttling as a function of the workload of the block.

[0027] In Figure 1In [the figure], ASIC 100 includes two blocks 110-1–110-2 (collectively referred to as block 110), which are configured to operate based on a root clock 120 provided to each block 110. The root clock 120 of ASIC 100 provided to each block 110 is a free-running clock, which can be the system clock of ASIC 100 or any other suitable source clock for the blocks 110 of ASIC 100. The blocks 110 can be configured to support various logic functions. The blocks 110-1–110-2 accordingly include clock distribution trees 111-1–111-2 (collectively referred to as clock distribution tree 111). The clock distribution tree 111 is configured to distribute clock signals to the clock components of block 110, which are configured to support the various logic functions supported by block 110 (although only the leaf clock components of block 110 are shown for clarity). The entry of the root clock 120 of ASIC 100 into the blocks 110-1–110-2 generates root clocks 121-1–121-2 (collectively referred to as root clock 121) for the blocks 110-1–110-2, and these root clocks 121-1–121-2 are accordingly distributed to the clock components of the blocks 110-1–110-2 via the clock distribution trees 111-1–111-2 of the blocks 110-1–110-2, enabling the blocks 110-1–110-2 to operate based on the root clocks 121-1–121-2 accordingly. It will be understood that the root clock 121 of block 110 is equivalent to the root clock 120 of ASIC 100 and is therefore also a free-running clock.

[0028] In Figure 1 [the figure], block 110-1 is not configured to support root clock throttling, while block 110-2 is configured to support root clock throttling. For block 110-1 that does not support root clock throttling, power savings can only be achieved by leaf clock gating at the leaf components of the clock distribution tree 111-1 of block 110-1. For block 110-2 that supports root clock throttling, power savings can be achieved by applying root clock throttling to the root clock 112-2 of the clock distribution tree 111-2 of block 110-2 at various components at various levels of the clock distribution tree 111-2 of block 110-2.

[0029] In Figure 1In the above, as shown, block 110-2 is configured to support root clock throttling. Block 110-2 is configured to support root clock throttling of root clock 121-2 to form a throttled clock 122 for block 110-2. Block 110-2 is configured to support root clock throttling of root clock 121-2 based on workload indication information 123 indicating the workload on block 110-2 to form a throttled clock 122 for block 110-2. Block 110-2 is configured to support root clock throttling based on the clock throttling controller 125 of block 110-2 and based on the root clock modulator 127 of block 110-2. In block 110-2, the clock throttling controller 125 is configured to generate a clock control signal 126, which is provided to the root clock modulator 127 for the root clock modulator 127 to use to throttle the root clock 121-2 to form a throttled clock 122, and the throttled clock 122 is propagated by a part of the clock distribution tree 111-2 of block 110-2. As Figure 1 shown, throttling the root clock 121-2 of block 110-2 to form a throttled clock 122 for block 110-2 causes the root clock 121-2 of block 110-2 to propagate through a first part of the clock distribution tree 111-2 of block 110-2 (thus causing the free-running clock domain part of block 110-2, including components served by the free-running root clock 121-2), and also causes the throttled clock 122 to propagate through a second part of the clock distribution tree 111-2 of block 110-2 (thus causing the throttled clock domain part of block 110-2, including components served by the throttled clock 122).

[0030] The clock throttling controller 125 of block 110-2 can control the throttling of the root clock 121-2 of block 110-2 based on the workload of block 110-2 to form the throttled clock 122 of block 110-2. The clock throttling controller 125 of block 110-2 can control the throttling of the root clock 121-2 of block 110-2 by throttling the root clock 121-2 of block 110-2 to form the throttled clock 122 of block 110-2 as a function of the workload of block 110-2, thereby forming the throttled clock 122 of block 110-2. The clock throttling controller 125 of block 110-2 can control the throttling of the root clock 121-2 of block 110-2 to form the throttled clock 122 of block 110-2 as a function of the workload indication information 123 indicating the workload of block 110-2. As discussed further below, the workload indication information 123 indicating the workload of block 110-2 can include various types of information, which can be obtained from various information sources indicating the workload of block 110-2, and can be analyzed in various ways for controlling the throttling of the root clock 121-2 of block 110-2 to form the throttled clock 122 of block 110-2 as a function of the workload of block 110-2, etc., and various combinations thereof.

[0031] As described above, the clock throttling controller 125 can control the throttling of the root clock 121-2 of block 110-2 based on the workload indication information 123 indicating the workload of block 110-2 to form the throttled clock 122 for block 110-2. The workload indication information 123 indicating the workload of block 110-2 can be received from various sources of such information. As Figure 1As shown, the workload indication information 123 indicating the workload of the indication block 110-2 can be received from one or more elements located within and / or associated with the throttled clock domain, one or more elements located within and / or associated with the free-running clock domain, etc., and various combinations thereof. The workload indication information 123 indicating the workload of the indication block 110-2 can include various types of information that can indicate the workload on the block 110-2. For example, the workload indication information 123 can include information indicating input activity on the set of input interfaces of the block 110-2 (e.g., the queue occupancy of one or more queues of one or more input interfaces entering the block 110-2), information indicating the pending work on the core logic of the block 110-2 (e.g., the queue occupancy of one or more queues of the core logic of the block 110-2, an indication of the number of active threads for the core logic of the block 110-2, etc.), information indicating output activity on the set of output interfaces of the block 110-2 (e.g., the queue occupancy of one or more queues of one or more output interfaces outside the block 110-2), etc., and various combinations thereof. It should be understood that the clock throttling controller 125 can determine the workload of the block 110-2 in various other ways.

[0032] As described above, the clock throttling controller 125 can control the throttling of the root clock 121-2 of block 110-2 based on the workload indication information 123 indicating the workload of block 110-2 to form a throttled clock 122 for block 110-2. The clock throttling controller 125 can use the workload indication information 123 indicating the workload of block 110-2 in various ways for controlling the throttling of the root clock 121-2 of block 110-2 to form a throttled clock 122 for block 110-2. For example, the clock throttling controller 125 of block 110-2 can control the throttling of the root clock 121-2 of block 110-2 by receiving the workload indication information 123 indicating the workload of block 110-2 and generating a clock control signal 126 based on the workload indication information 123 indicating the workload of block 110-2. For example, the clock throttling controller 125 of block 110-2 can control the throttling of the root clock 121-2 of block 110-2 by receiving the workload indication information 123 indicating the workload on block 110-2, calculating a measurement of the workload on block 110-2 based on the workload indication information 123 indicating the workload of block 110-2, and generating a clock control signal 126 based on the measurement of the workload of block 110-2. In other words, the workload indication information 123 indicating the workload of block 110-2 can be used directly or indirectly (e.g., based on information that can be derived from processing and / or analyzing the workload indication information 123 indicating the workload of 110-2) as a basis for generating a clock control signal 126 that is used to control the throttling of the root clock 121-2 of block 110-2 to form a throttled clock 122 for block 110-2.

[0033] As described above, the clock throttling controller 125 can control the throttling of the root clock 121-2 of block 110-2 based on the workload indication information 123 indicating the workload of block 110-2 to form a throttled clock 122 for block 110-2. It should be noted that the various aspects of controlling the throttling of the root clock 121-2 of block 110-2 to form the throttled clock 122 for block 10-2 (e.g., the ability to determine the clock rate of the throttled clock 122, the clock rate granularity supported for the throttled clock 122, etc., and their various combinations) can depend on the various aspects of the workload indication information 123 indicating the workload of block 110-2 (e.g., the type of information included in the workload indication information, the level of detail of the information included in the workload indication information, etc., and their various combinations). For example, in the case where the workload indication information 123 only includes an indication of whether the queue fill level meets a threshold, one or more heuristics can be applied to determine an appropriate throttled clock rate for the throttled clock 122. For example, in the case where the workload indication information 123 includes a queue fill level value identifying a specific fill level of the queue, one or more mapping algorithms can be applied to map the specific fill level of the queue to a specific throttled clock rate for the throttled clock 122. It will be understood that various other capabilities can be applied to the workload indication information 123 and / or the information derived from the workload indication information 123 to control the throttling of the root clock 121-2 of block 110-2 to form the throttled clock 122 for block 110-2 (e.g., at various granularity levels of the throttled clock rate for the throttled clock 122, based on the support for various throttled clock rate levels and / or transitions for the throttled clock 122, etc., and their various combinations).

[0034] The clock throttling controller 125 of block 110-2 can be configured to control the generation of the throttled clock 122 from the root clock 121-2 by controlling the transfer of clock pulses of the root clock 121-2 of block 110-2 to at least a portion of the clock distribution tree 111-2 of block 110-2. For example, in a case where the throttled clock for block 110-2 is configured to support four rates (e.g., a fully unthrottled clock rate, a 1 / 2 clock rate, a 1 / 4 clock rate, and a 1 / 8 clock rate), throttling the root clock 121-2 to provide the throttled clock 122 for block 110-2 can include: when the fully unthrottled clock rate is used, allowing all pulses of the root clock 121-2 to be clock pulses of the throttled clock 122 for the clock distribution tree 111-2; when the 1 / 2 clock rate is supported, allowing every other pulse of the root clock 121-2 to be a clock pulse of the throttled clock 122 for the clock distribution tree 111-2; when the 1 / 4 clock rate is supported, allowing every fourth pulse of the root clock 121-2 to be a clock pulse of the throttled clock 122 for the clock distribution tree 111-2; and when the 1 / 8 clock rate is supported, allowing every eighth pulse of the root clock 121-2 to enter the clock distribution tree 111-2. The transfer of clock pulses of the root clock 121-2 of block 110-2 to at least a portion of the clock distribution tree 111-2 of block 110-2 can be controlled based on gating or using other suitable clock pulse control techniques. It will be understood that the throttled clock for block 110-2 can be generated from the root clock 121-2 of block 110-2 in various other ways (e.g., using various other throttled clock rate fraction levels based on the fraction of clock pulses of the root clock 121-1 of block 110-2 that are allowed to be clock pulses of the throttled clock 122 for block 110-2, using various other clock pulse control techniques for controlling which clock pulses of the root clock 121-1 of block 110-2 become clock pulses of the throttled clock 122 for block 110-2, etc., and various combinations thereof).

[0035] The clock throttling controller 125 of block 110-2 can be configured to support a throttled clock 122 having a throttled clock range. The clock throttling controller 125 of block 110-2 can throttle the root clock 121-2 of block 110-2 by modulating the root clock 121-2 of block 110-2 within the throttled clock range, thereby providing the throttled clock 122 for block 110-2. The throttled clock range of the throttled clock 122 of block 110-2 can be defined based on the clock rate of the root clock 121-2 of block 110-2. The throttled clock range of the throttled clock 122 of block 110-2 can be defined between a non-zero minimum clock rate (which is a fraction of the clock rate of the root clock 121-2 of block 110-2) and a maximum clock rate (which is equal to the clock rate of the root clock 121-2 of block 110-2). The non-zero minimum clock rate ensures that the clock of block 110-2 always runs at least at a certain minimum rate (e.g., for handling background traffic in a network context or other types of work in other contexts). The maximum clock rate is equal to the clock rate of the root clock 121-2 of block 110-2 without throttling, so that the clock of block 110-2 can run unthrottled at the root clock rate of the root clock 121-2 of block 110-2 when needed (i.e., the root clock 121-2 of block 110-2 runs freely at the same clock rate as the free-running root clock 120).

[0036] The clock throttling controller 125 of block 110-2 can be configured to support a throttled clock 122 having a specific number of clock rate levels, specific clock rates for the clock rate levels, a specific clock rate transition between adjacent clock rate levels, etc. For example, the throttled clock 122 for block 110-2 can support five clock rate levels, which are defined by halving / doubling the clock rate between adjacent clock rate levels (e.g., the fully unthrottled clock rate, 1 / 2 clock rate, 1 / 4 clock rate, 1 / 8 clock rate, and 1 / 16 clock rate as the minimum throttled clock rate). For example, the throttled clock 122 for block 110-2 can support four clock rate levels, which are defined by quartering / quadrupling the clock rate between adjacent clock rate levels (e.g., the fully unthrottled clock rate, 1 / 4 clock rate, 1 / 16 clock rate, and 1 / 64 clock rate as the minimum throttled clock rate).

[0037] The clock throttling controller 125 of block 110 may be configured to control transitions between clock rate levels of the throttled clock 122 based on a set of transition thresholds. For example, in a case where the throttled clock 122 for block 110-2 is configured to support four rates (e.g., fully unthrottled clock rate, 1 / 2 clock rate, 1 / 4 clock rate, 1 / 8 clock rate), throttling of the root clock 121-2 may be controlled based on three transition thresholds associated with the workload on block 110-2 to provide the throttled clock 122 for block 110-2. For example, the three transition thresholds may include low, medium, and high thresholds, where the 1 / 8 clock rate is used when workload indication information 123 indicating the workload on block 110-2 indicates that the workload on block 110-2 is below the low threshold level, the 1 / 4 clock rate is used when the workload indication information 123 indicating the workload on block 110-2 indicates that the workload on block 110-2 is between the low threshold level and the medium threshold level, the 1 / 2 clock rate is used when the workload indication information 123 indicating the workload on block 110-2 indicates that the workload on block 110-2 is between the medium threshold level and the high threshold level, and the fully unthrottled clock rate (i.e., the root clock 121-2) is used when the workload indication information 123 indicating the workload on block 110-2 indicates that the workload on block 110-2 is determined to be above the high threshold level. It will be understood that in cases where the throttled clock 122 supports other numbers of clock rate levels, other numbers of transition thresholds may be used.

[0038] It will be understood that although primarily introduced in connection with supporting a particular number of clock rate levels, particular clock rates for the clock rate levels, and particular clock rate transitions between adjacent clock rate levels, various other numbers of clock rate levels may be supported, various other clock rates for the clock rate levels may be supported, various other clock rate transitions between adjacent clock rate levels may be supported, etc., and various combinations thereof (i.e., since the clock throttling controller 125 may control the propagation of individual pulses of the root clock 121-2 of block 110-2 to / from the throttled clock 122 for block 110-2 individually, various combinations of pulses of the root clock 121-2 of block 110-2 may be allowed to become part of and / or prevented from becoming part of the throttled clock 122 in a manner that may support various clock rates, clock rate levels, clock rate transitions, clock rate transition thresholds, etc., and various combinations thereof and / or in a manner that may avoid specifically defining such clock rates, clock rate levels, clock rate transitions, clock rate transition thresholds, etc., and various combinations thereof).

[0039] The clock throttling controller 125 of block 110-2, although mainly described as using discrete transitions between defined clock rate levels based on a defined clock transition threshold, can also or alternatively be configured to support more continuous control of the root clock 121-2 between a defined minimum clock rate and a maximum clock rate of the clock rate range used to throttle the clock 122, to provide the throttled clock 122 for block 110-2. For example, throttling of the root clock 121-2 of block 110-2 to form the throttled clock 122 for block 110-2 can be performed such that the clock rate of the throttled clock 122 is proportional to the workload of block 110-2. For example, in a case where the root clock 121-2 operates at a free-running rate of 32 clock pulses per second and the minimum clock rate of the throttled clock is defined as 1 / 32 of the clock rate of the root clock 121-2, the clock throttling controller 125 can allow clock pulses of the root clock 121-2 to enter the throttled portion of the clock distribution tree 111-2 as the throttled clock 122 in proportion to the workload of block 110-2 (e.g., allowing 8 clock pulses to pass based on a determination that the workload 123-2 of block 110-2 is 25% of the maximum possible workload of block 110-2, allowing 10 clock pulses to pass based on a determination that the workload of block 110-2 is 30% of the maximum possible workload of block 110-2, allowing 28 clock pulses to pass based on a determination that the workload of block 110-2 is 88% of the maximum possible workload of block 110-2, etc.).

[0040] As described above, the clock throttling controller 125 of block 110-2 can be configured to control the throttling of the root clock 121-2 of block 110-2, thereby providing the throttled clock 122 for block 110-2 in various ways. For example, root clock throttling of the root clock 121-2 of block 110-2 to provide the throttled clock 122 for block 110-2 can be performed by increasing the clock rate of the throttled clock 122 based on a determination that the workload on block 110-2 has increased (or increased above a threshold defined as the transition point between the supported clock rates of the throttled clock 122), and decreasing the clock rate of the throttled clock 122 based on a determination that the workload on block 110-2 has decreased (or decreased below a threshold defined as the transition point between the supported clock rates of the throttled clock 122). In this way, when the workload on block 110-2 remains low, the throttled clock 122 for block 110-2 can be maintained at a non-zero minimum clock rate of the throttled clock range, and then increased as the workload on block 110-2 increases until the maximum unthrottled clock rate of the throttled clock range is reached (i.e., at this time the throttled clock 122 of block 110-2 is simply the free-running root clock 121-2, which operates within block 110-2 without any throttling).

[0041] The clock throttling controller 125 of block 110-2 can be configured to control the delivery of clock pulses of the root clock 121-2 of block 110-2 to the throttled portion of the clock distribution tree 111-2 of block 110-2, as the throttled clock 122 for block 110-2, based on the generation of a clock control signal 126 provided to the root clock modulator 127. The clock throttling controller 125 of block 110-2 is configured to generate the clock control signal 126 based on information indicating the workload on block 110-2, in a manner that controls the fraction of the pulses of the root clock 121-2 that are allowed to pass through the root clock modulator 127 to become the pulses of the throttled clock 122 for the clock distribution tree 111-2 of block 110-2. As Figure 1 shown, the root clock modulator 127 can be an AND gate, which is configured to accept the root clock 121-2 and the clock control signal 126 as inputs and output the throttled clock 122. In this case, when the clock control signal 126 is high, then the pulses of the root clock 121-2 are allowed to pass through the AND gate to become the pulses of the throttled clock 122 (thus causing the throttled clock 122 to be equal to the free-running root clock 121-2 as long as the clock control signal 126 remains high), while when the clock control signal 126 is low, then the pulses of the root clock 121-2 are effectively blocked from passing through the AND gate to become the pulses of the throttled clock 122 (thus causing the throttled clock 122 to be able to run at a clock rate lower than the full, unthrottled free-running clock rate of the root clock 121-2).

[0042] The clock throttling controller 125 of block 110-2 and / or the root clock modulator 127 of block 110-2 can be configured to ensure a fault-free output for the throttled clock 122 of block 110-2. The clock throttling controller 125 of block 110-2 and / or the root clock modulator 127 of block 110-2 can be configured to ensure a fault-free output for the throttled clock 122 of block 110-2 based on the use of a latch to ensure that the control signal 126 is latched when the root clock 121-2 is low (since the control signal 126 changes on the rising edge, which could cause a fault in the throttled clock 122 if the control signal 126 were directly fed into the root clock modulator 127). For example, in the case where the root clock modulator 127 is an AND logic gate, the latch can be provided by a latch that is provided at one input of the AND logic gate, where the latch accepts the pulses of the root clock 121-2 and the clock control signal and outputs a signal that is provided as the control signal to one input of the AND logic gate to ensure a fault-free output for the throttled clock 122 of block 110-2. For example, the latch can be provided by the clock throttling controller 125 to ensure a fault-free output for the throttled clock 122 of block 110-2.

[0043] It will be understood that although the description has been mainly directed to using a specific type of logic gate as the root clock modulator 127 (i.e., an AND logic gate), various other logic gates or combinations of logic gates (e.g., multiple AND gates, multiple NAND gates, etc.) can be used to provide the root clock modulator 127 that controls the propagation of the pulses of the root clock 121-2 of block 110-2 within the clock distribution tree 111-2 of block 110-2 to become the throttled clock 122 for block 110-2.

[0044] In Figure 1 it, the control of the root clock throttling for block 110-2 is implemented within the free-running clock domain of block 110-2. For example, to control the root clock throttling for block 110-2, the clock throttling controller 125 and the root clock modulator 127 are implemented within the free-running clock domain of block 110-2. The root clock throttling control logic can be implemented within the free-running clock domain because the clock control signal 126 provided to the root clock modulator 127 needs to have the ability to turn on at any clock (e.g., in this case, the root clock modulator 127 can be regarded as being arranged between the free-running clock domain part of block 110-2 and the throttled clock domain part of block 110-2, such that the input of the root clock modulator 127 that receives the root clock 121-2 is regarded as part of the free-running clock domain part of block 110-2, and the output of the root clock modulator 127 is regarded as part of the throttled clock domain part of block 110-2). It will be understood that although the description has been mainly directed to the implementation of the root clock throttling control logic within the free-running clock domain of block 110-2, at least a part of the root clock throttling control logic can be implemented within the throttled clock domain of block 110-2 (e.g., the root clock modulator 127, or a part thereof can be regarded as being arranged within the throttled clock domain of block 110-2).

[0045] It will be understood that the ASIC 100 can be implemented in various other ways to support the root clock throttling for the ASIC 100.

[0046] Figure 2 An example embodiment depicting the root clock throttling for a block as a function of the workload of the block is shown.

[0047] In Figure 2In this case, the ASIC 200 includes a free-running clock domain 210 and a throttled clock domain 240. The ASIC 200 includes: a set of input interfaces 220 from the free-running clock domain 210 to the throttled clock domain 240, and a set of output interfaces 230 from the throttled clock domain 240 to the free-running clock domain 210. The ASIC 200 also includes core logic 241 within the throttled clock domain 240. The throttled clock domain 240 receives work inputs via the set of input interfaces 220 and provides work outputs via the set of output interfaces 230. It will be understood that when mapping the Figure 2 ASIC 200 to Figure 1 the ASIC 100, the free-running clock domain 210 may correspond to the free-running clock domain of block 110-2, and the throttled clock domain 240 may correspond to the throttled clock domain of block 110-2.

[0048] In Figure 2 this case, the root clock 201 is used within the free-running clock domain 210, and the throttled clock 202 is used within the throttled clock domain 240. The free-running clock domain 210 includes a clock throttling controller 211 (which may correspond to Figure 1 the clock throttling controller 125), which is configured to determine the workload of the throttled clock domain 240 and control the throttling of the root clock 201 to form the throttled clock 202 applied to the throttled clock domain 240. This control is shown by a clock control signal 215 (which may correspond to Figure 1 the clock control signal 126), which is provided to the throttled clock domain 240 to control the throttling of the root clock 201 to provide the throttled clock 202. It will be understood that the clock control signal 215 may be applied to one or more logic gates (omitted for clarity, which may correspond to Figure 1 the root clock modulator 127), which may use the clock control signal 215 to control the clock pulses of the root clock 201 as the throttled clock 202 into the throttled clock domain 240. In this way, the root clock 201 may be throttled as a function of the workload of the throttled clock domain 240 to form the throttled clock 202.

[0049] As Figure 2As shown and further discussed below, the clock throttling controller 211 can obtain workload indication information 212 indicative of the workload on the throttled clock domain 240, for use in generating a clock control signal 215 for the throttled clock domain 240, based on inputs from the set of input interfaces 220, inputs from the core logic 241 of the throttled clock domain 240, and inputs from the set of output interfaces 230. The types of inputs used by the clock throttling controller 211 to determine the workload indication information 212 and generate the clock control signal 215 for the throttled clock domain 240 can vary depending on various factors, such as the application for which the ASIC is designed, the type of core logic 241 used, the way in which the interfaces of the core logic 241 are implemented, etc., and various combinations thereof. Some examples of combinations of input information that can be used by the clock throttling controller 211 are further described below to determine the workload indication information 212 indicative of the workload on the throttled clock domain 240, for use in generating the clock control signal 215 for the throttled clock domain 240; however, it will be understood that various other types of workload indication information can be used as a basis for generating the clock control signal 215 for the throttled clock domain 240.

[0050] As an example, the clock throttling controller 211 can increase the clock rate of the throttled clock 202 in the throttled clock domain 240 based on detecting various conditions indicative of an increasing workload on the throttled clock domain 240. For example, the clock throttling controller 211 can be based on determining that the input request queue is not empty (such that input work requests are immediately pulled into the block, rather than waiting for a potentially large number of clock pulses, where the clock rate of the throttled clock 202 is relatively low compared to the clock rate of the root clock 201), based on determining that the command queue occupancy rate exceeds a configured threshold (where it will be understood here that the occupancy rate indicates the workload pending for the block), one cycle after any input valid (which can be done for simplicity), and one cycle after any output valid (which can be done for simplicity). It will be understood that various other information indicative of the workload on the throttled clock domain 240 can be used as a basis for controlling the throttling of the root clock 201 (up to a maximum clock rate equal to the clock rate of the free-running root clock) to form the throttled clock 202 for the throttled clock domain 240.

[0051] As an example, the clock throttling controller 211 may reduce the clock rate of the throttled clock 202 in the throttled clock domain 240 based on the detection of various conditions indicating a reduction in workload on the throttled clock domain 240. For example, the clock throttling controller 211 may reduce the clock rate of the throttled clock 202 in the throttled clock domain 240 (e.g., by preventing one or more additional clock pulses of the root clock 201 from entering the clock distribution tree of the throttled clock domain 240) based on determining that the input request queue is empty (such that input work requests do not need to be pulled into the block), based on determining that the command queue occupancy rate is below a configured threshold (where it will be understood that the occupancy rate indicates the workload pending for the block), a threshold number of cycles after any input valid (which may be done for simplicity), and a threshold number of cycles after any output valid (which may be done for simplicity). It will be understood that various other information indicating the workload on the throttled clock domain 240 may be used as a basis for controlling the throttling of the root clock 201 (reducing to a predefined non-zero minimum clock rate) to form the throttled clock 202 for the throttled clock domain 240.

[0052] In Figure 2 it, communication between pseudo-synchronous clock domains may be supported in a variety of ways, which may depend on whether the communication is from a free-running clock domain (root clock) to a throttled clock domain (throttled clock) or from a throttled clock domain (throttled clock) to a free-running clock domain (root clock). For example, for communication from the free-running clock domain 210 to the throttled clock domain 240 (i.e., fast → slow), communication based on different clock rates may be supported based on one or more of the following: using a pseudo-synchronous FIFO queue, using a pulse crosser configured to pass pulses (e.g., the number of input cycles held in the normal clock domain will generate the same number of output cycles held high in the throttled clock domain), directly using signals from the free-running clock domain in the throttled clock domain if the signal itself is semi-static or there is no issue of missing activity between the clocks (e.g., a counter), etc., and various combinations thereof. For example, for communication from the throttled clock domain 240 to the free-running clock domain 210 (i.e., slow → fast), communication based on different clock rates may be supported in one or more of the following ways: using one or more pseudo-synchronous FIFO queues, using a Pulse-to-Pulse (PTP) module to transfer the signal to the normal domain (e.g., for certain types of signals that are pulses per cycle), etc., and various combinations thereof. It will be understood that inter-domain communication may be supported in various other ways.

[0053] Figure 3 depicts an example embodiment of a root clock throttling technique for forming a throttled clock in a manner that gates the root clock to preserve the timing synchronization between the root clock and the throttled clock. As Figure 3As shown, the root clock 310 is throttled to form a throttled clock 320 that is a function of the workload based on the work to be processed 330 and the input requests 340. At Figure 3 , to the left of the work-to-be-processed transition point 331, the work to be processed is relatively high, so the root clock 310 is allowed to run unthrottled (i.e., all pulses of the root clock 310 are allowed to pass, such that the throttled clock 320 is equivalent to the root clock 310). At Figure 3 , to the left of the work-to-be-processed transition point 331, the work to be processed is relatively high, so the root clock 310 is allowed to run unthrottled (i.e., all pulses of the root clock 310 are allowed to pass, such that the throttled clock 320 is equivalent to the root clock 310). At Figure 3 , to the right of the work-to-be-processed transition point 331, the work to be processed 330 drops, so the root clock 310 is throttled such that the throttled clock 320 runs at a lower clock rate (i.e., a fraction of the pulses of the root clock 310 are allowed to pass, such that the throttled clock 320 has fewer pulses than the root clock 310). At Figure 3 , when the work to be processed 330 drops to the work-to-be-processed transition point 331, the throttled clock 320 is running mainly at a reduced rate, but an input request 341 is received during this time, which temporarily causes the clock rate of the throttled clock 320 to increase (as shown by the clock pulse 342) before being reduced again based on the work to be processed 330. This illustrates how a workload indicator can be used in a way that reduces the clock rate of a block, thereby achieving significant power savings in the clock distribution tree of the block.

[0054] Figure 4 Depicts an example embodiment of a root clock throttling technique for forming a throttled clock by gating the root clock such that more useful work will be performed by blocks based on the throttled clock. As Figure 4 shown, throttling the root clock to provide a throttled clock enables more useful work to be completed per clock cycle. This can be seen based on the work transitions along the pipeline in the normal clock domain using the root clock (as shown at the top of Figure 4 ) and the work transitions along the pipeline in the throttled clock domain using a throttled clock operating at a quarter of the root clock rate (as shown at the bottom of Figure 4 ). In both cases, input work requests enter once every four normal clock cycles (the work requests are represented as A, B, C, D, and E). As shown at the top of Figure 4 , only one of the four stages shown on the left side of Figure 4 works on each clock pulse of the root clock (represented by the letters 'A' to 'E' below the clock pulses, with only one letter below each clock pulse). As shown at the bottom of Figure 4 , for each of the clock pulses N + 2, N + 3, and N + 4,Figure 4 Multiple stages out of the four stages shown on the left side are working for each clock pulse of the throttled clock. For example, the first and second stages work based on work requests B and A for clock pulse N+2, respectively. Similarly, for example, the first, second, and third stages work based on work requests C, B, and A for clock pulse N+3, respectively. Similarly, for example, the first, second, third, and fourth stages work based on work requests D, C, B, and A for clock pulse N+4, respectively. In Figure 4 , the power savings between the normal clock domain and the throttled clock domain are indicated by Figure 4 the number of instances of the letters representing the work requests shown in

[0055] It will be understood that the various example embodiments presented herein, although primarily presented for supporting power optimization for a particular type of electronic circuit (i.e., within an ASIC), can be applied to support power optimization for other types of electronic circuits, and thus, can be more generally described within the context of supporting power optimization for blocks generally used in electronic circuits.

[0056] The various example embodiments can be configured to provide a device including a block, where the block includes a set of elements configured to operate based on a clock signal applied to the block, where the block includes a clock distribution tree configured to distribute clock pulses of the clock signal to the set of elements of the block, and where the block is configured to control which clock pulses of the clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree. The first portion of the block's clock distribution tree can serve a first portion of the elements, while the second portion of the block's clock distribution tree can serve a second portion of the elements including the leaf elements of the block. The block can be configured to control which clock pulses of the clock signal are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree based on information indicating the workload on the block. The block can include a controller configured to obtain information indicating the workload on the block and generate a clock control signal based on the information indicating the workload on the block, the clock control signal being configured to control which clock pulses of the clock signal of the block are allowed to pass from a first portion of the block's clock distribution tree to a second portion of the block's clock distribution tree. Here, the device can be an electronic circuit (e.g., an IC, an ASIC, etc.) on which the block is arranged, a device including the electronic circuit on which the block is arranged, etc.

[0057] It will be understood that these example embodiments for supporting power optimization for blocks generally used in electronic circuits can be further understood by referring to Figure 5 and Figure 6 and

[0058] Figure 5 Illustrates an example embodiment of a method used by a controller of a block of an electronic circuit to support root clock throttling. It should be understood that although method 500 is primarily presented as being executed sequentially, at least some of the functions may be executed simultaneously or in a different order than Figure 5 shown. At block 501, method 500 begins. At block 510, information indicating the workload on the block is obtained by a controller of a block including a clock distribution tree configured to distribute clock signals within the block. At block 520, a clock control signal is provided by the controller of the block based on the information indicating the workload on the block, the clock control signal being configured to control which clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block. At block 599, method 500 ends. It should be understood that the various functions presented herein with respect to Figures 1 to 4 can be incorporated into Figure 5 the context of method 500.

[0059] Figure 6 Illustrates an example embodiment of a method used by a block of an electronic circuit to support root clock throttling. It will be understood that although the functions of method 600 are primarily presented as being executed serially, at least some of the functions may be executed simultaneously or in a different order than Figure 6 shown. At block 601, method 600 begins. At block 610, information indicating the workload on the block is obtained by a block including a clock distribution tree configured to distribute clock signals within the block. At block 620, which clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block is controlled based on the information indicating the workload on the block. At block 699, method 600 ends. It should be understood that the various functions presented herein with respect to Figures 1 to 4 shown can be incorporated into Figure 6 the context of method 600.

[0060] Figure 7 Illustrates an example embodiment of a computer suitable for performing the various functions presented herein.

[0061] Computer 700 includes a processor 702 (e.g., a central processing unit (CPU), a processor, a processor having a set of processor cores, a processor core of a processor, etc.) and a memory 704 (e.g., a random access memory (RAM), a read-only memory (ROM), etc.). In at least some example embodiments, computer 700 may include at least one processor and at least one memory, the at least one memory storing instructions that, when executed by the at least one processor, cause the computer to perform the various functions presented herein.

[0062] The computer 700 may also include a collaboration element 705. The collaboration element 705 may be a hardware device. The collaboration element 705 may be a process that can be loaded into the memory 704 and executed by the processor 702 to implement the various functions presented herein (in this case, for example, the collaboration element 705 (including associated data structures) may be stored on a non-transitory computer-readable medium, such as a storage device or other suitable type of storage element (e.g., magnetic drive, optical drive, etc.)).

[0063] The computer 700 may also include one or more input / output devices 706. The input / output devices 706 may include one or more of the following: user input devices (e.g., keyboard, keypad, mouse, microphone, camera, etc.), user output devices (e.g., display, speaker, etc.), one or more network communication devices or elements (e.g., input port, output port, receiver, transmitter, transceiver, etc.), one or more storage devices (e.g., tape drive, floppy drive, hard drive, optical drive, etc.), and various combinations thereof.

[0064] It will be understood that the computer 700 may represent a general architecture and functionality suitable for implementing the functional elements described herein, portions of the functional elements described herein, and various combinations thereof. For example, the computer 700 may provide a general architecture and functionality suitable for implementing one or more of the elements described herein. For example, the computer 700 may provide a general architecture and functionality that is suitable for implementing at least one of a computer configured to support the design of an electronic circuit or a portion thereof, a computer configured to utilize an electronic circuit or a portion thereof, and various combinations thereof.

[0065] It will be understood that at least some of the functions presented herein may be implemented in software (e.g., via the implementation of software on one or more processors for execution on a general-purpose computer (e.g., via execution by one or more processors) to provide a special-purpose computer, etc.) and / or may be implemented in hardware (e.g., using a general-purpose computer, one or more application-specific integrated circuits, and / or any other hardware equivalent).

[0066] It will be understood that at least some of the functions presented herein may be implemented within the hardware, e.g., as circuitry that collaborates with the processor to perform the various functions. Portions of the functions / elements described herein may be implemented as a computer program product, where computer instructions, when processed by a computer, adjust the operation of the computer such that the methods and / or techniques described herein are invoked or otherwise provided. The instructions for invoking the various methods may be stored on a fixed or removable medium (e.g., a non-transitory computer-readable medium), transmitted via a data stream in a broadcast or other signal-bearing medium, and / or stored in the memory within a computing device operating in accordance with the instructions.

[0067] It will be understood that the term "non-transitory" as used herein is a limitation of the medium itself (i.e., tangible, rather than a signal), rather than a limitation of data storage persistence (e.g., RAM vs. ROM).

[0068] It will be understood that as used herein, the phrases "at least one of <list of two or more elements>" and "at least one of the following: <list of two or more elements>" and similar phrasings, where the list of two or more elements is joined by "and" or "or", mean at least any one of the elements, or at least two or more of the elements, or at least all of the elements.

[0069] It will be understood that as used herein, the term "or" refers to a non-exclusive "or", unless otherwise specified (e.g., by use of "otherwise" or "alternatively").

[0070] It will be understood that although various embodiments in connection with the teachings presented herein have been shown and described in detail, those skilled in the art can readily devise many other different embodiments that still incorporate these teachings.

Claims

1. A device for power optimization, comprising: A block, wherein the block includes a clock distribution tree configured to distribute a clock signal within the block, wherein the block is configured to control which clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block based on information indicating a workload on the block.

2. The apparatus of claim 1 , wherein the fraction of the clock pulses of the clock signal that are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is controlled to remain within a range between a non-zero minimum value and a maximum value based on the clock signal of the block.

3. An apparatus according to any one of claims 1 to 2, wherein when the information indicative of the workload on the block indicates that activity is presented at an input interface to the block, clock pulses of the clock signal of the block are allowed to pass from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

4. An apparatus according to any one of claims 1 to 3, wherein when the information indicative of the workload on the block indicates that no activity is presented at the input interface to the block, clock pulses of the clock signal of the block are prevented from passing from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

5. An apparatus according to any one of claims 1 to 4, wherein when the information indicative of the workload on the block indicates that activity is available at an output interface from the block, clock pulses of the clock signal of the block are allowed to pass from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

6. An apparatus according to any one of claims 1 to 5, wherein when the information indicative of the workload on the block indicates that no activity is available at an output interface from the block, clock pulses of the clock signal of the block are blocked from passing from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

7. An apparatus according to any one of claims 1 to 6, wherein when the information indicating the workload on the block indicates that a measurement of the internal state of the block indicates that work is presented to the block, clock pulses of the clock signal of the block are allowed to pass from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

8. The apparatus of claim 7, wherein the measurement of internal state is based on at least one of: a measurement of occupancy of a work queue of the block, or a measurement of a number of active threads of the block.

9. The apparatus of claim 7 , wherein the number of clock pulses of the clock signal of the block that are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is based on the measurement of the internal state of the block.

10. The apparatus of claim 9, wherein the number of clock pulses of the clock signal of the block that are allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is determined based on a mapping table that maps a set of workload thresholds to a set of clock pulse fractions that will be allowed to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block.

11. An apparatus according to any one of claims 1 to 10, wherein the clock pulse of the clock signal of the block that is allowed to pass from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block is synchronized with the clock signal of the block at the leaf level of the clock distribution tree of the block.

12. The apparatus according to any one of claims 1 to 11, wherein the block comprises: a controller configured to generate a clock control signal based on the information indicative of the workload on the block, the clock control signal configured to control which clock pulses of the clock signal are allowed to pass from the first portion of the clock distribution tree for the block to the second portion of the clock distribution tree for the block; as well as A clock modulator is configured to control the passing of clock pulses of the clock signal of the block from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block based on the clock control signal.

13. The apparatus according to any one of claims 1 to 12, wherein the block comprises: a controller configured to generate a clock control signal based on the information indicative of the workload on the block, the clock control signal configured to control which clock pulses of the clock signal are allowed to pass from the first portion of the clock distribution tree for the block to the second portion of the clock distribution tree for the block; as well as A clock modulator comprising: a clock input configured to receive the clock signal of the block, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output the clock pulse of the clock signal of the block that is allowed to pass from the first part of the clock distribution tree of the block to the second part of the clock distribution tree of the block.

14. The apparatus of any one of claims 1 to 13, wherein the block comprises an interface configured to support communication between the first portion of the clock distribution tree of the block and the second portion of the clock distribution tree of the block.

15. The apparatus of claim 14, wherein the interface comprises a pseudo-synchronous first-in-first-out queue.

16. The apparatus of claim 14, wherein the interface comprises at least one of: a pulse interleaver, or a pulse to pulse module.

17. The apparatus of any one of claims 1 to 16, wherein the block comprises a processor and a memory.

18. The apparatus according to any one of claims 1 to 17, wherein the apparatus is a device comprising an electronic circuit, the block being placed on the electronic circuit.

19. The device according to any one of claims 1 to 17, wherein the device is an electronic circuit and the block is placed on the electronic circuit.

20. The device according to any one of claims 1 to 17, wherein the device is an integrated circuit and the block is placed on the integrated circuit.

21. The apparatus according to any one of claims 1 to 17, wherein the apparatus is an application specific integrated circuit, the block being placed on the application specific integrated circuit.

22. A method for power optimization, comprising: obtaining, by a block including a clock distribution tree, information indicative of a workload on the block, the clock distribution tree being configured to distribute a clock signal within the block; as well as Based on the information indicative of the workload on the block, controlling which clock pulses of the clock signal are allowed to pass from the first portion of the clock distribution tree for the block to a second portion of the clock distribution tree for the block.

23. A device for power optimization, comprising: A block, wherein the block comprises a set of elements, the set of elements being configured to operate based on a clock signal applied to the block, wherein the block comprises a clock distribution tree, the clock distribution tree being configured to distribute clock pulses of the clock signal to the set of elements of the block, wherein the block is configured to control which of the clock pulses of the clock signal are allowed to pass from a first portion of the clock distribution tree of the block to a second portion of the clock distribution tree of the block based on information indicating a workload on the block.

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