Method for manufacturing high-power nitride semiconductor microwave transistor on gallium nitride substrate

Abstract

The invention discloses a method for manufacturing a high-power nitride semiconductor microwave transistor on a gallium nitride substrate. The method mainly solves the problems that an existing device has a parasitic electric leakage channel at a homoepitaxial interface and is low in breakdown voltage. According to the scheme, the method comprises the following steps: firstly, selecting a p-type gallium nitride single-crystal substrate, carrying out surface pretreatment on the p-type gallium nitride single-crystal substrate to obtain a p-type gallium nitride single-crystal substrate containing a p-type AlN electric leakage isolation layer, and then sequentially growing a GaN channel layer, an AlN insertion layer and a barrier layer on the pretreated substrate; and finally, preparing an insulated gate dielectric layer and a gate electrode on the barrier layer, and manufacturing a source electrode and a drain electrode on two sides to complete device manufacturing. Through in-situ compensation of donor impurities based on the p-type AlN electric leakage isolation layer and ion implantation, complete isolation of a parasitic electric leakage channel at a homoepitaxial interface and a 2DEG conductive channel at a homoepitaxial GaN heterojunction interface is realized, transverse electric leakage of the device is effectively inhibited, and the voltage endurance capability and the output power of the device are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a method for manufacturing a high-power nitride semiconductor microwave transistor on a gallium nitride single crystal substrate, which can be used to manufacture high-efficiency solid-state microwave power amplifiers and radio frequency terminal components. Background Art

[0002] Gallium nitride (GaN) materials have wide bandgap, high electron saturation rate, high temperature resistance and radiation resistance. In GaN heterojunction materials, there is a two-dimensional electron gas (2DEG) with high electron mobility and high surface density formed by polarization effect. Therefore, GaN semiconductor materials have become a research hotspot in the field of microelectronics technology, especially in solid-state microwave power devices. High electron mobility transistor (HEMT) based on GaN heterostructure is the core structure of nitride semiconductor microwave transistor. The current mainstream GaNHEMT devices are mainly prepared by heteroepitaxial growth on silicon Si, silicon carbide SiC and sapphire substrates. The large thermal expansion coefficient and lattice mismatch in heteroepitaxial materials will produce extremely high density dislocation defects, which not only deteriorate the 2DEG transport characteristics, but also significantly reduce the breakdown voltage of the device, which is extremely unfavorable to improving the device output power and working reliability.

[0003] In recent years, with the development of GaN single crystal substrate preparation technology and the expansion of market demand, the quality and process stability of GaN single crystals have been significantly improved, resulting in the expansion of wafer size and the reduction of preparation costs. Therefore, the homoepitaxial growth technology of GaN semiconductor microwave transistors has become a research focus.

[0004] In the existing document with the publication number CN113555431A and the name "Homoepitaxial gallium nitride high electron mobility transistor based on P-type GaN leakage isolation layer and manufacturing method", a substrate is disclosed, which uses a self-supporting gallium nitride substrate or a thick film gallium nitride substrate material, and a P-type GaN leakage isolation layer and a GaN buffer layer are arranged between the substrate and the channel layer, and the upper part of the barrier layer is provided with an insulating gate dielectric layer and a gate electrode in sequence, and both sides are ohmic contact areas, and the source and drain electrodes are arranged on the ohmic contact area. Transistor. Although the parasitic leakage problem of Si impurities at the homoepitaxial interface has been solved to a certain extent, the structure has problems such as poor uniformity and high process difficulty, and it is difficult to reproduce in its preparation process.

[0005] The traditional structure of a GaN HEMT device with homoepitaxy on a gallium nitride substrate includes, from bottom to top, a gallium nitride substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, a barrier layer, etc. In this structure, the surface of the gallium nitride single crystal substrate is prone to adsorb shallow-level donor impurities such as silicon (Si) and oxygen (O), forming parasitic conductive channels at the interface between the GaN epitaxial layer and the gallium nitride single crystal substrate. This will generate high off-state leakage current in the homoepitaxial GaN HEMT device, resulting in a large gap between the breakdown voltage and output power of the device and the theoretical expected values, seriously restricting the performance advantages of the gallium nitride single crystal substrate and its application in nitride semiconductor microwave transistors. Summary of the Invention

[0006] The object of the present invention is to address the deficiencies of the above-mentioned prior art and propose a method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate. By means of a pretreatment method for a gallium nitride single crystal substrate based on a p-type AlN leakage isolation layer and ion implantation to self-compensate donor impurities, in-situ compensation of donor impurities such as Si and O adsorbed on the surface of the gallium nitride single crystal substrate is achieved, parasitic leakage channels at the homoepitaxial interface are eliminated, the off-state leakage current and radio frequency loss of the homoepitaxial gallium nitride radio frequency transistor are reduced, and the breakdown voltage and output power of the device are increased. At the same time, the p-type AlN leakage isolation layer has the characteristic of self-organized nucleation after high-temperature annealing, which can inhibit the dislocation proliferation of the material of the homoepitaxial gallium nitride radio frequency transistor, ensure that the quality of the homoepitaxial GaN material is equivalent to that of the gallium nitride single crystal substrate, and further improve the working reliability of the homoepitaxial gallium nitride radio frequency transistor.

[0007] To achieve the above object, the technical solution proposed by the present invention is as follows:

[0008] A method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate, the transistor includes, from bottom to top, a gallium nitride single crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer, wherein the gallium nitride single crystal substrate is a p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer obtained by surface pretreatment. The implementation steps of the method of the present invention are as follows:

[0009] 1) Select a p-type gallium nitride single crystal substrate and perform pretreatment on it:

[0010] 1.1) Grow a polycrystalline GaN sacrificial layer on the p-type gallium nitride single crystal substrate;

[0011] 1.2) Inject ions into the p-type gallium nitride single crystal substrate through the polycrystalline GaN sacrificial layer;

[0012] 1.3) Use hydrogen atom etching technology to remove the polycrystalline GaN sacrificial layer, obtaining a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface;

[0013] 1.4) Grow a p-type AlN leakage isolation layer on a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on its surface, and planarize the surface of the p-type gallium nitride single crystal substrate;

[0014] 1.5) Anneal the p-type gallium nitride single crystal substrate with the p-type AlN leakage isolation layer grown thereon to achieve self-organized nucleation of the p-type AlN leakage isolation layer, and obtain a quasi-patterned substrate, thus completing the pre-treatment process;

[0015] 2) Sequentially grow a GaN channel layer, an AlN insertion layer, and a barrier layer on the quasi-patterned substrate, that is, the p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer after surface pre-treatment;

[0016] 3) Etch the barrier layer to the channel layer to form a source electrode and a drain electrode on both sides thereof;

[0017] 4) Deposit an insulating gate dielectric layer on the upper surface of the barrier layer, and form a gate electrode on this dielectric layer to complete the device fabrication.

[0018] The present invention has the following advantages compared with the prior art:

[0019] First, since the present invention provides a polycrystalline GaN sacrificial layer, the irregular crystal orientations in this layer can regulate the path of the implanted high-energy ions, making the concentration peak located at the parasitic leakage channel on the surface of the gallium nitride single crystal substrate, ensuring that the implanted ions compensate for the Si and O impurities adsorbed on the surface of the gallium nitride single crystal substrate, and achieving the purpose of isolating the parasitic leakage channel.

[0020] Second, the p-type AlN leakage isolation layer adopted in the present invention can self-organize nucleate after annealing, forming the effect of a quasi-patterned substrate, thereby significantly improving the crystallization quality of its homoepitaxial GaN material and avoiding the proliferation of dislocations in the homoepitaxial GaN material.

[0021] Third, the p-type AlN leakage isolation layer adopted in the present invention self-organizes nucleate and forms island-shaped nucleation points after annealing. At the same time, after the hydrogen atoms etch the polycrystalline GaN sacrificial layer, the irregularly distributed pit defects left on the surface of the gallium nitride single crystal substrate are entered. The p-type AlN leakage isolation layer materials in the island-shaped nucleation points and the pit defects are distributed in a zigzag manner, densely covering the entire surface of the gallium nitride single crystal substrate, realizing the spatial isolation between the parasitic leakage channel of Si impurities on the surface of the gallium nitride substrate and the 2DEG conductive channel at the heterointerface of the homoepitaxial GaN, and preventing the lateral conduction of the parasitic leakage channel of Si impurities on the surface of the gallium nitride substrate, and overall improving the lateral breakdown voltage capability of the device.

[0022] Fourth, the p-type AlN leakage isolation layer adopted in the present invention is a wide-bandgap material, which can act as a back barrier, improve the confinement and transport characteristics of 2DEG in the channel layer at the heterointerface of the active region of the gallium nitride device, and suppress vertical leakage, thereby improving the longitudinal breakdown voltage capability of the device.

[0023] Fifth, the pre-treatment process of the gallium nitride single crystal substrate in the present invention has controllable cost and simple operation, providing extremely high freedom and feasibility for the fabrication of a homoepitaxial nitride semiconductor radio frequency transistor on the gallium nitride single crystal substrate. Description of the Drawings

[0024] Figure 1 is a schematic flow chart of a method for pre-treating a gallium nitride single crystal substrate provided by an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the overall structure of a high-power nitride semiconductor microwave transistor on a gallium nitride substrate in the present invention;

[0026] Figure 3 is a schematic flow chart of the fabrication of a high-power nitride semiconductor microwave transistor on a gallium nitride substrate in the present invention;

[0027] Figure 4 is a measured cross-sectional transmission electron microscope image of the material in an embodiment of the present invention. Detailed Embodiments

[0028] The present invention will be further described below with reference to the drawings.

[0029] Example 1. Referring to the attached Figures 1-3 , a method for fabricating a high-power nitride semiconductor microwave transistor on a gallium nitride substrate proposed by the present invention, the transistor includes a gallium nitride single crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer from bottom to top, wherein the gallium nitride single crystal substrate is a p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer obtained by surface pre-treatment. The method for fabricating the high-power nitride semiconductor microwave transistor on the gallium nitride substrate specifically includes the following steps:

[0030] Step 1) Select a p-type gallium nitride single crystal substrate, the doping element of which is any one of C, Fe, and Mn; and perform pre-treatment on it:

[0031] 1.1) Grow a polycrystalline GaN sacrificial layer on the p-type gallium nitride single crystal substrate, and adopt any one of PVD, MOCVD, MBE, HVPE, PLD, and ALD growth methods. In this embodiment, PVD or MOCVD is preferably adopted;

[0032] 1.2) Inject ions into the p-type gallium nitride single crystal substrate through the polycrystalline GaN sacrificial layer; in this embodiment, when performing this step, specifically, an ion implantation process is adopted, and any one or several of C, Fe, and Mg ions are injected into the p-type gallium nitride single crystal substrate through the polycrystalline GaN sacrificial layer, and the injection dosage is 1×10 12 cm -2 ~1×1014 cm -2 The implantation energy is 40 keV to 60 keV, and the implantation method is vertical implantation;

[0033] 1.3) The polycrystalline GaN sacrificial layer is removed by hydrogen atom etching technology to obtain a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface;

[0034] 1.4) A p-type AlN leakage isolation layer is grown on the p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface to flatten the surface of the p-type gallium nitride single crystal substrate.

[0035] In this embodiment, when growing the p-type AlN leakage isolation layer, any one of PVD, MOCVD, MBE, HVPE, PLD, and ALD growth methods is adopted. Preferably, PVD or MOCVD is used to grow a p-type AlN leakage isolation layer with a thickness of 3 nm - 15 nm; and the p-type doping element is any one or several of Mn, Fe, and Mg;

[0036] 1.5) The p-type gallium nitride single crystal substrate with the p-type AlN leakage isolation layer grown thereon is annealed. In this embodiment, the annealing temperature is preferably set to 800 °C - 1200 °C, and the annealing time is 40 s - 60 s; self-organized nucleation occurs in the p-type AlN leakage isolation layer, realizing a quasi-patterned substrate and completing the pretreatment process.

[0037] Step 2) A GaN channel layer, an AlN insertion layer, and a barrier layer are sequentially grown on the quasi-patterned substrate, that is, the p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer after surface pretreatment; the growth methods are all MOCVD or MBE; the thicknesses are 500 nm - 2000 nm, 1 nm - 2 nm, and 3 nm - 30 nm in sequence. The barrier layer is any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN.

[0038] Step 3) The barrier layer is etched to the channel layer, and source and drain electrodes are formed on both sides thereof; specifically, it is formed in the following manner: First, a photoresist is used as a mask on the barrier layer to define the source and drain electrode patterns; then, a dry etching method is used to etch the barrier layer to the channel layer to form grooves in the source and drain electrode regions; finally, an electron beam evaporation process is used to deposit a Ti / Al / Ni / Au metal combination in the grooves of the source and drain electrode regions and anneal it to form the source and drain electrodes.

[0039] Step 4) Deposit an insulating gate dielectric layer on the upper surface of the barrier layer and form a gate electrode on this dielectric layer. Specifically, deposit the insulating gate dielectric on the surface of the barrier layer by ALD process, define the gate electrode pattern on the surface of the insulating gate dielectric layer by photolithography process, and then deposit a Ni / Au metal combination on the insulating gate dielectric layer by electron beam evaporation process to form the gate electrode; finally, complete the device fabrication.

[0040] Example 2. The overall implementation steps of the preparation method provided in this example are the same as those in Example 1. Now, refer to Figure 3 (a)-(e) in the attached drawings to further describe in detail the pretreatment method of the gallium nitride single crystal substrate involved in the present invention; pretreat the p-type gallium nitride single crystal substrate doped with C, the C ion implantation dosage is 1×10 14 cm -2 , the implantation energy is 60 keV; the doping element of the p-type AlN leakage isolation layer is Mg, and the thickness is 3 nm; the annealing temperature is 800 °C and the annealing time is 60 s. The implementation steps are as follows:

[0041] Step 1. Deposit a polycrystalline GaN sacrificial layer, as Figure 3 (a).

[0042] Deposit a polycrystalline GaN sacrificial layer on the p-type gallium nitride single crystal substrate doped with C by PVD method. The thickness of the polycrystalline GaN sacrificial layer is 10 nm.

[0043] Step 2. C ion implantation, as Figure 3 (b).

[0044] Inject high-energy ions into the p-type gallium nitride single crystal substrate through the polycrystalline GaN sacrificial layer, and the implanted ions are C ions. The conditions of ion implantation are: the implantation dosage is 1×10 14 cm -2 , and the implantation energy is 60 keV.

[0045] Step 3. Hydrogen atom etching, as Figure 3 (c).

[0046] Use hydrogen atom etching technology to etch and remove the polycrystalline GaN sacrificial layer.

[0047] Step 4. Deposit a p-type AlN leakage isolation layer, as Figure 3 (d).

[0048] Deposit a p-type AlN leakage isolation layer on the p-type gallium nitride single crystal substrate from which the polycrystalline GaN sacrificial layer has been removed by PVD method. The thickness of the p-type AlN leakage isolation layer is 3 nm and the p-type doping element is Mg.

[0049] Step 5. Annealing treatment, as Figure 3 (e).

[0050] Anneal the p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer grown on it. The annealing conditions are: the annealing temperature is 800 °C, and the annealing time is 60 s.

[0051] Example 3. The overall implementation steps of the preparation method provided in this example are the same as those in Example 1. Now, refer to Figure 3 (a)-(e) in the attached drawings to further describe in detail the pretreatment method of the gallium nitride single crystal substrate involved in the present invention; pretreat the p-type gallium nitride single crystal substrate doped with Mn, the Fe ion implantation dosage is 1×10 13 cm -2 , the implantation energy is 50 keV; the doping element of the p-type AlN leakage isolation layer is Fe, and the thickness is 10 nm; the annealing temperature is 1000 °C, and the annealing time is 50 s. The implementation steps are as follows:

[0052] Step 1. Deposit a polycrystalline GaN sacrificial layer by MOCVD technology, as Figure 3 (a).

[0053] Deposit a polycrystalline GaN sacrificial layer on the p-type gallium nitride single crystal substrate doped with Mn by MOCVD technology. The thickness of the polycrystalline GaN sacrificial layer is 20 nm.

[0054] Step 2. Fe ion implantation treatment, as Figure 3 (b).

[0055] Put the p-type gallium nitride single crystal substrate with a deposited polycrystalline GaN sacrificial layer into the ion implantation chamber, set the implanted ion type as Fe ions, the implantation dosage is 1×10 13 cm -2 , and the implantation energy is 50 keV.

[0056] Step 3. Hydrogen atom etching, as Figure 3 (c).

[0057] Use hydrogen atom etching technology to etch and remove the polycrystalline GaN sacrificial layer.

[0058] Step 4. Deposit a p-type AlN leakage isolation layer by MOCVD technology, as Figure 3 (d).

[0059] Set the process conditions of the temperature at 800 °C, the pressure at 40 Torr, the ammonia flow rate at 1500 sccm, the nitrogen flow rate at 1000 sccm, the aluminum source flow rate at 3 sccm, and the iron source flow rate at 10 sccm, and deposit a p-type AlN leakage isolation layer with a thickness of 10 nm on the p-type gallium nitride single crystal substrate from which the polycrystalline GaN sacrificial layer has been removed.

[0060] Step 5. Annealing treatment, as Figure 3 (e).

[0061] Under the process conditions of an annealing temperature of 1000 °C and an annealing time of 50 s, the p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer grown on it is annealed.

[0062] Example 4. The overall implementation steps of the preparation method provided in this example are the same as those in Example 1. Now, with reference to (a)-(e) in the appendix Figure 3 the pretreatment method of the gallium nitride single crystal substrate involved in the present invention is further described in detail; the pre-treated Fe-doped p-type gallium nitride single crystal substrate, the Mn ion implantation dosage is 1×10 12 cm -2 , the implantation energy is 40 keV; the doping element of the p-type AlN leakage isolation layer is Mn, and the thickness is 15 nm; the annealing temperature is 1200 °C and the annealing time is 40 s. The implementation steps are as follows:

[0063] Step A. Depositing a polycrystalline GaN sacrificial layer, as Figure 3 (a).

[0064] Using MBE technology, a polycrystalline GaN sacrificial layer with a thickness of 30 nm is deposited on the Fe-doped p-type gallium nitride single crystal substrate.

[0065] Step B. Mn ion implantation treatment, as Figure 3 (b).

[0066] The p-type gallium nitride single crystal substrate with the deposited polycrystalline GaN sacrificial layer is placed in an ion implantation chamber, and under the conditions of an implantation dose of 1×10 12 cm -2 and an implantation energy of 40 keV, Mn ion implantation is carried out in a vertical implantation form.

[0067] Step C. Hydrogen atom etching, as Figure 3 (c).

[0068] Using hydrogen atom etching technology to etch and remove the polycrystalline GaN sacrificial layer.

[0069] Step D. Depositing a p-type AlN leakage isolation layer, as Figure 3 (d).

[0070] Using MBE technology, at a temperature of 600 °C, a nitrogen flow rate of 1.6 sccm, an equivalent equilibrium vapor pressure of the aluminum beam current of 6.5×10 -7 Torr, and an equivalent equilibrium vapor pressure of the manganese beam current of 2.5×10 -8 Torr, a p-type AlN leakage isolation layer with a thickness of 15 nm is deposited on the p-type gallium nitride single crystal substrate from which the polycrystalline GaN sacrificial layer has been removed.

[0071] Step E. Annealing treatment, as Figure 3(e).

[0072] Under the process conditions of an annealing temperature of 1200 °C and an annealing time of 40 s, annealing treatment is performed on a p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer grown thereon.

[0073] Example 5. The overall implementation steps of the preparation method provided in this example are the same as those in Example 1. Now, with reference to (f)-(k) in the appendix Figure 3 further gives the detailed process of successively growing a GaN channel layer, an AlN insertion layer, and a barrier layer on a p-type gallium nitride single crystal substrate with a p-type AlN leakage isolation layer after surface pretreatment, and finally completing the device preparation:

[0074] Step (1): Deposit a GaN channel layer, as Figure 3 (f).

[0075] Using MOCVD technology, under the process conditions of a temperature of 1200 °C, a pressure of 40 Torr, an ammonia flow rate of 3500 sccm, a hydrogen flow rate of 3000 sccm, and a gallium source flow rate of 200 sccm, deposit a GaN channel layer with a thickness of 500 nm on the p-type AlN isolation layer.

[0076] Step (2): Deposit an AlN insertion layer, as Figure 3 (g).

[0077] Using MOCVD technology, under the process conditions of a temperature of 1200 °C, a pressure of 40 Torr, an ammonia flow rate of 3500 sccm, a hydrogen flow rate of 3000 sccm, and an aluminum source flow rate of 20 sccm, deposit a 2-nm AlN insertion layer on the GaN channel layer.

[0078] Step (3): Deposit Al 0.25 Ga 0.75 N barrier layer, as Figure 3 (h).

[0079] Using MOCVD technology, under the process conditions of a temperature of 1200 °C, a pressure of 40 Torr, an ammonia flow rate of 3500 sccm, a hydrogen flow rate of 3000 sccm, a gallium source flow rate of 200 sccm, and an aluminum source flow rate of 20 sccm, deposit an Al 0.25 Ga 0.75 N barrier layer with a thickness of 25 nm on the AlN insertion layer.

[0080] Step (4): Dry etching to form grooves in the source electrode and drain electrode regions, as Figure 3 (i).

[0081] In Al 0.25 Ga 0.75Using photoresist as a mask on the N barrier layer, the source and drain electrode patterns are defined. Using dry etching technology, under the process conditions of a Cl 2 flow rate of 18 sccm, a reaction chamber pressure of 12 mTorr, and an electrode power of 160 W, the Al 0.25 Ga 0.75 N barrier layer and the AlN insertion layer on the surface of the GaN channel layer in the source and drain electrode regions are removed to form grooves in the source and drain electrode regions.

[0082] Step (5): Fabricate the source and drain electrodes, as shown in Figure 3 (j).

[0083] Using electron beam evaporation process, under the process conditions of a vacuum less than 1.2×10 -3 Pa, a power of 500 W, and an evaporation rate of , a Ti / Al / Ni / Au metal combination with a thickness of 0.02 μm / 0.14 μm / 0.05 μm / 0.04 μm is deposited on the grooves in the source and drain electrode regions and annealed in a nitrogen atmosphere at 860 °C to form the source and drain electrodes.

[0084] Step (6): Fabricate the gate electrode, as shown in Figure 3 (k).

[0085] Using ALD process to deposit the insulating gate dielectric, using photolithography process to define the gate electrode pattern on the surface of the insulating gate dielectric layer; using electron beam evaporation technology, under the process conditions of a vacuum less than 1.2×10 -3 Pa, a power of 500 W, and an evaporation rate of , a Ni / Au metal combination with a thickness of 0.05 μm / 0.15 μm is deposited on the insulating gate dielectric layer to form the gate, and the device fabrication is completed.

[0086] The parts not described in detail in the present invention belong to the common general knowledge of those skilled in the art.

[0087] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Obviously, for those skilled in the art, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the materials mentioned in the above embodiments for the p-type AlN leakage isolation layer, any one of p-type InAlN, p-type AlN, p-type InAlGaN, p-type BAlN, p-type ScAlN, p-type AlPN, p-type BPN can be used. However, these corrections and changes based on the idea of the present invention are still within the scope of the claims of the present invention.

Claims

1. A method for manufacturing a high-power nitride semiconductor microwave transistor on a gallium nitride substrate, wherein the transistor comprises, from bottom to top, a gallium nitride single crystal substrate, a GaN channel layer, an AlN insertion layer, and a barrier layer, characterized in that: The substrate is subjected to surface pretreatment to obtain a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer; the implementation steps of the method include the following: 1) Select a p-type gallium nitride single crystal substrate and pre-treat it: 1.1) growing a polycrystalline GaN sacrificial layer on a p-type gallium nitride single crystal substrate; 1.2) Implanting ions into the p-type gallium nitride single crystal substrate through a polycrystalline GaN sacrificial layer; 1.3) Using hydrogen atom etching technology to remove the polycrystalline GaN sacrificial layer, a p-type gallium nitride single crystal substrate with irregularly distributed pit defects on the surface is obtained; 1.4) growing a p-type AlN leakage isolation layer on a p-type gallium nitride single crystal substrate having irregularly distributed pit defects on the surface, and flattening the surface of the p-type gallium nitride single crystal substrate; 1.5) Annealing the p-type gallium nitride single crystal substrate on which the p-type AlN leakage isolation layer is grown to achieve self-organized nucleation of the p-type AlN leakage isolation layer, thereby obtaining a quasi-patterned substrate and completing the pretreatment process; 2) sequentially growing a GaN channel layer, an AlN insertion layer, and a barrier layer on a quasi-patterned substrate, i.e., a p-type gallium nitride single crystal substrate containing a p-type AlN leakage isolation layer after surface pretreatment; 3) etching the barrier layer to the channel layer, and forming a source electrode and a drain electrode on both sides thereof; 4) An insulating gate dielectric layer is deposited on the upper surface of the barrier layer, and a gate electrode is formed on the dielectric layer to complete the device manufacturing.

2. The method according to claim 1, characterized in that: Step 1) The p-type gallium nitride single crystal substrate is doped with any one of C, Fe and Mn.

3. The method according to claim 1, characterized in that: In step 1.1), a polycrystalline GaN sacrificial layer is grown on a p-type gallium nitride single crystal substrate using any one of PVD, MOCVD, MBE, HVPE, PLD, and ALD growth methods.

4. The method according to claim 1, characterized in that: Step 1.2) The ion implantation is specifically to use an ion implantation process to implant any one or more ions of C, Fe, and Mg into the p-type gallium nitride single crystal substrate through the polycrystalline GaN sacrificial layer, with an implantation dosage of 1×10 12 cm -2 ~1×10 14 cm -2 , the injection energy is 40keV~60keV.

5. The method according to claim 1, characterized in that: In step 1.4), a p-type AlN leakage isolation layer is grown by any one of PVD, MOCVD, MBE, HVPE, PLD, and ALD, and the p-type doping element is any one or more of Mn, Fe, and Mg.

6. The method according to claim 1, characterized in that: In step 2), the GaN channel layer, AlN insertion layer, and barrier layer are all grown by MOCVD or MBE; their thicknesses are 500nm-2000nm, 1nm-2nm, and 3nm-30nm, respectively.

7. The method according to claim 6, characterized in that: The barrier layer is any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN.

8. The method according to claim 1, characterized in that: Step 3) The source electrode and the drain electrode are formed in the following manner: first, a photoresist is used as a mask on the barrier layer to define the source electrode and the drain electrode patterns; then, a dry etching method is used to etch the barrier layer to the channel layer to form grooves in the source electrode and drain electrode regions; finally, an electron beam evaporation process is used to deposit a Ti / Al / Ni / Au metal combination in the grooves in the source electrode and drain electrode regions, and annealing is performed to form the source electrode and the drain electrode.

9. The method according to claim 1, characterized in that: Step 4) deposits an insulating gate dielectric layer on the upper surface of the barrier layer, and forms a gate electrode on the dielectric layer. Specifically, an insulating gate dielectric is deposited on the surface of the barrier layer using an ALD process, a gate electrode pattern is defined on the surface of the insulating gate dielectric layer using a photolithography process, and then a Ni / Au metal combination is deposited on the insulating gate dielectric layer using an electron beam evaporation process to form a gate electrode.

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