Wiring method and device of 2.5 D stacked chip, storage medium and electronic equipment

Abstract

The invention discloses a wiring method and device of 2.5 D stacked chips, a storage medium and electronic equipment, and the wiring method of the 2.5 D stacked chips comprises the steps: obtaining a minimum inclusion rectangle of each internet on a chip; constructing an R-Tree data structure based on the minimum inclusion rectangle; combining the nodes of the R-Tree data structure to form a to-be-wired group; dividing the area to which the to-be-wired group belongs into a plurality of regular grids, and counting the number of the minimum included rectangles covered on each regular grid to form a resource demand matrix; determining a wiring sequence of each internet in the to-be-wired group based on the resource demand matrix; and according to the wiring sequence, wiring the internetworks in the to-be-wired group in sequence. According to the invention, the wiring efficiency of the 2.5 D stacked chip can be improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of integrated circuit technology, and in particular, to a wiring method, device, storage medium, and electronic device for a 2.5D stacked chip. Background Art

[0002] As the integrated circuit process technology evolves towards smaller nodes, the 2.5D packaging technology, as an important means to improve system performance, reduce power consumption, and increase integration density, has been widely used in fields such as high-performance computing, artificial intelligence, and server chips. A 2.5D stacked chip usually integrates multiple die on the same interposer (such as a silicon interposer) to achieve high-speed interconnection of different functional modules.

[0003] In a 2.5D stacked chip, the interconnection network between die needs to be wired on the interposer. Due to the physical concentration and interconnection density of communication between die, the wiring resource requirements in some areas are significantly higher than those in other areas, resulting in local congestion.

[0004] Currently, two strategies, global wiring or detailed wiring, are usually adopted. However, regardless of whether it is global wiring or detailed wiring, a trial wiring method is generally used, which is prone to the situation where the previously wired interconnection network occupies key wiring resources, and the later wired interconnection network needs to be repeatedly torn up and re-wired due to insufficient wiring resources. The randomness of tearing up and re-wiring leads to low wiring efficiency. Summary of the Invention

[0005] Embodiments of the present application provide a wiring method, device, storage medium, and electronic device for a 2.5D stacked chip, which can improve the wiring efficiency of the 2.5D stacked chip.

[0006] In a first aspect, embodiments of the present application provide a wiring method for a 2.5D stacked chip, including: Obtaining the Minimum Bounding Rectangle (MBR) of each interconnection network on the chip; Constructing an R-Tree data structure based on the Minimum Bounding Rectangle; Performing a merging process on the nodes of the R-Tree data structure to form a group of networks to be wired; Dividing the area where the group of networks to be wired is located into a number of regular grids, and counting the number of Minimum Bounding Rectangles covered on each regular grid to form a resource demand matrix; Determining the wiring order of each interconnection network in the group of networks to be wired based on the resource demand matrix; Wiring each of the interconnection networks in the group of networks to be wired in sequence according to the wiring order.

[0007] In the wiring method of the 2.5D stacked chip provided in the embodiments of the present application, determining the wiring order of each interconnection network in the to-be-wired group based on the resource requirement matrix includes: Performing gradient analysis on the resource requirement matrix to obtain a key area; Moving the interconnection networks in the key area from the to-be-wired group to the wiring order list; Updating the resource requirement matrix and returning to perform the step of performing gradient analysis on the resource requirement matrix to obtain a key area until all the interconnection networks in the to-be-wired group are moved to the wiring order list, so as to obtain the wiring order of each interconnection network in the to-be-wired group.

[0008] In the wiring method of the 2.5D stacked chip provided in the embodiments of the present application, performing gradient analysis on the resource requirement matrix to obtain a key area includes: Using a Sobel operator to calculate the first gradient of the resource requirement matrix in the horizontal direction and the second gradient in the vertical direction respectively; Determining the key area based on the first gradient and the second gradient.

[0009] In the wiring method of the 2.5D stacked chip provided in the embodiments of the present application, determining the key area based on the first gradient and the second gradient includes: Determining candidate areas where both the first gradient and the second gradient are zero, and identifying the edge points of the candidate areas; Obtaining the resource requirement values of the edge points and the resource requirement values of their adjacent non-zero gradient points; Comparing the resource requirement values of the edge points with the resource requirement values of the adjacent non-zero gradient points, and determining the key area according to the comparison result.

[0010] In the wiring method of the 2.5D stacked chip provided in the embodiments of the present application, merging the nodes of the R-Tree data structure to form a to-be-wired group includes: Obtaining the first network direction of each leaf node in the R-Tree data structure; Based on the first network direction, sequentially merging the leaf nodes of each minimum non-leaf node in the R-Tree data structure to form a to-be-wired group.

[0011] In the wiring method of the 2.5D stacked chip provided in the embodiments of the present application, sequentially merging the leaf nodes of each minimum non-leaf node in the R-Tree data structure based on the first network direction to form a to-be-wired group includes: Randomly determine a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure; According to the first network direction, determine whether multiple leaf nodes in the target non-leaf node meet the merging condition; If all leaf nodes in the target non-leaf node meet the merging condition, delete the target non-leaf node and merge all leaf nodes in the target non-leaf node into a new leaf node; If some leaf nodes in the target non-leaf node meet the merging condition, merge the part of the leaf nodes that meet the merging condition into a new leaf node, mark the target non-leaf node as processed, and retain the unmerged leaf nodes; Return to execute the step of randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure until all minimum non-leaf nodes are processed, generate a new R-Tree data structure, and use each leaf node in the new R-Tree data structure as a wiring group to be routed.

[0012] In the wiring method of the 2.5D stacked chip provided in the embodiment of the present application, the obtaining the first network direction of each leaf node in the R-Tree data structure includes: Obtain the second network direction of the interconnected networks of each leaf node in the R-Tree data structure; Determine the first network direction of each leaf node according to the second network direction.

[0013] In a second aspect, an embodiment of the present application provides a wiring device for a 2.5D stacked chip, including: A rectangle obtaining unit, configured to obtain the minimum enclosing rectangle of each interconnected network on the chip; A structure building unit, configured to build an R-Tree data structure based on the minimum enclosing rectangle; A node merging unit, configured to perform a merging process on the nodes of the R-Tree data structure to form a wiring group to be routed; A matrix forming unit, configured to divide the area to which the wiring group belongs into several regular grids, and count the number of minimum enclosing rectangles covered on each regular grid to form a resource requirement matrix; An order determining unit, configured to determine the routing order of each interconnected network in the wiring group based on the resource requirement matrix; A network routing unit, configured to route each interconnected network in the wiring group in sequence according to the routing order.

[0014] In a third aspect, the present application provides a storage medium storing a plurality of instructions adapted to be loaded by a processor to execute the wiring method for a 2.5D stacked chip according to any one of the above.

[0015] In a fourth aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. Wherein, when the processor executes the computer program, it implements the wiring method for a 2.5D stacked chip according to any one of the above.

[0016] In summary, the wiring method for a 2.5D stacked chip provided by the embodiments of the present application includes: obtaining the minimum bounding rectangle of each interconnect network on the chip; constructing an R-Tree data structure based on the minimum bounding rectangle; performing a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed; dividing the area where the group of nets to be routed belongs into a number of regular grids, and counting the number of minimum bounding rectangles covered on each regular grid to form a resource requirement matrix; determining the routing order of each interconnect network in the group of nets to be routed based on the resource requirement matrix; and routing each interconnect network in the group of nets to be routed in sequence according to the routing order. The solution of the embodiments of the present application determines the routing order of each interconnect network in the group of nets to be routed based on the resource requirement matrix, ensuring that when there is a routing resource competition among multiple interconnect networks in the group of nets to be routed, the interconnect networks with a greater congestion risk are preferentially processed, avoiding the problems of local resource preemption and repeated tearing and re-routing caused by an unreasonable routing order in the traditional method, and thus improving the routing efficiency of the 2.5D stacked chip. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a schematic diagram of the application scenario of the wiring method for a 2.5D stacked chip provided by the embodiments of the present application.

[0019] Figure 2 is a schematic flowchart of the wiring method for a 2.5D stacked chip provided by the embodiments of the present application.

[0020] Figure 3 is a schematic structural diagram of the wiring device for a 2.5D stacked chip provided by the embodiments of the present application.

[0021] Figure 4 is a schematic structural diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0022] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0023] It should be noted that, in this document, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0024] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0025] In subsequent descriptions, suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of description of the present application and have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0026] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0027] In a 2.5D stacked chip, the interconnection network between dielets needs to be routed on the same interposer (such as a silicon interposer). Due to the physical concentration and interconnection density of communication between dies, the wiring resource requirements in some areas are significantly higher than those in other areas, resulting in local congestion.

[0028] Currently, two strategies, global routing or detailed routing, are usually adopted. However, whether it is global routing or detailed routing, trial routing is generally used. It is easy for the interconnected networks that are routed first to occupy key routing resources, and the interconnected networks that are routed later need to be repeatedly torn up and re-routed due to insufficient routing resources, resulting in low routing efficiency.

[0029] Based on this, the embodiments of the present application provide a routing method, device, storage medium and electronic device for a 2.5D stacked chip. Specifically, the routing device for the 2.5D stacked chip can be integrated in an electronic device, and the electronic device can be a server or a terminal device, etc.; among them, the terminal can include a mobile phone, a wearable intelligent device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0030] For example, as Figure 1 shown, the electronic device can first obtain the minimum bounding rectangle of each interconnected network on the chip; then construct an R-Tree data structure based on the minimum bounding rectangle; then perform a merging process on the nodes of the R-Tree data structure to form a group of networks to be routed; then divide the area to which the group of networks to be routed belongs into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; finally, determine the routing order of each interconnected network in the group of networks to be routed based on the resource demand matrix; and route each interconnected network in the group of networks to be routed in sequence according to the routing order.

[0031] By determining the routing order of each interconnected network in the group of networks to be routed based on the resource demand matrix, the electronic device ensures that when there is routing resource competition among multiple interconnected networks in the group of networks to be routed, the interconnected networks with a greater congestion risk are preferentially processed, avoiding the problems of local resource preemption and repeated tearing up and re-routing caused by unreasonable routing order in the traditional method, and thus improving the routing efficiency of the 2.5D stacked chip.

[0032] The following will specifically describe the technical solutions shown in the present application through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0033] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the routing method for a 2.5D stacked chip provided by the embodiments of the present application. The specific process of the routing method for the 2.5D stacked chip can be as follows: 101. Obtain the minimum bounding rectangle of each interconnected network on the chip.

[0034] For each interconnect network on the chip, a minimum bounding rectangle can be calculated based on the coordinates of its start and end points. This minimum bounding rectangle can cover the routing path of the interconnect network and is the smallest rectangle that can cover the routing path of the interconnect network. That is, this minimum bounding rectangle can represent the resource area occupied by the interconnect network during routing.

[0035] For example, for each interconnect network, assume the start point coordinates are (x 1 , y 1 ), and the end point coordinates are (x 2 , y 2 ). Then, the four sides of the minimum bounding rectangle can be obtained according to min(x 1 , x 2 ), max(x 1 , x 2 ), min(y 1 , y 2 ), and max(y 1 , y 2 ). Specifically, the coordinates of the four vertices of this minimum bounding rectangle are as follows: The coordinates of the bottom-left vertex are: (min(x 1 , x 2 ), min(y 1 , y 2 )); The coordinates of the top-left vertex are: (min(x 1 , x 2 ), max(y 1 , y 2 )); The coordinates of the top-right vertex are: (max(x 1 , x 2 ), max(y 1 , y 2 )); The coordinates of the bottom-right vertex are: (max(x 1 , x 2 ), min(y 1 , y 2 )).

[0036] Based on the coordinates of the above four vertices, the four sides of the minimum bounding rectangle can be obtained, and thus the minimum bounding rectangle can be obtained.

[0037] 102. Construct an R-Tree data structure based on the minimum bounding rectangle.

[0038] Specifically, leaf nodes can be constructed based on the spatial position, overlap, and inclusion relationship of the minimum bounding rectangles. Each leaf node can contain one or more minimum bounding rectangles.

[0039] Among them, the spatial position refers to the two-dimensional coordinate area determined by the minimum bounding rectangle of the interconnection network in the chip plane coordinate system, which is used to represent the wiring coverage area of the interconnection network on the chip. Overlap refers to the intersection relationship between the areas covered by two or more minimum bounding rectangles on the chip plane, which is used to measure the sharing degree of wiring resources by different interconnection networks. The inclusion relationship means that one minimum bounding rectangle completely surrounds another minimum bounding rectangle geometrically.

[0040] Specifically, if two minimum bounding rectangles do not intersect: it means that the spatial positions of the interconnection networks where the two minimum bounding rectangles are located are separated from each other, and the two minimum bounding rectangles can be added to the upper layer as two leaf nodes respectively; if there is an intersection (overlap) between two minimum bounding rectangles: it indicates that wiring resources may conflict and should be grouped into the same leaf node as much as possible; if one minimum bounding rectangle completely contains another minimum bounding rectangle: it means that there is an obvious inclusion relationship between the two minimum bounding rectangles, and the two minimum bounding rectangles should be grouped into the same leaf node.

[0041] For example, starting from the minimum bounding rectangle, leaf nodes can be constructed according to the following logic: several minimum bounding rectangles with adjacent spatial positions (spacing less than the threshold) or having an overlap / inclusion relationship are merged into one leaf node.

[0042] During the construction of leaf nodes, when the number of minimum bounding rectangles in a certain leaf node exceeds the first preset capacity, a splitting strategy is triggered. The splitting operation redistributes all the minimum bounding rectangles in the original leaf node to two new leaf nodes. When the original leaf node splits into two new leaf nodes, a minimum non-leaf node is created as the parent node of the two new leaf nodes to mount these two new leaf nodes.

[0043] It can be understood that the boundary rectangle of each leaf node should be the minimum common coverage area of all the minimum bounding rectangles it includes.

[0044] Similarly, when the number of leaf nodes in a certain minimum non-leaf node exceeds the second preset capacity, a splitting strategy is triggered. The splitting operation redistributes all the leaf nodes in the original minimum non-leaf node to two new minimum non-leaf nodes. When the original minimum non-leaf node splits into two new minimum non-leaf nodes, a higher-level non-leaf node is created as the parent node of the two new minimum non-leaf nodes to mount these two new minimum non-leaf nodes.

[0045] The construction process of the R-Tree data structure is a recursive upward process starting from the minimum bounding rectangle until the root node.

[0046] It can be understood that the minimum non-leaf node is the parent node directly mounting the leaf nodes.

[0047] 103. Merge the nodes of the R-Tree data structure to form a group of nets to be routed.

[0048] Specifically, the first network direction of each leaf node in the R-Tree data structure can be obtained; based on the first network direction, the leaf nodes of each minimum non-leaf node in the R-Tree data structure are sequentially merged to form a group of nets to be routed.

[0049] Specifically, a target non-leaf node is randomly determined from multiple minimum non-leaf nodes in the R-Tree data structure; it is judged whether multiple leaf nodes in the target non-leaf node meet the merging conditions according to the first network direction.

[0050] If all leaf nodes in the target non-leaf node meet the merging conditions, then delete the target non-leaf node, and merge all leaf nodes in the target non-leaf node into a new leaf node. If some leaf nodes in the target non-leaf node meet the merging conditions, then merge the part of leaf nodes that meet the merging conditions into a new leaf node, mark the target non-leaf node as processed, and retain the unmerged leaf nodes. Then, the step of randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure can be returned to execute until all minimum non-leaf nodes are processed, a new R-Tree data structure is generated, and each leaf node in the new R-Tree data structure is used as a group of nets to be routed.

[0051] It should be noted that each time a target non-leaf node is randomly determined from multiple minimum non-leaf nodes in the R-Tree data structure, the target non-leaf node is randomly determined from the currently unprocessed minimum non-leaf nodes. The minimum non-leaf nodes marked as processed no longer participate in the iterative process. It can be understood that the termination condition of the iteration is that all minimum non-leaf nodes are processed, and at this time all leaf nodes do not meet the merging conditions.

[0052] Among them, the merging condition means that the first network directions are the same and the proximity condition is met. The proximity condition means that the gap between the bounding rectangles of two leaf nodes is less than or equal to the gap threshold (such as ≤2μm), and the overlapping ratio of the gap region and the region where the minimum bounding rectangle of other leaf nodes is located is less than or equal to the overlapping threshold.

[0053] This gap threshold can prevent the missed merging opportunity due to an extremely small gap, enhancing the grouping coherence; meanwhile, it can avoid the unnecessary group expansion caused by the merging of an overly large gap, improving the local consistency of routing. This overlap threshold can ensure that the newly generated leaf nodes after merging will not "occupy" too much third-party network resources, and at the same time limit the excessive coverage of the minimum bounding rectangles of other leaf nodes at the gap, avoiding the emergence of new high-congestion points after merging.

[0054] For each interconnected network, a vector can be formed by its starting point and ending point. By calculating the cosine value of this vector and a reference direction (horizontal, vertical, or diagonal), the direction of each interconnected network can be quantified into one of the three reference directions (horizontal, vertical, or diagonal). Specifically, the cosine values of the vector and the three reference directions can be calculated respectively, and then the reference direction with the largest obtained cosine value can be used as the third direction of this interconnected network.

[0055] For each leaf node, the second network directions of the interconnected networks it includes can be statistically analyzed. If the proportion of the number of interconnected networks with a certain second network direction f1 in this leaf node exceeds the threshold t, then the second network direction f1 can be used as the first network direction of this leaf node.

[0056] That is to say, the step of "obtaining the direction of each leaf node in the R-Tree data structure" can be: obtaining the second network directions of the interconnected networks of each leaf node in the R-Tree data structure; determining the first direction of each leaf node according to the third direction; determining the first network direction of each non-leaf node according to the second network direction.

[0057] 104. Divide the area where the to-be-routed group is located into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix.

[0058] For each to-be-routed group, the area where the to-be-routed group is located can be divided into several regular grids according to the physical routing resource (Track) information occupied by the interconnected networks in the to-be-routed group within the area.

[0059] Specifically, the y coordinates (vertical coordinates) of all horizontal Tracks and the x coordinates (horizontal coordinates) of all vertical Tracks can be extracted by using the Track list defined in the physical design tool or design rule library; then, taking these Track positions as grid lines, the area where the to-be-routed group is located is divided into several "Track units" (regular grids), and each "Track unit" exactly corresponds to the rectangular area between one horizontal Track and one vertical Track.

[0060] Finally, map the minimum bounding rectangles of each interconnected network onto a regular grid, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix.

[0061] It can be understood that the value of each regular grid in the resource demand matrix represents the wiring resource demand value occupied at the position of the regular grid. As the minimum bounding rectangles of multiple interconnected networks overlap, the value of the corresponding regular grid will increase accordingly, thereby reflecting the tightness of the wiring resources in the area corresponding to the regular grid.

[0062] 105. Determine the wiring order of each interconnected network in the to-be-wired group based on the resource demand matrix.

[0063] First, gradient analysis can be performed on the resource demand matrix to obtain a critical region; then, move the interconnected networks in the critical region from the to-be-wired group to the wiring order list; after that, update the resource demand matrix and return to execute the step of "performing gradient analysis on the resource demand matrix to obtain a critical region" until all the interconnected networks in the to-be-wired group are moved to the wiring order list, so as to obtain the wiring order of each interconnected network in the to-be-wired group.

[0064] Among them, the critical region refers to the region with the highest current congestion risk in the region to which the to-be-wired group belongs. The order of moving to the wiring order list is the wiring order of each interconnected network in the to-be-wired group.

[0065] In some embodiments, the Sobel operator can be used to calculate the first gradient in the horizontal (x) direction and the second gradient in the vertical (y) direction of the resource demand matrix respectively; then determine the critical region based on the first gradient and the second gradient.

[0066] Specifically, the horizontal kernel Sobel_x of the Sobel operator can be applied to perform convolution operation on the resource demand matrix in the horizontal direction to obtain the first gradient. The vertical kernel Sobel_y of the Sobel operator can be applied to perform convolution operation on the resource demand matrix in the vertical direction to obtain the second gradient.

[0067] It can be understood that in the region where both the first gradient and the second gradient are zero, it indicates that the resource demand change in this region is small, and it may form a maximum region, a minimum region or a saddle point region. And the critical region refers to the region with the highest current congestion risk (i.e., the maximum region).

[0068] Therefore, in this embodiment, it is necessary to first determine the candidate regions where both the first gradient and the second gradient are zero, and then determine the maximum region from the candidate regions.

[0069] In some embodiments, the boundaries of the candidate region may be traversed, and for each edge point, the resource requirement values ​​of its adjacent non-zero points (possibly a group) may be obtained. If the resource requirement value of the edge point is greater than or equal to the resource requirement values ​​of all adjacent non-zero points, the candidate region may be determined to be a maximum value region (key region).

[0070] That is, the step of "determining the key area based on the first gradient and the second gradient" can be: determining a candidate area where the first gradient and the second gradient are both zero, and identifying the edge points of the candidate area; obtaining the resource requirement value of the edge point in the resource requirement matrix and the resource requirement value of its adjacent non-zero gradient point; comparing the resource requirement value of the edge point with the resource requirement value of the adjacent non-zero gradient point, and determining the key area based on the comparison result.

[0071] It is understandable that since the routing of the interconnected networks that determine the routing order will occupy certain resources, its subsequent impact on other interconnected networks needs to be considered. Therefore, after moving an interconnected network in the group to be routed to the routing order list, the resource requirement value of the area to which the group to be routed belongs can be updated (i.e., updating the resource requirement matrix), which is helpful for the subsequent re-evaluation of the conflict risk of other interconnected networks. After that, the resource requirement matrix can be re-analyzed by gradient to obtain the key area, so as to re-evaluate the routing priority of the remaining interconnected networks.

[0072] In some embodiments, when there are more than one interconnect networks in the critical area, the interconnect network with the largest resource requirement value can be determined as the target network based on the resource requirement values ​​of each interconnect network in the critical area, and the target network can be moved from the to-be-wired group to the wiring order list.

[0073] In some embodiments, when there are more than one interconnection networks with the largest resource demand value, an interconnection network with a longer path physical length may be used as a target network.

[0074] 106. Routing each interconnection network in the wiring group in turn according to the wiring order.

[0075] Specifically, the starting point coordinates and the end point coordinates of the target interconnect network can be obtained based on the wiring sequence; the path search algorithm is executed in the area to which it belongs to plan the wiring path; if the planned wiring path is available, the wiring path is locked and wiring is performed, and the wiring resource requirements are updated; the process is repeated until all the interconnect networks in the group to be wired are wired.

[0076] In some embodiments, under the condition that the path search is completed and the routing path is confirmed to be available, each routing resource unit (such as grid lines, routing tracks, metal layer channels) on the routing path can be marked as occupied by the target interconnect network; if the routing path spans multiple routing layers, VIA (vias) are inserted at the interlayer junctions to achieve cross-layer connection; network endpoints are created at both ends of the routing path to form a complete physical connection relationship; the physical location information of the routing path is recorded in the layout for subsequent timing simulation, electrical verification, and layout convergence.

[0077] That is, after locking the routing path, the lines can be sequentially routed on the chip layout based on the locked routing path; if the routing path includes multiple routing layers, VIA are inserted at the interlayer transfer positions of the routing path to achieve cross-layer connection; the start point and end point of the routing path are physically connected to the corresponding logic units to complete the layout of the interconnect network.

[0078] It can be understood that the target interconnect network is the interconnect network with the optimal current routing order. In some embodiments, the path search algorithm can be a heuristic A* pathfinding algorithm, a maze routing algorithm, or other pathfinding algorithms based on cost function optimization.

[0079] In summary, the routing method for 2.5D stacked chips provided by the embodiments of the present application includes: obtaining the minimum bounding rectangles of each interconnect network on the chip; constructing an R-Tree data structure based on the minimum bounding rectangles; performing a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed; dividing the area where the group of nets to be routed belongs into several regular grids, and counting the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; determining the routing order of each interconnect network in the group of nets to be routed based on the resource demand matrix; and routing each interconnect network in the group of nets to be routed in sequence according to the routing order. The present application realizes hierarchical, graded, and orderly control of the routing process by introducing the R-Tree data structure, grouping by combining the direction analysis of the interconnect network, calculating the resource demand change trend using the Sobel gradient, and preferentially determining the routing order based on the gradient maximum area. It can effectively avoid routing failures and re-routing problems caused by local resource contention, improve the routing efficiency and quality, and is particularly suitable for application scenarios with dense cross-die interconnects in 2.5D stacked chips.

[0080] To facilitate better implementation of the routing method for 2.5D stacked chips provided by the embodiments of the present application, the embodiments of the present application also provide a routing device for 2.5D stacked chips. The meanings of the terms are the same as those in the above routing method for 2.5D stacked chips, and the specific implementation details can refer to the description in the method embodiments.

[0081] Please refer to Figure 3 , Figure 3It is a schematic structural diagram of a wiring device for a 2.5D stacked chip provided by an embodiment of the present application. The wiring device for the 2.5D stacked chip may include a rectangular acquisition unit 201, a structure construction unit 202, a node merging unit 203, a matrix formation unit 204, an order determination unit 205, and a network wiring unit 206. Among them, The rectangular acquisition unit 201 is configured to acquire the minimum enclosing rectangle of each interconnect network on the chip; The structure construction unit 202 is configured to construct an R-Tree data structure based on the minimum enclosing rectangle; The node merging unit 203 is configured to perform a merging process on the nodes of the R-Tree data structure to form a group to be wired; The matrix formation unit 204 is configured to divide the area to which the group to be wired belongs into a plurality of regular grids, and count the number of minimum enclosing rectangles covered on each regular grid to form a resource demand matrix; The order determination unit 205 is configured to determine the wiring order of each interconnect network in the group to be wired based on the resource demand matrix; The network wiring unit 206 is configured to wire each interconnect network in the group to be wired in sequence according to the wiring order.

[0082] For the specific implementation manners of the above respective units, reference may be made to the embodiments of the above-mentioned wiring method for the 2.5D stacked chip, which will not be elaborated herein one by one.

[0083] In summary, the wiring device for the 2.5D stacked chip provided by the embodiment of the present application can acquire the minimum enclosing rectangle of each interconnect network on the chip through the rectangular acquisition unit 201; construct an R-Tree data structure based on the minimum enclosing rectangle by the structure construction unit 202; perform a merging process on the nodes of the R-Tree data structure by the node merging unit 203 to form a group to be wired; divide the area to which the group to be wired belongs into a plurality of regular grids by the matrix formation unit 204, and count the number of minimum enclosing rectangles covered on each regular grid to form a resource demand matrix; determine the wiring order of each interconnect network in the group to be wired based on the resource demand matrix by the order determination unit 205; and wire each interconnect network in the group to be wired in sequence according to the wiring order by the network wiring unit 206. The present application realizes hierarchical, graded, and orderly regulation of the wiring process by introducing the R-Tree data structure, grouping in combination with the analysis of the interconnect network direction, calculating the resource demand change trend using the Sobel gradient, and preferentially determining the wiring order based on the gradient maximum value area. It can effectively avoid the wiring failure and re-wiring problems caused by local resource contention, improve the wiring efficiency and quality, and is particularly suitable for application scenarios with dense cross-die interconnects in 2.5D stacked chips.

[0084] The embodiment of the present application also provides an electronic device, which may be integrated with the wiring device of the 2.5D stacked chip of the embodiment of the present application, as Figure 4 shown, which shows the structural schematic diagram of the electronic device involved in the embodiment of the present application. Specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art can understand that Figure 4 the structure of the electronic device shown in does not constitute a limitation to the electronic device, and it may include more or fewer components than shown, or combine certain components, or have different component arrangements. Among them:

[0085] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 mainly includes a program storage area and a data storage area. Among them, the program storage area can store operating storage media, application programs required for at least one function, etc.; the data storage area can store data created according to the use of the electronic device. In addition, the memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices. Correspondingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0086] Although not shown, the electronic device may also include a display unit, an input unit, a power supply, etc., which will not be elaborated here. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302 to implement various functions as follows: Obtain the minimum enclosing rectangle of each interconnection network on the chip; Construct an R-Tree data structure based on the minimum bounding rectangle; Merge the nodes of the R-Tree data structure to form a group of nets to be routed; Divide the area where the group of nets to be routed is located into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; Determine the routing order of each interconnect network in the group of nets to be routed based on the resource demand matrix; Route each interconnect network in the group of nets to be routed in sequence according to the routing order.

[0087] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0088] For this reason, an embodiment of the present application provides a storage medium, which stores multiple instructions that can be loaded by a processor to execute the steps in any one of the methods provided by the embodiments of the present application. For example, the instructions can perform the following steps: Obtain the minimum bounding rectangles of each interconnect network on the chip; Construct an R-Tree data structure based on the minimum bounding rectangle; Merge the nodes of the R-Tree data structure to form a group of nets to be routed; Divide the area where the group of nets to be routed is located into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; Determine the routing order of each interconnect network in the group of nets to be routed based on the resource demand matrix; Route each interconnect network in the group of nets to be routed in sequence according to the routing order.

[0089] For the specific implementation of each of the above operations, reference can be made to the previous embodiments, which will not be elaborated here.

[0090] Among them, the storage medium may include: Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk or optical disc, etc.

[0091] Since the instructions stored in the storage medium can execute the steps in any one of the methods provided by the embodiments of the present application, the beneficial effects achievable by any one of the methods provided by the embodiments of the present application can be achieved. For details, reference can be made to the previous embodiments, which will not be elaborated here.

[0092] The wiring method, device, storage medium and electronic device of the 2.5D stacked chip provided by the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A wiring method for 2.5D stacked chips, characterized in that: include: Obtain the minimum containing rectangle of each interconnect network on the chip; Constructing an R-Tree data structure based on the minimum containing rectangle; Merging the nodes of the R-Tree data structure to form a to-be-wired group; Dividing the area to which the to-be-wired group belongs into a number of regular grids, and counting the number of minimum containing rectangles covered on each of the regular grids to form a resource requirement matrix; Determining the wiring order of each interconnection network in the to-be-wired group based on the resource requirement matrix; Each interconnection network in the to-be-wired group is wired in sequence according to the wiring sequence.

2. The wiring method of 2.5D stacked chips according to claim 1, characterized in that: The determining of the wiring order of each interconnection network in the to-be-wired group based on the resource requirement matrix includes: Performing gradient analysis on the resource demand matrix to obtain key areas; Moving the interconnection network in the critical area from the to-be-wired group to the wiring order list; The resource requirement matrix is ​​updated, and the step of performing gradient analysis on the resource requirement matrix to obtain the critical area is returned until all interconnected networks in the group to be wired are moved to the wiring order list to obtain the wiring order of each interconnected network in the group to be wired.

3. The wiring method of 2.5D stacked chips according to claim 2, characterized in that: The resource requirement matrix is ​​subjected to gradient analysis to obtain key areas, including: Using the Sobel operator to calculate the first gradient in the horizontal direction and the second gradient in the vertical direction of the resource demand matrix respectively; The key area is determined based on the first gradient and the second gradient.

4. The wiring method of 2.5D stacked chips according to claim 3, characterized in that: The determining the key area based on the first gradient and the second gradient includes: Determine a candidate region where both the first gradient and the second gradient are zero, and identify edge points of the candidate region; Obtaining the resource requirement value of the edge point and the resource requirement values ​​of its adjacent non-zero gradient points; The resource requirement value of the edge point is compared with the resource requirement value of the adjacent non-zero gradient point, and the key area is determined according to the comparison result.

5. The wiring method of 2.5D stacked chips according to claim 1, characterized in that: The merging of the nodes of the R-Tree data structure to form a to-be-wired group includes: Obtaining a first network direction of each leaf node in the R-Tree data structure; Based on the first network direction, the leaf nodes of each minimum non-leaf node in the R-Tree data structure are merged in sequence to form a to-be-wired group.

6. The wiring method of 2.5D stacked chips according to claim 5, characterized in that: Based on the first network direction, the leaf nodes of each smallest non-leaf node in the R-Tree data structure are merged in sequence to form a to-be-wired group, including: Randomly determine the target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure; Determining whether multiple leaf nodes in the target non-leaf node meet a merging condition according to the first network direction; If all leaf nodes in the target non-leaf node meet the merging condition, the target non-leaf node is deleted, and all leaf nodes in the target non-leaf node are merged into a new leaf node; If some of the leaf nodes in the target non-leaf nodes meet the merging condition, merge some of the leaf nodes that meet the merging condition into new leaf nodes, mark the target non-leaf nodes as processed, and retain the leaf nodes that have not been merged; Return to the step of randomly determining a target non-leaf node from a plurality of minimum non-leaf nodes in the R-Tree data structure until all minimum non-leaf nodes are processed, generate a new R-Tree data structure, and use each leaf node in the new R-Tree data structure as a group to be wired.

7. The wiring method of 2.5D stacked chips according to claim 4, characterized in that: The obtaining of the first network direction of each leaf node in the R-Tree data structure includes: Obtaining a second network direction of the interconnected network of each leaf node in the R-Tree data structure; The first network direction of each leaf node is determined according to the second network direction.

8. A wiring device for 2.5D stacked chips, characterized in that: include: A rectangle acquisition unit, used to acquire the minimum containing rectangle of each interconnection network on the chip; A structure building unit, used for building an R-Tree data structure based on the minimum containing rectangle; A node merging unit, used for merging the nodes of the R-Tree data structure to form a to-be-wired group; A matrix forming unit, used for dividing the area to which the to-be-wired group belongs into a plurality of regular grids, and counting the number of minimum containing rectangles covered on each of the regular grids to form a resource requirement matrix; A sequence determination unit, used for determining the wiring sequence of each interconnection network in the to-be-wired group based on the resource requirement matrix; The network wiring unit is used to sequentially wire each of the interconnected networks in the to-be-wired group according to the wiring sequence.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the wiring method of the 2.5D stacked chip according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the wiring method of the 2.5D stacked chip as described in any one of claims 1 to 7 is implemented.

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