A trench terminal connects ground buried layer SiC JBS diode and its preparation method

Abstract

The application provides a trench terminal connection ground buried layer SiC JBS diode and a preparation method thereof. The diode comprises, from bottom to top, a cathode, a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, and an anode located on the surface of the terminal transition ring of the second epitaxial layer. The first epitaxial layer comprises, inside and close to one side of the second epitaxial layer, a ground buried layer located in a preset area and a terminal transition ring located outside the preset area. In the direction perpendicular to the plane where the substrate is located, the orthographic projection of the second epitaxial layer and the orthographic projection of the terminal transition ring do not overlap. The side of the second epitaxial layer, inside and far away from the first epitaxial layer, comprises a main junction. Since the ground buried layer accelerates the discharge of excess carriers, effectively modulates the peak electric field distribution inside the device, reduces the electric field at the epitaxial / substrate homojunction, and further reduces the collision ionization at the homojunction, the single event transient current and the transient temperature are effectively reduced, and the threshold of the device leakage degradation is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a SiC JBS diode with a trench-terminated grounding layer and its fabrication method. Background Technology

[0002] In recent years, semiconductor technology has developed rapidly, and silicon carbide (SiC), as a rapidly developing third-generation semiconductor material, has attracted widespread attention. Compared with traditional silicon (Si) materials, silicon carbide has superior physical properties. First, silicon carbide possesses a higher critical displacement energy and a lower intrinsic carrier concentration, making it more suitable for space irradiation applications. Second, silicon carbide has a much higher melting point than silicon and a thermal conductivity three times that of silicon, making it more suitable for high-temperature operations. Furthermore, silicon carbide has a critical breakdown electric field ten times that of silicon and a saturation drift velocity twice that of silicon, making it more suitable for high-voltage, high-frequency environments. In conclusion, silicon carbide power devices have broad application prospects in the aerospace field.

[0003] However, the single-event sensitivity of SiC power devices does not conform to theoretical expectations. The threshold voltage for single-event burnout of junction barrier Schottky diodes (JBS) is about 30% to 50% of the rated voltage; while SELCs can be triggered at a lower voltage, about 10% to 30% of the rated voltage. This seriously affects the application of SiC power devices.

[0004] Therefore, improving the single-event immunity of SiC power devices is a key focus and challenge in the aerospace industry. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a SiC JBS diode with a trench-terminated grounding layer and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a SiC JBS diode with a trench-terminated grounding layer, comprising:

[0007] Substrate;

[0008] A buffer layer, a first epitaxial layer, and a second epitaxial layer are sequentially located on the surface of the substrate. The first epitaxial layer includes, on the side closest to the second epitaxial layer, a ground buried layer located within a preset area and a terminal transition ring located outside the preset area. In a direction perpendicular to the plane of the substrate, the orthographic projection of the second epitaxial layer and the orthographic projection of the terminal transition ring do not overlap.

[0009] The main junction is located inside the second epitaxial layer on the side away from the first epitaxial layer;

[0010] The cathode is located on the surface of the substrate away from the buffer layer, and the anode is located on the surface of the second epitaxial layer and the terminal transition ring.

[0011] In one embodiment of the present invention, the grounding layer includes a plurality of first strip cells spaced apart along a first direction and extending along a second direction, and the main junction includes a plurality of second strip cells spaced apart along the first direction and extending along the second direction, wherein the first direction is perpendicular to the second direction.

[0012] In one embodiment of the present invention, in a direction perpendicular to the plane of the substrate, the orthographic projections of each second strip cell in the main junction and the orthographic projections of each first strip cell in the grounding layer are arranged alternately.

[0013] In one embodiment of the present invention, the substrate is an N-type substrate with a doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0014] In one embodiment of the present invention, the doping concentration of the buffer layer is 1×10⁻⁶. 18 cm -3 .

[0015] In one embodiment of the present invention, the doping concentration of the first epitaxial layer is 7 × 10⁻⁶. 15 cm -3 .

[0016] In a second aspect, the present invention also provides a method for preparing a SiC JBS diode with a trench terminal connected to a grounding buried layer, for preparing the SiC JBS diode described in the first aspect;

[0017] The method includes:

[0018] Provide a substrate;

[0019] A buffer layer and a first epitaxial layer are sequentially grown on the surface of the substrate;

[0020] Ion implantation is performed in a predetermined region of the first epitaxial layer to form a grounding buried layer in the predetermined region and a terminal transition ring outside the predetermined region;

[0021] A second epitaxial layer is grown on the surface of the first epitaxial layer, and the orthographic projection of the second epitaxial layer does not overlap with the orthographic projection of the terminal transition ring;

[0022] Ion implantation is performed on the surface of the second epitaxial layer to form a main junction;

[0023] A cathode is formed on the surface of the substrate away from the buffer layer, and an anode is formed on the surface of the second epitaxial layer and the terminal transition ring to form a SiC JBS diode with a trench terminal connected to the ground buried layer.

[0024] In one embodiment of the present invention, the step of performing ion implantation in a predetermined region of the first epitaxial layer to form a grounded buried layer in the predetermined region and forming a termination transition ring outside the predetermined region includes:

[0025] Al ions are implanted in a predetermined region of the first epitaxial layer using an ion implantation process to form a grounded buried layer comprising a plurality of first strip cells spaced apart along a first direction and extending along a second direction, and a terminal transition ring is formed outside the predetermined region; the first direction is perpendicular to the second direction.

[0026] The step of ion implantation on the surface of the second epitaxial layer to form a main junction includes:

[0027] Al ions are implanted into the surface of the second epitaxial layer using an ion implantation process to form a main junction comprising a plurality of second strip cells spaced apart along a first direction and extending along a second direction.

[0028] In one embodiment of the present invention, the step of growing a second epitaxial layer on the surface of the first epitaxial layer includes:

[0029] A second epitaxial layer is grown on the surface of the first epitaxial layer;

[0030] After depositing a silicon dioxide layer on the surface of the second epitaxial layer, photoresist is coated in a preset etching area and etched to remove the second epitaxial layer located within the terminal transition ring, forming an active region mesa and a trench structure terminal transition ring.

[0031] In one embodiment of the present invention, the step of forming a SiC JBS diode with a trench-terminated grounding connection by fabricating a cathode on the surface of the substrate away from the buffer layer and an anode on the surfaces of the second epitaxial layer and the terminal transition ring includes:

[0032] A carbon film is sputtered onto the upper surface of the device, followed by high-temperature annealing to activate ion implantation.

[0033] A silicon dioxide layer is deposited on the upper surface of the device, and photoresist is coated to form an active region pattern by photolithography, and the active region is further formed by wet etching.

[0034] Photoresist is coated on the upper surface of the device and photolithography is used to form contact hole patterns. ICP etching is used to open the contact hole area. Metal titanium and metal nickel are evaporated on the upper and lower surfaces of the device, respectively. After rapid thermal annealing, front contact and back contact are formed.

[0035] After evaporating to form a metallic Al layer on the upper surface of the device, photoresist is applied to form a metallic pattern, and then etching is used to form another metallic pattern to fabricate the anode.

[0036] A Ti / Ni / Ag layer is formed by evaporation on the lower surface of the device to fabricate the cathode.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] This invention provides a SiC JBS diode with a trench-terminated grounding layer and its fabrication method. In this SiC JBS diode, the first epitaxial layer, near the upper second epitaxial layer, includes a grounding layer within a predetermined region and a termination transition ring outside the predetermined region. In a direction perpendicular to the plane of the substrate, the orthographic projection of the second epitaxial layer and the orthographic projection of the termination transition ring do not overlap. This allows the second epitaxial layer and the termination transition ring region in the first epitaxial layer to form a mesa structure, creating a trench termination. Because the grounding layer accelerates the discharge of excess carriers, it effectively modulates the peak electric field distribution inside the device, reducing the electric field at the epitaxial / substrate homojunction, thereby decreasing collisional ionization at that location. This effectively reduces single-particle transient current and transient temperature, which is beneficial for improving the device's leakage degradation threshold.

[0039] In addition, in the above-mentioned SiC JBS, the ground buried layer is connected to the device groove terminal transition ring and then to the surface electrode without significantly affecting the device conduction characteristics, thereby achieving accelerated extraction of excess carriers.

[0040] Furthermore, compared with the traditional method of active region groove injection and connection to the ground buried layer, the present invention can reduce the process difficulty and process cost in the device fabrication process, and has high practicality.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of the SiC JBS diode with trench terminal connection to grounding buried layer provided in an embodiment of the present invention;

[0043] Figure 2 This is a top view of the SiC JBS diode with trench terminal connection to the grounding buried layer provided in an embodiment of the present invention;

[0044] Figure 3 yes Figure 2 The cross-sectional view at section line AA' in the top view shown;

[0045] Figure 4 yes Figure 2The cross-sectional view at the section line BB' in the top view shown;

[0046] Figure 5 This is a flowchart of the method for fabricating a SiC JBS diode with a trench terminal connected to a grounding buried layer, as provided in an embodiment of the present invention.

[0047] Figures 6-10 This is a schematic diagram of the process for preparing a SiC JBS diode with a trench terminal connection and grounding buried layer provided in an embodiment of the present invention. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0049] Figure 1 This is a schematic diagram of the structure of the SiC JBS diode with trench terminal connection to the grounding buried layer provided in an embodiment of the present invention. Figure 2 This is a top view of a SiC JBS diode with a trench terminal connected to a buried ground layer, as provided in an embodiment of the present invention. Figures 1-2 As shown, an embodiment of the present invention provides a SiC JBS diode with a trench-terminated grounding layer, comprising:

[0050] Substrate 1;

[0051] A buffer layer 2, a first epitaxial layer 3, and a second epitaxial layer 4 are sequentially located on the surface of substrate 1. The side of the first epitaxial layer 3 closest to the second epitaxial layer 4 includes: a ground buried layer 301 located within a preset area, and a terminal transition ring 302 located outside the preset area. In the direction perpendicular to the plane of substrate 1, the orthographic projection of the second epitaxial layer 4 and the orthographic projection of the terminal transition ring 302 do not overlap.

[0052] The main junction 401 is located inside the second epitaxial layer 4 on the side away from the first epitaxial layer 3;

[0053] The cathode 5 is located on the surface of the substrate 1 away from the buffer layer 2, and the anode 6 is located on the surface of the second epitaxial layer 4 and the terminal transition ring 302.

[0054] In this embodiment, the SiC JBS diode includes: a substrate 1 and a buffer layer 2, a first epitaxial layer 3, and a second epitaxial layer 4 sequentially located on the surface of the substrate 1. The first epitaxial layer 3, near the second epitaxial layer 4, includes a ground buried layer 301 formed by ion implantation, and the periphery of the ground buried layer 301 is a termination transition ring 302. In the direction perpendicular to the plane of the substrate 1, i.e. Figure 2 From the top-down view shown, the orthographic projection of the second epitaxial layer 4 is located within the preset area and does not overlap with the orthographic projection of the terminal transition ring 302. The area where the second epitaxial layer 4 and the terminal transition ring 302 are located is a platform structure, forming a trench terminal.

[0055] In the SiC JBS diode provided by this invention, the buried ground layer 301 accelerates the discharge of excess carriers, effectively modulates the peak electric field distribution inside the device, reduces the electric field at the homojunction of the epitaxial layer / substrate 1, and consequently reduces collisional ionization at that location, thereby effectively reducing single-particle transient current and transient temperature, which is beneficial for improving the device leakage degradation threshold. Furthermore, in the aforementioned SiC JBS diode, the buried ground layer 301 is connected to the device etching electrode without significantly affecting the device's conduction characteristics, achieving accelerated extraction of excess carriers. Moreover, compared with the traditional method of active region trench injection and connection to the buried ground layer 301, this invention can also reduce the process difficulty and cost in the device fabrication process, demonstrating high practicality.

[0056] Please continue reading Figure 2 The grounding layer 301 includes a plurality of first strip cells arranged at intervals along a first direction and extending along a second direction, and the main junction 401 includes a plurality of second strip cells arranged at intervals along a first direction and extending along a second direction, wherein the first direction is perpendicular to the second direction.

[0057] Figure 3 yes Figure 2 The cross-sectional view at section line AA' in the top view shown. Figure 4 yes Figure 2 The cross-sectional view at line BB' in the top view shown should be understood as being intended to clearly demonstrate the positional relationship between the grounding layer 301 and the main junction 401 from the top viewpoint. Figure 1 The top view shown does not indicate the anode 6 located on the top layer of the device. Figures 3-4 The cathode 5 located on the lower surface of substrate 1 and the anode 6 located on the top layer of the device are not shown. Figures 2-4 As shown, in the direction perpendicular to the plane of substrate 1, the orthographic projections of each second stripe cell in the main junction 401 and the orthographic projections of each first stripe cell in the buried ground layer 301 are arranged alternately. That is, in the direction perpendicular to the plane of substrate 1, the orthographic projection of each second stripe cell does not overlap or only partially overlaps with the orthographic projection of the adjacent first stripe cell. It should be understood that after the introduction of the buried ground layer in this embodiment, the alternating arrangement of the buried ground layer and the main junction can ensure that the device surface is shielded by P-type doping, thereby shielding the excess holes generated by single-particle incident from accumulating on the device surface and improving the device's resistance to single-particle interference.

[0058] Optionally, in this embodiment, an N-type substrate 1, such as a SiC substrate 1, is selectively used, with a thickness of 350 micrometers and a doping concentration of 5 × 10⁻⁶. 18 cm -3 Doping ions are impurity ions that can form N-type semiconductors, such as N (nitrogen) ions and P (phosphorus) ions.

[0059] Optionally, the doping concentration of buffer layer 2 is 1×10⁻⁶. 18 cm -3 The thickness is 1 micrometer, and the doping concentration of the first epitaxial layer 3 is 7 × 10⁻⁶. 15 cm -3 Typically, the thickness of buffer layer 2 is determined by the voltage rating of the device; for a 1200V device, the thickness of the first epitaxial layer 3 is 11 micrometers. Similarly, the dopant ions in buffer layer 2 and the first epitaxial layer 3 are also impurity ions that can form N-type semiconductors.

[0060] Figure 5 This is a flowchart illustrating the fabrication method of the SiC JBS diode with trench terminal connection to grounding buried layer provided in an embodiment of the present invention. Figures 6-10 This is a schematic diagram illustrating the process of fabricating a SiC JBS diode with a trench-terminated grounding layer, as provided in an embodiment of the present invention. Please refer to... Figure 1 and Figures 5-10 The present invention also provides a method for preparing a SiC JBS diode with a trench terminal connected to a grounding buried layer 301, for preparing the above-mentioned SiC JBS diode;

[0061] The method includes:

[0062] S1, Provide a substrate 1.

[0063] This embodiment selectively uses an N-type substrate 1.

[0064] S2. A buffer layer 2 and a first epitaxial layer 3 are sequentially grown on the surface of substrate 1.

[0065] S3. Ion implantation is performed in a preset region of the first epitaxial layer 3 to form a grounding buried layer 301 in the preset region and a terminal transition ring 302 outside the preset region.

[0066] Step S3, which involves ion implantation in a predetermined region of the first epitaxial layer 3 to form a ground buried layer 301 within the predetermined region and a termination transition ring 302 outside the predetermined region, includes:

[0067] Al ions are implanted in a predetermined region of the first epitaxial layer 3 using an ion implantation process to form a grounded buried layer 301 containing a plurality of first strip cells spaced apart along a first direction and extending along a second direction, and a terminal transition ring 302 is formed outside the predetermined region; the first direction is perpendicular to the second direction.

[0068] S4. A second epitaxial layer 4 is grown on the surface of the first epitaxial layer 3. In a direction perpendicular to the plane of the substrate 1, the orthographic projection of the second epitaxial layer 4 is located within a preset area.

[0069] After the step of growing the second epitaxial layer 4 on the surface of the first epitaxial layer 3, the method further includes:

[0070] After depositing a silicon dioxide layer on the surface of the second epitaxial layer 4, photoresist is coated in the preset etching area and etched to remove the second epitaxial layer 4 located within the terminal transition ring 302, forming an active region mesa.

[0071] S5. Ion implantation is performed on the surface of the second epitaxial layer 4 to form the main junction 401.

[0072] Step S5, which involves ion implantation on the surface of the second epitaxial layer 4 to form the main junction 401, includes:

[0073] Al ions are implanted into the surface of the second epitaxial layer 4 using an ion implantation process to form a main junction 401 containing a plurality of second strip cells spaced apart along a first direction and extending along a second direction.

[0074] S6. A cathode 5 is fabricated on the surface of the substrate 1 away from the buffer layer 2, and an anode 6 is fabricated on the surface of the second epitaxial layer 4 and the terminal transition ring 302 to form a SiC JBS diode with a trench terminal connected to the ground buried layer 301.

[0075] Optionally, step S6, which involves fabricating a cathode 5 on the surface of substrate 1 away from buffer layer 2 and an anode 6 on the surfaces of the second epitaxial layer 4 and the terminal transition ring 302 to form a SiC JBS diode with a trench terminal connected to the buried ground layer 301, includes:

[0076] A carbon film is sputtered onto the upper surface of the device, followed by high-temperature annealing to activate ion implantation.

[0077] A silicon dioxide layer is deposited on the upper surface of the device, and photoresist is coated to form an active region pattern by photolithography, and the active region is further formed by wet etching.

[0078] Photoresist is coated on the upper surface of the device and photolithography is used to form contact hole patterns. ICP etching is used to open the contact hole area. Metal titanium and metal nickel are evaporated on the upper and lower surfaces of the device, respectively. After rapid thermal annealing, front contact and back contact are formed.

[0079] After evaporating to form a metallic Al layer on the upper surface of the device, photoresist is applied to form a metallic pattern, and then etching is performed to form another metallic pattern, thus fabricating the anode 6.

[0080] A Ti / Ni / Ag layer is formed by evaporation on the lower surface of the device to fabricate the cathode 5.

[0081] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0082] This invention provides a SiC JBS diode with a trench-terminated grounding layer and its fabrication method. In this SiC JBS diode, the first epitaxial layer, near the upper second epitaxial layer, includes a grounding layer within a predetermined region and a termination transition ring outside the predetermined region. In a direction perpendicular to the plane of the substrate, the orthographic projection of the second epitaxial layer and the orthographic projection of the termination transition ring do not overlap. This allows the second epitaxial layer and the termination transition ring region in the first epitaxial layer to form a mesa structure, creating a trench termination. Because the grounding layer accelerates the discharge of excess carriers, it effectively modulates the peak electric field distribution inside the device, reducing the electric field at the epitaxial / substrate homojunction, thereby decreasing collisional ionization at that location. This effectively reduces single-particle transient current and transient temperature, which is beneficial for improving the device's leakage degradation threshold.

[0083] In addition, in the above-mentioned SiC JBS, the ground buried layer is connected to the device groove terminal transition ring and then to the surface electrode without significantly affecting the device conduction characteristics, thereby achieving accelerated extraction of excess carriers.

[0084] Furthermore, compared with the traditional method of active region groove injection and connection to the ground buried layer, the present invention can reduce the process difficulty and process cost in the device fabrication process, and has high practicality.

[0085] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0087] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0088] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A trench termination connected ground plane buried layer SiC JBS diode, characterized by, The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode.

2. The trench-terminated, ground-plane-buried SiC JBS diode of claim 1, wherein, The application relates to a SiC JBS diode.

3. The trench-terminated, ground-plane-connected SiC JBS diode of claim 2, wherein, The application relates to a SiC JBS diode.

4. The trench-terminated, ground-plane-buried SiC JBS diode of claim 1, wherein, The substrate is an N-type substrate with a doping concentration of 5 x 1018cm-3. 18 cm -3 -3.

5. The trench-terminated, ground-plane-buried SiC JBS diode of claim 1, wherein, The doping concentration of the buffer layer is 1 x 10 18 cm -3 .

6. The trench-terminated, ground-plane-buried SiC JBS diode of claim 1, wherein, The first epitaxial layer has a doping concentration of 7x1018cm-3 15 cm -3 .

7. A method of fabricating a trench-terminated, grounded-buried-layer SiC JBS diode, characterized by, The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode.

8. The method of fabricating a trench-terminated ground-plane-buried SiC JBS diode according to claim 7, wherein, The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode. The application relates to a SiC JBS diode.

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The method of fabricating a trench-terminated, grounded-buried-layer SiC JBS diode of claim 7, wherein, The step of manufacturing the SiC JBS diode with trench termination and ground buried layer includes: Sputtering carbon film on the upper surface of the device, and performing high-temperature annealing to activate ion implantation; Depositing a silicon dioxide layer on the upper surface of the device, and coating photoresist to form active region patterns by photolithography, and further forming active regions by wet etching; Coating photoresist on the upper surface of the device and forming contact hole patterns by photolithography, opening the contact hole region by ICP etching, evaporating metal titanium and metal nickel on the upper and lower surfaces of the device respectively, and forming front and back contacts after rapid thermal annealing; After evaporating metal Al layer on the upper surface of the device, photoresist is coated to form metal patterns, and the metal patterns are etched to obtain an anode; Evaporating Ti / Ni / Ag layer on the lower surface of the device to obtain a cathode.

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