Fin type drift region LDMOS (Laterally Diffused Metal Oxide Semiconductor) with full-surrounding electron accumulation layer

Abstract

The invention discloses a silicon-on-insulator lateral double-diffused transistor power device (SOI LDMOS) with a fin-shaped drift region. The device comprises a substrate region, a channel region, a drift region, a buried oxide layer structure, a gate structure, a control electrode structure and a self-adaptive potential modulation region. The gate structure belongs to a trench gate and is used for channel adjustment of a drift region; the self-adaptive modulation region is located on the surface of the drift region and surrounds the drift region under the combined action of the self-adaptive modulation region and the buried oxide layer structure; the control electrode structure is located on the surface of the self-adaptive modulation region, control voltage is applied to the control electrode and extends to the whole self-adaptive modulation region, meanwhile, the voltage of the drift region is close to 0V, and therefore an electron accumulation layer is formed around the whole drift region, and an ultralow resistance channel is provided for conduction of the LDMOS. According to the invention, the specific on-resistance is greatly reduced, and the high breakdown voltage can be maintained at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductors, and mainly relates to a SOI LDMOS for reducing on-resistance. By adopting an electron accumulation technology, a unique device structure is designed, and an extremely low specific on-resistance is obtained, thereby reducing the on-state loss of power devices and promising to have a broad application space in the field of power electronics. Technical Background

[0002] Insulated Gate Bipolar Transistor (IGBT) devices are widely used in high-voltage power integrated circuits and intelligent power integrated circuits due to their advantages such as high breakdown voltage, fast switching speed, high power, and good compatibility with CMOS processes. However, compared with bipolar power transistors, IGBTs mainly rely on a unipolar MOS structure to conduct current, and their current density is relatively low, which limits their performance in high-current applications, increases the on-state loss, and reduces the system efficiency. The key to the design of power devices is to achieve high breakdown voltage and low power consumption. Therefore, for the design of high-voltage power device structures, the two most important performance indicators are the breakdown voltage BV and the specific on-resistance R on,sp . The lateral power device IGBT is the core device of the power integrated circuit, often occupying a large chip area, and is the mainstream choice in the high-voltage BCD platform. However, there is a traditional "silicon limit" constraint relationship of the 2.5th power between its breakdown voltage and the specific on-resistance. Breaking the "silicon limit" constraint relationship, alleviating the contradictory relationship between the breakdown voltage and the specific on-resistance, and reducing the specific on-resistance while increasing the device breakdown voltage have become important issues to be considered in the design of lateral power devices. FOM (Figure of Merit) is an index used to comprehensively evaluate the performance of devices. The higher the FOM value, the better the balance achieved by the device in the two mutually restrictive performances of high breakdown voltage and low on-resistance.

[0003] With the country's proposal of the concept of energy conservation, environmental protection, and the development of green energy, improving the energy efficiency of devices has become an extremely important topic. Therefore, studying new IGBT devices with low specific on-resistance R on,sp without reducing the device breakdown voltage BV is of great significance for social development. Summary of the Invention

[0004] The object of the present invention is to propose a uniquely designed LDMOS device structure, which forms a surrounding electron accumulation layer around the drift region to provide an ultra-wide low-resistance channel for device conduction. Therefore, while maintaining the same breakdown voltage as the traditional LDMOS, an extremely low specific on-resistance is achieved to reduce the on-state power consumption of the device. Thus, a larger FOM value (square of the breakdown voltage / specific on-resistance) can be obtained.

[0005] In order to achieve the above object of the invention, the technical solution of the present invention is as follows:

[0006] An SOI LDMOS structure with a fully surrounding electron accumulation layer in the drift region, comprising:

[0007] Substrate region: a P-type semiconductor substrate 1, with a substrate electrode connected below it and a buried oxide layer 2 above it;

[0008] Source region: composed of a P-type heavily doped region 3, jointly connected to an electrode 14 with an N-type heavily doped region 4 as the source;

[0009] P-type body region 5: internally provided with a gate oxide layer 8 and a vertical trench gate electrode 15;

[0010] Drift region: a drift region 6 of N-type lightly doped region;

[0011] First drain region: a first N-type heavily doped drain region 7, with a drain electrode 17 connected above it;

[0012] Adaptive potential modulation region: an adaptive potential region 10 containing N-type lightly doped polysilicon and an insulating dielectric layer structure 9, the insulating dielectric layer structure 9 is located between the adaptive potential region 10 and the drift region 6, separating the two; Control region: a P-type lightly doped control region 11 is located on the surface of the adaptive potential region 10, with a control electrode 16 connected above it;

[0013] Second drain region: comprising a second N-type heavily doped drain region 12 and a P-type doped drain region 13, with a drain electrode 17 connected above the P-type doped region 13;

[0014] The surface of the drift region 6 is surrounded by the insulating dielectric layer structure 9, and the insulating dielectric layer structure 9 and the buried oxide layer 2 jointly surround the drift region 6 inside.

[0015] The bottom boundary of the drift region 6 is flush with the top boundary of the buried oxide layer 2, and the surface boundary of the drift region 6 is flush with the inner boundary of the insulating dielectric layer structure 9.

[0016] The adaptive potential region 10 is formed on the outer surface of the insulating dielectric layer structure 9, and the insulating dielectric layer structure 9 isolates the adaptive potential region 10 from the drift region 6.

[0017] The adaptive potential region 10 is a polysilicon structure with lightly doped N-type. A control electrode 16 and a drain electrode 17 are arranged on its surface. A P-type lightly doped control region 11 is arranged below the control electrode 16; a second drain region is arranged below the drain electrode 17, and the second drain region includes a second N-type heavily doped drain region 12 and a P-type doped drain region 13.

[0018] The P-type doped drain region 13 is arranged on the surface of the second N-type heavily doped drain region 12, and the drain electrode 17 is arranged on the surface of the P-type doped drain region 13.

[0019] The optimization effect of the present invention is that: since an electron accumulation layer with full surround in the drift region is introduced, the device can have an ultra-wide conductive channel with low resistance. In addition, the control electrode can skillfully adjust the accumulation intensity of the electron accumulation effect and achieve the best accumulation effect. It can be seen from the simulation results that the present invention realizes an extremely low specific on-resistance Ron,sp, only 0.28 mΩ·cm 2 , compared with the specific on-resistance of 12.56 mΩ·cm 2 of the traditional LDMOS, under the condition that the breakdown voltage BV of both is 258V, it is reduced by 97.7%. Therefore, a record high FOM value is obtained, reaching 237.7 MW / cm 2 . Brief Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is the SOI LDMOS structure (a) with an electron accumulation layer with full surround in the drift region proposed by the present invention and its cross-sectional view (b) along the A-A' direction.

[0022] Figure 2 It is a traditional trench-gate SOI LDMOS.

[0023] Figure 3 It is the potential distribution diagram of (a) the structure of the present invention and (b) the traditional structure when the device is in the on state, and the potential distribution diagrams of the two structures on the surface of the drift region.

[0024] Figure 4 It is Figure 3 the potential distribution curve diagrams of the two structures inside.

[0025] Figure 5 It is the structure R of the present invention ON,spThe graph showing the variation of [device] with BV under different control voltages with respect to the drift region width, and a comparison with a traditional LDMOS.

[0026] Figure 6 The graph showing the variation of the FOM of the present invention under different control voltages with respect to the drift region width, and a comparison with a traditional LDMOS. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some of the embodiments of this application, rather than all the embodiments. Usually, the components of the embodiments of this application described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts shall fall within the scope of protection of this application.

[0028] Aiming at the problem of large on-resistance caused by lightly doped drift region, the present invention provides an ultra-low resistance channel for the drift region conduction by introducing a method of forming a drift region surrounded by an electron accumulation layer, thereby reducing the specific on-resistance. Figure 1 Figure (a) shows the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region proposed by the present invention. It includes:

[0029] Substrate region: A P-type semiconductor substrate 1 with a substrate electrode connected below and a buried oxide layer 2 above;

[0030] Source region: Composed of a P-type heavily doped region 3, jointly connected to an electrode 14 with an N-type heavily doped region 4 as the source;

[0031] P-type body region 5: Inside which a gate oxide layer 8 and a vertical trench gate electrode 15 are provided;

[0032] Drift region: The drift region 6 which is an N-type lightly doped region;

[0033] First drain region: The first N-type heavily doped drain region 7 with a drain electrode 17 connected above;

[0034] Adaptive potential modulation region: An adaptive potential region 10 containing N-type lightly doped polysilicon and an insulating dielectric layer structure 9. The insulating dielectric layer structure 9 is located between the adaptive potential region 10 and the drift region 6, separating the two; Control region: The P-type lightly doped control region 11 is located on the surface of the adaptive potential region 10, with a control electrode 16 connected above;

[0035] Second drain region: It includes a second N-type heavily doped drain region 12 and a P-type doped drain region 13, and a drain electrode 17 is connected above the P-type doped region 13;

[0036] Embodiment 1

[0037] Figure 1 (b) shows a cross-sectional view of the SOI LDMOS structure with a drift region fully surrounded by an electron accumulation layer along Figure 1 the A-A' direction in (a).

[0038] The insulating dielectric layer 9 and the buried oxide layer 2 work together to surround the drift region 6. The outer surface of the drift region 6 is fully attached to the inner surface of the insulating dielectric layer 9 and partially attached to the upper surface of the buried oxide layer 2. The inner surface of the adaptive potential region 10 is fully attached to the outer surface of the insulating dielectric layer 9. The bottom surfaces of the adaptive potential region 10, the insulating dielectric layer 9, and the drift region 6 are all on the same horizontal line as the upper surface of the buried oxide layer 2.

[0039] Embodiment 2

[0040] Figure 2 is a traditional trench-gate SOI LDMOS

[0041] The difference between the present invention and Figure 2 the traditional trench-gate SOI LDMOS shown lies in the structural design of the drift region. The new structure proposed by the present invention includes: an insulating dielectric layer 9, an adaptive potential region 10, a P-type lightly doped control region 11, a control electrode 16, a second N-type heavily doped drain region 12, a P-type doped drain region 13, and a drain electrode 17 provided on the surface of the P-type doped drain region 13.

[0042] The P-type lightly doped control region 11 and the control electrode 16 in the control region are both provided on the top layer of the adaptive potential region 10, and the second N-type heavily doped drain region 12 and the P-type doped drain region 13 in the second drain region are both provided on the top layer of the adaptive potential region 10. The control region and the second drain region are located at the leftmost and rightmost ends of the top layer of the adaptive potential region 10 respectively, aiming to achieve a higher breakdown voltage.

[0043] Embodiment 3

[0044] Figure 3The potential distribution diagrams of the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region proposed by the present invention (a) and the traditional SOI LDMOS (b) when the device is turned on. The results show that: the drift region 6 of the structure of the present invention always maintains a low potential close to 0V, while the overall adaptive potential region 10 maintains a high potential close to the voltage of the control electrode 16. Therefore, a potential difference equal to the control voltage is formed between the drift region 6 and the adaptive potential region 10. In addition, a part of the high potential in the adaptive potential region 10 extends to the buried oxide layer 2, finally introducing a fully surrounded electron accumulation layer in the drift region. At this time, the drift region of the traditional SOI LDMOS still maintains a low potential close to 0V.

[0045] Example 4

[0046] Figure 4 The potential distribution diagram of the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region proposed by the present invention at different voltages of the control electrode 16. The results show that when the voltage of the control electrode 16 changes, the potential of the adaptive potential region 10 also changes accordingly, while the potential of the drift region 6 always remains at a low level.

[0047] Example 5

[0048] Figure 5 For the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region proposed by the present invention ON,sp The diagram of the variation law of R and BV of the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region proposed by the present invention with the change of the drift region width at different control voltages, and a comparison with the traditional LDMOS. The results show that: since the narrower the width of the drift region 6, the smaller the proportion of the area of the low-doped region with a higher resistance, which makes the specific on-resistance related to the device surface area decrease accordingly. Since a higher voltage of the control electrode 16 brings a stronger electron accumulation effect, the on-resistance in the drift region 6 decreases, thus the specific on-resistance decreases. Therefore, an extremely low R is achieved ON,sp , reaching 0.27 mΩ·cm 2 . At this time, the drift region 6 of the traditional SOI LDMOS is a low-doped region with a higher resistance, so R ON,sp is 12.56 mΩ·cm 2 , which is much larger than the R of the structure of the present invention ON,sp . In addition, since the breakdown voltage of the LDMOS device is mainly related to the lateral breakdown voltage and the vertical breakdown voltage, the change of the width of the drift region has almost no effect on the breakdown voltage of the device.

[0049] Example 6

[0050] Figure 6The figure shows the variation law of the FOM of the SOI LDMOS structure with a fully surrounded electron accumulation layer in the drift region of the present invention with respect to the width of the drift region 6 under different control voltages, and a comparison is made with the traditional SOI LDMOS. The results show that: Due to Figure 5 As shown, the R of the structure of the present invention ON,sp is much smaller than that of the traditional LDMOS, while the breakdown voltage BV hardly changes. Therefore, the FOM of the structure of the present invention reaches an extremely high 237.7 MW / cm 2 , far exceeding 5.5 MW / cm of the traditional SOI LDMOS 2 . It shows that the present invention achieves a better balance in two mutually restrictive performances of high breakdown voltage and low on-resistance.

Claims

1. A SOILDMOS structure having an electron accumulation layer surrounding the drift region, characterized in that: It includes: substrate region: a P-type semiconductor substrate 1, with a substrate electrode connected below and a buried oxide layer 2 above; Source region: composed of a P-type heavily doped region 3, and connected to an electrode 14 together with an N-type heavily doped region 4, serving as a source; P-type body region 5: a gate oxide layer 8 and a vertical trench gate electrode 15 are arranged inside; Drift region: drift region 6 which is an N-type lightly doped region; First drain region: a first N-type heavily doped drain region 7, with a drain electrode 17 connected thereto; Adaptive potential modulation region: comprising an adaptive potential region 10 of N-type lightly doped polysilicon and an insulating dielectric layer structure 9, wherein the insulating dielectric layer structure 9 is located between the adaptive potential region 10 and the drift region 6 to separate the two; Control region: a P-type lightly doped control region 11 is located on the surface of the adaptive potential region 10, and a control electrode 16 is connected thereto; The second drain region includes a second N-type heavily doped drain region 12 and a P-type doped drain region 13, and a drain electrode 17 is connected above the P-type doped region 13; The direction from source to drain is Z, the direction from the surface to the inside of the device is Y, and the X direction is perpendicular to the ZOY plane.

2. The SOI LDMOS structure having an electron accumulation layer fully surrounding the drift region according to claim 1, characterized in that: The surface of the drift region 6 is surrounded by an insulating dielectric layer structure 9 , and the insulating dielectric layer structure 9 and the buried oxide layer 2 together surround the drift region 6 .

3. The SOI LDMOS structure having an electron accumulation layer fully surrounding the drift region according to claim 1, characterized in that: The bottom boundary of the drift region 6 is flush with the top boundary of the buried oxide layer 2 , and the surface boundary of the drift region 6 is flush with the inner boundary of the insulating dielectric layer structure 9 .

4. The SOI LDMOS structure having an electron accumulation layer fully surrounding the drift region according to claim 1, characterized in that: The adaptive potential region 10 is formed on the outer surface of the insulating dielectric layer structure 9 , and the insulating dielectric layer structure 9 isolates the adaptive potential region 10 from the drift region 6 .

5. The SOI LDMOS structure having an electron accumulation layer fully surrounding the drift region according to claim 1, characterized in that: The adaptive potential region 10 is an N-type lightly doped polysilicon structure, with a control electrode 16 and a drain electrode 17 arranged on its surface, and a P-type lightly doped control region 11 is arranged below the control electrode 16; a second drain region is arranged below the drain electrode 17, and the second drain region includes a second N-type heavily doped drain region 12 and a P-type doped drain region 13.

6. The SOIL DMOS structure having an electron accumulation layer fully surrounding the drift region according to claim 1, characterized in that: The P-type doped drain region 13 is disposed on the surface of the second N-type heavily doped drain region 12 , and the drain electrode 17 is disposed on the surface of the P-type doped drain region 13 .

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