Trench gate silicon carbide MOSFET and manufacturing method thereof

Abstract

The invention discloses a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The top surface of a second conductive type doped first buried layer formed in a first conductive type doped silicon carbide epitaxial layer is lower than the bottom surface of a gate trench; and a heterojunction polycrystalline silicon layer filled in the second groove is formed on the outer side of the first side surface of the channel region. A lateral current path is made up of the silicon carbide epitaxial layer located over the top surface of the first buried layer, and a longitudinal current path is made up of the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench and forms a current path of the heterojunction diode together with the lateral current path. A plurality of first connecting layers are formed in a partial region where the first buried layer and the channel region are overlapped, intervals are formed between the first connecting layers in the length direction of the first buried layer, and interval regions are constituent parts of a transverse current path. The invention further discloses a manufacturing method of the trench gate silicon carbide MOSFET. According to the invention, the heterojunction diode can be integrated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a trench gate silicon carbide MOSFET; this invention also relates to a method for manufacturing a trench gate silicon carbide MOSFET. Background Technology

[0002] The performance of existing traditional silicon-based semiconductor devices is gradually approaching the physical limits of the materials. Devices made using third-generation semiconductor materials, represented by silicon carbide (SiC), have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. They can achieve higher power density and higher efficiency, and have broad application prospects in the fields of high power, high temperature and high frequency power electronics.

[0003] SiC MOSFETs, as representative SiC switching devices, possess advantages such as low switching losses, high operating frequency, easy driving, and suitability for parallel operation. They are increasingly being promoted and used in applications such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC transmission. However, due to the large bandgap of silicon carbide, the body diode of SiC MOSFETs exhibits a high forward turn-on voltage drop (VON > 2.7V), increasing the device's conduction losses. Simultaneously, the injection of unbalanced minority carriers during body diode conduction, and the reverse recovery process during turn-off, also increase device losses. Furthermore, the low stacking fault energy on the basal surface of silicon carbide allows basal dislocations to split into Shockley partial dislocations under external forces, resulting in stacking faults and causing bipolar degradation, leading to device reliability issues. Therefore, when using SiC MOSFETs, a SiC Schottky diode is typically connected in reverse parallel externally. However, this introduces additional parasitic parameters and increases system manufacturing costs. Summary of the Invention

[0004] The technical problem to be solved by this invention is to provide a trench-gate silicon carbide MOSFET that can integrate a heterojunction diode, reduce the third quadrant on-state voltage drop, reduce conduction losses, and improve reliability. To this end, this invention also provides a method for manufacturing a trench-gate silicon carbide MOSFET.

[0005] To solve the above-mentioned technical problems, the trench-gate silicon carbide MOSFET provided by the present invention includes: A silicon carbide epitaxial layer doped with a first conductivity type has a drain region heavily doped with the first conductivity type formed on the back side of the silicon carbide epitaxial layer.

[0006] A trench gate includes a gate dielectric layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench.

[0007] A second conductivity type channel region is formed in the silicon carbide epitaxial layer, and the second side of the channel region, which is longitudinally penetrated through the channel region and covered by the side of the gate conductive material layer, is used to form the channel of the MOSFET.

[0008] A heavily doped source region of the first conductivity type is formed in the surface region of the channel region, and the second side of the source region is aligned with the side of the gate trench.

[0009] A first buried layer doped with a second conductivity type, the top surface of the first buried layer being lower than the bottom surface of the gate trench; a second trench is formed in the top region of the silicon carbide epitaxial layer outside the first side of the channel region, and a heterojunction polysilicon layer is filled in the second trench, the heterojunction polysilicon layer and the bottom silicon carbide epitaxial layer being in contact to form a heterojunction diode.

[0010] The first side of the first buried layer extends to the first side of the second trench or to the outside, and a lateral current path is formed by the silicon carbide epitaxial layer located above the top surface of the first buried layer. The second side of the first buried layer is located outside the side of the corresponding gate trench and a longitudinal current path is formed by the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench. The lateral current path and the longitudinal current path form the current path of the heterojunction diode.

[0011] In the overlapping region of the first buried layer and the channel region, a plurality of first interconnect layers doped with a second conductivity type are formed to connect the first buried layer to the channel region. There is a gap between each first interconnect layer along the length direction of the first buried layer. The gap between each first interconnect layer is part of the lateral current path. The length direction of the first buried layer is the same as the length direction of the gate trench.

[0012] A further improvement is that the width of each of the first connecting layers is smaller than the width of the first buried layer.

[0013] A further improvement is that a heavily doped channel contact region of a second conductivity type is formed in the surface region of the channel region, and the channel contact region is located outside the source region.

[0014] The top of the source region is connected to the source electrode, which is composed of a front metal layer, through a contact hole, and the contact hole corresponding to the top of the source region is also in contact with the channel contact region.

[0015] The heterojunction polysilicon layer is also connected to the source electrode through the corresponding contact hole at the top.

[0016] A further improvement is that the channel region, the source region, the heterojunction polysilicon layer, the first buried layer, and the first interconnect layer are formed on both sides of the gate trench and are symmetrical about the center of the gate trench.

[0017] A further improvement is that a current spreading layer doped with a first conductivity type is formed in the surface region of the silicon carbide epitaxial layer. The doping concentration of the current spreading layer is greater than that of the silicon carbide epitaxial layer and is used to reduce the specific on-resistance.

[0018] A further improvement is that the formation area of ​​the first connection layer is defined by the layout, and the on-resistance is adjusted by adjusting the area ratio of the first connection layer in the lateral current path. The smaller the area ratio of the first connection layer, the lower the on-resistance.

[0019] A further improvement is that the heterojunction polysilicon layer is P-type doped or N-type doped.

[0020] A further improvement is that the trench-gate silicon carbide MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench-gate silicon carbide MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0021] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a trench-gate silicon carbide MOSFET, comprising: A silicon carbide epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the silicon carbide epitaxial layer.

[0022] A first buried layer is formed in a selected region within the silicon carbide epitaxial layer by implanting ions of a second conductivity type.

[0023] A first interconnect layer is formed in a selected region on top of the first buried layer by second conductivity type ion implantation; there is a gap between each first interconnect layer along the length direction of the first buried layer.

[0024] A second conductivity type ion implantation is performed to form a channel region in a selected area of ​​the surface region of the silicon carbide epitaxial layer. The top surface of the first connecting layer and the bottom surface of the channel region are in contact to achieve the connection between the first buried layer and the channel region.

[0025] A source region is formed in a selected area of ​​the surface region of the channel region by implanting ions heavily doped with the first conductivity type.

[0026] A second trench is formed in the top region of the silicon carbide epitaxial layer on the outer side of the first side of the trench region by etching. Then, a heterojunction polysilicon layer is filled in the second trench. The heterojunction polysilicon layer and the bottom silicon carbide epitaxial layer are in contact to form a heterojunction diode.

[0027] Forming a trench gate includes forming a gate trench, forming a gate dielectric layer on the inner surface of the gate trench, and filling the gate trench with a gate conductive material layer; the gate trench extends longitudinally through the channel region and is covered by the side surface of the gate conductive material layer, and the second side surface of the channel region is used to form the channel of the MOSFET; the second side surface of the source region is aligned with the side surface of the gate trench; the top surface of the first buried layer is lower than the bottom surface of the gate trench, and the length direction of the first buried layer is the same as the length direction of the gate trench.

[0028] The first side of the first buried layer extends to the first side or outside of the second trench, and a lateral current path is formed by the silicon carbide epitaxial layer located above the top surface of the first buried layer, with the spacing between each of the first interconnecting layers being a component of the lateral current path; the second side of the first buried layer is located outside the side of the corresponding gate trench and a longitudinal current path is formed by the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench, and the current path of the heterojunction diode is formed by the lateral current path and the longitudinal current path.

[0029] A further improvement is that the width of each of the first connecting layers is smaller than the width of the first buried layer.

[0030] A further improvement is that, after forming the source region, the method further includes: Ions heavily doped with a second conductivity type are implanted to form a channel contact region in a selected area of ​​the surface region of the channel region, the channel contact region being located outside the source region.

[0031] Further improvements include: An interlayer film is formed, the interlayer film is etched to form contact holes, a front metal layer is formed, and the front metal layer is patterned to form the source and gate. The top of the source region is connected to the source through the corresponding contact hole, and the contact hole corresponding to the top of the source region is also in contact with the channel contact region. The heterojunction polysilicon layer is also connected to the source through the corresponding contact hole at the top.

[0032] After completing the front-side process, it also includes: A back metal layer is formed on the back side of the leak area.

[0033] A further improvement is that the channel region, the source region, the heterojunction polysilicon layer, the first buried layer, and the first interconnect layer are formed on both sides of the gate trench and are symmetrical about the center of the gate trench.

[0034] A further improvement is that a current spreading layer doped with a first conductivity type is formed in the surface region of the silicon carbide epitaxial layer. The doping concentration of the current spreading layer is greater than that of the silicon carbide epitaxial layer and is used to reduce the specific on-resistance.

[0035] A further improvement is that the formation area of ​​the first connection layer is defined by the layout, and the on-resistance is adjusted by adjusting the area ratio of the first connection layer in the lateral current path. The smaller the area ratio of the first connection layer, the lower the on-resistance.

[0036] A further improvement is that the heterojunction polysilicon layer is P-type doped or N-type doped.

[0037] A further improvement is that the trench-gate silicon carbide MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench-gate silicon carbide MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0038] The present invention provides a heterojunction polysilicon layer filled in a second trench on the outer side of the first side of the channel region, thereby forming a heterojunction diode in contact with the silicon carbide epitaxial layer. The heterojunction diode has a low barrier height, thus having the advantage of low on-state voltage drop, thereby reducing the on-state voltage drop in the third quadrant of the device.

[0039] The present invention also includes a first buried layer and a first connection layer. The first buried layer is disposed outside the gate trench and extends laterally from a position directly below the heterojunction polysilicon layer to a position near the side of the gate trench. This allows a lateral current path composed of a silicon carbide epitaxial layer to be formed on the top of the first buried layer and a longitudinal current path composed of a silicon carbide epitaxial layer to be formed between the second side of the first buried layer and the bottom of the gate trench. In this way, the first buried layer can effectively control the current path of the heterojunction diode while providing good protection for the gate dielectric layer. Furthermore, by connecting the first buried layer to the channel region and then to the source through the first connection layer, the depletion region between the first buried layer and the silicon carbide epitaxial layer can be further contracted when the device is turned on in the third quadrant, thereby facilitating current flow and reducing the conduction loss of the device when operating in the third quadrant.

[0040] The present invention can also adjust the proportion of the injection region corresponding to the first connection layer and the non-injection region outside the first connection layer through layout design. When the proportion of the non-injection region increases, that is, the proportion of the injection region decreases, the on-resistance can be further reduced.

[0041] In addition, the heterojunction diode of the present invention does not have the bipolar degradation problem, thereby improving the reliability of the device under long-term operating conditions.

[0042] Therefore, this invention can integrate heterojunction diodes, reduce the on-state voltage drop in the third quadrant of the device, reduce conduction losses, and improve reliability.

[0043] This invention does not require an external reverse parallel SiC Schottky diode, so it does not introduce additional parasitic parameters and has low manufacturing cost. Attached Figure Description

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a three-dimensional structural schematic diagram of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention; Figure 2A yes Figure 1 A cross-sectional view of the xy plane at the dashed line AA; Figure 2B yes Figure 1 A cross-sectional view of the xy plane at the dashed line BB in the middle; Figures 3A-3G This is a schematic diagram of the device structure in each step of the manufacturing method of trench gate silicon carbide MOSFET according to an embodiment of the present invention; Figure 4A This is a schematic diagram of the equivalent circuit of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention; Figure 4B This is a schematic diagram of the forward conduction current flow direction of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention; Figure 4C This is a schematic diagram of the conduction current flow direction in the third quadrant of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention. Detailed Implementation

[0045] like Figure 1 The diagram shown is a three-dimensional structural schematic of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention; as shown Figure 2A As shown, is Figure 1 A cross-sectional view of the xy plane at the point where the dashed line AA is located; as shown. Figure 2B As shown, is Figure 1 A cross-sectional view of the xy plane at the dashed line BB; the trench-gate silicon carbide MOSFET of this embodiment includes: A silicon carbide epitaxial layer 2 doped with a first conductivity type has a drain region 1 heavily doped with a first conductivity type formed on its back side. The drain region 1 is formed from a silicon carbide substrate.

[0046] A trench gate includes a gate dielectric layer 10 formed on the inner surface of a gate trench and a gate conductive material layer 11 filled in the gate trench. In this embodiment of the invention, the gate dielectric layer 10 includes a gate oxide layer; the gate conductive material layer 11 includes a polysilicon gate.

[0047] A second conductivity type channel region 61 is formed in the silicon carbide epitaxial layer 2. The second side of the channel region 61, which is longitudinally penetrated by the gate trench and covered by the side of the gate conductive material layer 11, is used to form the channel of the MOSFET.

[0048] A heavily doped source region 71 of the first conductivity type is formed in the surface region of the channel region 61, and the second side of the source region 71 is aligned with the side of the gate trench.

[0049] A first buried layer 41 doped with a second conductivity type, the top surface of the first buried layer 41 being lower than the bottom surface of the gate trench; a second trench is formed in the top region of the silicon carbide epitaxial layer 2 on the outer side of the first side of the channel region 61, and a heterojunction polysilicon layer 91 is filled in the second trench, the heterojunction polysilicon layer 91 and the bottom silicon carbide epitaxial layer 2 are in contact to form a heterojunction diode.

[0050] In this embodiment of the invention, the heterojunction polysilicon layer 91 is P-type doped or N-type doped. For N-type devices, when the heterojunction polysilicon layer 91 is N-type doped, the heterojunction barrier is lower.

[0051] The first side of the first buried layer 41 extends to the first side or outside of the second trench, and a lateral current path is formed by the silicon carbide epitaxial layer 2 located above the top surface of the first buried layer 41. The second side of the first buried layer 41 is located outside the side of the corresponding gate trench and a longitudinal current path is formed by the silicon carbide epitaxial layer 2 located between the second side of the first buried layer 41 and the bottom of the gate trench. The lateral current path and the longitudinal current path form the current path of the heterojunction diode.

[0052] In the overlapping region of the first buried layer 41 and the channel region 61, a plurality of first interconnect layers 51 doped with a second conductivity type are formed to connect the first buried layer 41 to the channel region 61. There is a gap between each first interconnect layer 51 along the length direction of the first buried layer 41, and the gap between each first interconnect layer 51 is part of the lateral current path. The length direction of the first buried layer 41 is the same as the length direction of the gate trench. Figure 2A The image shows the spacing between the first connection layers 51. Figure 2B The first connecting layer 51 is then displayed. In this embodiment of the invention, the width of each first connecting layer 51 is smaller than the width of the first buried layer 41.

[0053] In this embodiment of the invention, the formation area of ​​the first connection layer 51 is defined by the layout. In the lateral current path, the specific on-resistance is adjusted by adjusting the area ratio of the first connection layer 51. The smaller the area ratio of the first connection layer 51, the lower the specific on-resistance.

[0054] A second conductivity type heavily doped channel contact region 81 is also formed in the surface region of the channel region 61, and the channel contact region 81 is located outside the source region 71.

[0055] The top of the source region 71 is connected to the source electrode composed of the front metal layer 15 through a contact hole passing through the interlayer film 12, and the contact hole corresponding to the top of the source region 71 is also in contact with the channel contact region 81. In this embodiment of the invention, an ohmic contact region 131 is also formed at the bottom of the contact hole corresponding to the source region 71 and the channel contact region 81.

[0056] The heterojunction polysilicon layer 91 is also connected to the source electrode through a corresponding contact hole at the top. In this embodiment of the invention, an ohmic contact region 141 is also formed at the bottom of the contact hole corresponding to the heterojunction polysilicon layer 91.

[0057] A back metal layer 3 is formed on the back side of the drain region 1 and forms the drain electrode.

[0058] In this embodiment of the invention, a channel region, a source region, a channel contact region, a heterojunction polysilicon layer, a first buried layer, and a first interconnect layer are formed on both sides of the gate trench, and are symmetrical about the center of the gate trench. That is, corresponding MOSFET and heterojunction diode unit structures are formed on both the left and right sides of the gate trench. The MOSFETs on the left and right sides of the gate trench are in parallel, and the heterojunction diodes on the left and right sides are also in parallel. The above is based on... Figure 1 Taking the channel region 61, source region 71, channel contact region 81, heterojunction polysilicon layer 91, first buried layer 41, and first interconnect layer 51 located on the left side of the gate trench as an example, the following description is provided: Since the channel region, source region, channel contact region, heterojunction polysilicon layer, first buried layer, and first interconnect layer are symmetrical about the center of the gate trench, Figure 1 The structure of the channel region 62, source region 72, channel contact region 82, heterojunction polysilicon layer 92, first buried layer 42, and first interconnect layer 52 located on the right side of the gate trench, as shown in the diagram, is completely identical to the process structure of the channel region 61, source region 71, channel contact region 81, heterojunction polysilicon layer 91, first buried layer 41, and first interconnect layer 51 on the left side of the gate trench. To indicate the symmetry between the two, the numbers of each region are individually labeled. Similarly, there are also ohmic contact regions 132 and 142 symmetrical to ohmic contact region 131 on the right side of the gate trench. This application focuses on... Figure 1The following section will be introduced using the channel region 61, source region 71, channel contact region 81, heterojunction polysilicon layer 91, first buried layer 41 and first interconnect layer 51 located on the left side of the gate trench as an example.

[0059] A current-spreading layer (not shown) doped with a first conductivity type is also formed in the surface region of the silicon carbide epitaxial layer 2. The doping concentration of the current-spreading layer is greater than that of the silicon carbide epitaxial layer 2 and is used to reduce the specific on-resistance. The bottom surface of the current-spreading layer can extend below the top surface of the first buried layer 41.

[0060] In this embodiment of the invention, the trench-gate silicon carbide MOSFET is an N-type device, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the trench-gate silicon carbide MOSFET can also be a P-type device, with P-type as the first conductivity type and N-type as the second conductivity type.

[0061] like Figure 4A The diagram shown is an equivalent circuit diagram of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention. The trench-gate silicon carbide MOSFET includes the MOSFET shown in dashed box 201 and the heterojunction diode shown in dashed box 202. Therefore, the embodiment of the present invention realizes the integration of the heterojunction diode. Among them, the MOSFET in dashed box 201 also has a body diode, which is formed between the channel region 61 and the silicon carbide epitaxial layer 2.

[0062] like Figure 4B The diagram shown is a schematic diagram of the forward conduction current flow of a trench gate silicon carbide MOSFET according to an embodiment of the present invention; the forward conduction current, as shown by the dashed arrow 203, is the Ids current from the drain to the source.

[0063] Figure 4C This is a schematic diagram of the third quadrant conduction current flow of a trench-gate silicon carbide MOSFET according to an embodiment of the present invention. The third quadrant conduction current, as shown by the dashed arrow 204, is the Isd current from the source to the drain. The heterojunction diode has a low barrier and will conduct first; when the voltage difference between the source and drain is greater than the turn-on voltage of the body diode, the body diode will also conduct.

[0064] In this embodiment of the invention, a heterojunction polysilicon layer 91 filled in a second trench is provided on the outer side of the first side of the channel region 61, thereby forming a heterojunction diode in contact with the silicon carbide epitaxial layer 2. The heterojunction diode has a low barrier height, thus having the advantage of a low on-state voltage drop, which can reduce the on-state voltage drop in the third quadrant of the device.

[0065] This embodiment of the invention also includes a first buried layer 41 and a first connecting layer 51. The first buried layer 41 is disposed on the outside of the gate trench and extends laterally from a position directly below the heterojunction polysilicon layer 91 to a position near the side of the gate trench. This allows a lateral current path composed of silicon carbide epitaxial layers 2 to be formed on the top of the first buried layer 41, and a longitudinal current path composed of silicon carbide epitaxial layers 2 to be formed between the second side of the first buried layer 41 and the bottom of the gate trench. In this way, the first buried layer 41 can effectively control the current path of the heterojunction diode while providing good protection for the gate dielectric layer 10, which is beneficial for reducing the on-resistance of the device. Furthermore, by connecting the first buried layer 41 to the channel region 61 and then to the source through the first connecting layer 51, the depletion region between the first buried layer 41 and the silicon carbide epitaxial layer 2 can be further contracted when the device is turned on in the third quadrant, thereby facilitating current flow and reducing the conduction loss of the device when it is operating in the third quadrant.

[0066] The embodiments of the present invention can also adjust the proportion of the injection region corresponding to the first connection layer 51 and the non-injection region outside the first connection layer 51 through layout design. When the proportion of the non-injection region increases, that is, the proportion of the injection region decreases, the on-resistance can be further reduced.

[0067] In addition, the heterojunction diodes of this invention do not have bipolar degradation problems, thereby improving the reliability of the device under long-term operating conditions.

[0068] Therefore, the embodiments of the present invention can integrate heterojunction diodes, reduce the on-state voltage drop in the third quadrant of the device, reduce conduction losses, and improve reliability.

[0069] The embodiments of the present invention do not require an externally connected SiC Schottky diode in reverse parallel, so the present invention does not introduce additional parasitic parameters and has low manufacturing cost.

[0070] The embodiments of the present invention can realize the integration of heterojunction diodes, thereby overcoming the problems of high forward turn-on voltage drop, large conduction loss, bipolar degradation when the device is turned on in the third quadrant, and the reliability risks caused thereto by SiC MOSFET body diodes.

[0071] The key aspect of this invention is the formation of a heterojunction structure by etching and depositing polysilicon on the source side of a trench-gate silicon carbide MOSFET, and connecting it to the source via a front-side metal. This creates a heterojunction diode with a current path that is first lateral and then vertical. The heterojunction barrier between polysilicon and silicon carbide is lower than the PN junction barrier height of silicon carbide, therefore the trench-gate silicon carbide MOSFET integrating this heterojunction diode will have a lower third-quadrant on-state voltage drop. Figure 1A first connection layer 51 with intermittent injection is also provided in the z direction. In the case of N-type device, the first connection layer 51 is a P-type doped connection layer. The uninjected area is used for current flow when the third quadrant is turned on. The injected area is used to connect the first buried layer 41 to the channel region 61, and then to the source. When the third quadrant is turned on, the depletion region of the first buried layer 41 and the silicon carbide epitaxial layer 2 can be contracted, which is conducive to current flow and reduces conduction loss.

[0072] In this embodiment of the invention, the lateral current path is mainly located in the first conductivity type doped silicon carbide epitaxial layer 2 between the first buried layer 41 and the channel region 61. The lateral current path should not be interrupted when it is conducting in the third quadrant, so that a conducting current can be formed.

[0073] In this embodiment of the invention, injecting an N-type current spreading layer on the surface of the silicon carbide epitaxial layer 2 can reduce the specific on-resistance of the device.

[0074] In this embodiment of the invention, the heterojunction polysilicon layer 91 can be P-type doped or N-type doped. When it is N-type doped, the barrier of the heterojunction will be lower and the on-state voltage drop in the third quadrant will also be lower.

[0075] like Figures 3A to 3G The diagram shown is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate silicon carbide MOSFET according to an embodiment of the present invention. Figures 3A to 3G The corresponding cross-sectional positions are all Figure 1 The xy plane at the dashed line BB and Figure 2B The cross-sectional positions are the same; the manufacturing method of trench gate silicon carbide MOSFET in this embodiment of the invention includes: like Figure 3A As shown, a silicon carbide epitaxial layer 2 doped with a first conductivity type is provided, and a drain region 1 heavily doped with the first conductivity type is formed on the back side of the silicon carbide epitaxial layer 2.

[0076] In the method of this embodiment, a current spreading layer doped with a first conductivity type is also formed in the surface region of the silicon carbide epitaxial layer 2. The doping concentration of the current spreading layer is greater than that of the silicon carbide epitaxial layer 2 and is used to reduce the specific on-resistance. The bottom surface of the current spreading layer can be located below the top surface of the subsequent first buried layer 41.

[0077] In the method of this embodiment of the invention, taking an N-type device as an example, the silicon carbide epitaxial layer 2 is N-type doped, the drain region 1 is composed of an N-type doped silicon carbide substrate, and the silicon carbide epitaxial layer 2 is formed on the surface of the silicon carbide substrate.

[0078] like Figure 3AAs shown, a first buried layer 41 is formed in a selected region within the silicon carbide epitaxial layer 2 by ion implantation of the second conductivity type. Similarly, the following description focuses on the structure on the left side of the gate trench, while the symmetrical structure on the right side of the gate trench is shown separately, such as the first buried layer 42 on the right side.

[0079] In the method of this embodiment of the invention, taking an N-type device as an example, the steps for forming the first buried layer 41 include: An oxide layer is deposited, and after photolithography, Al ions are implanted at a temperature of 300K to 1000K to form the first buried layers 41 and 42. After implantation, the mask layer is removed and the surface is cleaned.

[0080] like Figure 3B As shown, a first connecting layer 51 is formed in a selected region on top of the first buried layer 41 by implantation of ions of the second conductivity type; there are intervals between each first connecting layer 51 along the length direction of the first buried layer 41. In the method of this embodiment of the invention, the width of each first connecting layer 51 is smaller than the width of the first buried layer 41. Figure 3B The cross-section shows the width direction of the first connecting layer 51. The length direction of the first connecting layer 51 is along the direction perpendicular to the plane of the paper. Figure 1 The z-axis direction in the present invention. In the method of this embodiment, the formation area of ​​the first connection layer 51 is defined by the layout. In the lateral current path, the specific on-resistance is adjusted by adjusting the area ratio of the first connection layer 51. The smaller the area ratio of the first connection layer 51, the lower the specific on-resistance.

[0081] In the method of this embodiment of the invention, taking an N-type device as an example: the steps of forming the first interconnect layer 51 include: An oxide layer is deposited, and after photolithography, Al ions are implanted at a temperature of 300K to 1000K to form the first connecting layers 51 and 52. After implantation, the mask layer is removed and the surface is cleaned.

[0082] like Figure 3C As shown, a channel region 6 is formed in a selected area of ​​the surface region of the silicon carbide epitaxial layer 2 by ion implantation of the second conductivity type. At this time, the channel region 6 has not yet been divided into channel regions 61 and 62 by the gate trench, so the channel regions 61 and 62 are an integral structure, i.e., the channel region 6. The top surface of the first interconnect layer 51 contacts the bottom surface of the channel region 6, thereby connecting the first buried layer 41 and the channel region 6. Similarly, the top surface of the first interconnect layer 52 contacts the bottom surface of the channel region 6, thereby connecting the first buried layer 42 and the channel region 6.

[0083] In the method of this embodiment of the invention, taking an N-type device as an example: the steps for forming the channel region 6 include: An oxide layer is deposited, and after photolithography, Al ions are implanted at a temperature of 300K to 1000K to form the first connecting layers 51 and 52. After implantation, the mask layer is removed and the surface is cleaned.

[0084] like Figure 3C As shown, ions heavily doped with the first conductivity type are implanted into a selected region of the surface region of the channel region 61 to form a source region 71. A symmetrical source region 72 is also formed.

[0085] In the method of this embodiment of the invention, taking an N-type device as an example: the steps for forming the source region 71 include: An oxide layer is deposited, and after photolithography, N-ion implantation is performed at a temperature of 300K to 1000K to form source regions 71 and 72. After implantation, the mask layer is removed and the surface is cleaned.

[0086] like Figure 3D As shown, ions heavily doped with the second conductivity type are implanted into a selected area of ​​the surface region of the channel region 61 to form a channel contact region 81, which is located outside the source region 71. A symmetrical channel contact region 82 is also formed.

[0087] In the method of this embodiment of the invention, taking an N-type device as an example: the steps of forming the channel contact region 81 include: An oxide layer is deposited, and after photolithography, Al ions are implanted at a temperature of 300K to 1000K to form channel contact regions 81 and 82. After implantation, the mask layer is removed and the surface is cleaned.

[0088] like Figure 3E As shown, etching is performed to form a second trench in the top region of the silicon carbide epitaxial layer 2 on the outer side of the first side of the trench region 61. Then, a heterojunction polysilicon layer 91 is filled in the second trench. The heterojunction polysilicon layer 91 and the bottom silicon carbide epitaxial layer 2 are in contact to form a heterojunction diode. A symmetrical heterojunction polysilicon layer 92 is also formed.

[0089] In the method of this embodiment of the invention, the heterojunction polysilicon layer 91 is P-type doped or N-type doped. For N-type devices, when the heterojunction polysilicon layer 91 is N-type doped, the heterojunction barrier is lower.

[0090] like Figure 3FAs shown, forming a trench gate includes forming a gate trench, forming a gate dielectric layer 10 on the inner surface of the gate trench, and filling the gate trench with a gate conductive material layer 11; the second side of the channel region 61, which is longitudinally traversed by the gate trench and covered by the side of the gate conductive material layer 11, is used to form the channel of the MOSFET; the second side of the source region 71 is aligned with the side of the gate trench; the top surface of the first buried layer 41 is lower than the bottom surface of the gate trench, and the length direction of the first buried layer 41 is the same as the length direction of the gate trench. It can be seen that the gate trench traverses the channel region 6 and divides the channel region 6 into left and right channel regions 61 and 62.

[0091] In the method of this embodiment of the invention, the gate dielectric layer 10 is a gate oxide layer, and the gate conductive material layer 11 is a polysilicon gate.

[0092] The steps involved in forming a trench grid include: An oxide layer is deposited, and after photolithography, reactive ion etching is performed on the silicon carbide epitaxial layer 2 to form a gate trench. A carbon cap is then covered, and impurities are activated by annealing at a high temperature above 1600°C. The impurities are then thermally oxidized to form a gate oxide layer, i.e., the gate dielectric layer 10. Next, polysilicon is deposited and etched to form a polysilicon gate, i.e., the gate conductive material layer 11.

[0093] The first side of the first buried layer 41 extends to the first side or the outer side of the second trench. In this application, the first side of the second trench is the side of the second trench away from the gate trench. The silicon carbide epitaxial layer 2 located above the top surface of the first buried layer 41 forms a lateral current path, and the spacing between each first connection layer 51 is part of the lateral current path. The second side of the first buried layer 41 is located outside the side of the corresponding gate trench and forms a longitudinal current path with the silicon carbide epitaxial layer 2 located between the second side of the first buried layer 41 and the bottom of the gate trench. The lateral current path and the longitudinal current path form the current path of the heterojunction diode. Figure 3F In the middle, a first connecting layer 51 is formed above the top surface of the first buried layer 41, therefore Figure 3F There is no lateral current path in the cross-section shown; please refer to [reference needed] for lateral current paths. Figure 2A As shown. Figure 3F In the middle, the heterojunction diodes connected in parallel on the left and right sides of the gate trench share the same longitudinal current path located between the first buried layers 41 and 42.

[0094] Also includes: like Figure 3G As shown, an interlayer membrane 12 is formed.

[0095] The interlayer film 12 is etched to form contact hole openings, and ohmic contact regions 131, 132, 141, and 142 are formed at the bottom of the contact hole openings. Metal is then filled into the contact hole openings to form contact holes. In some embodiments, the interlayer film 12 is first etched to form contact hole openings corresponding to the top of the ohmic contact regions 131 and 132 and an alloy is deposited; then the interlayer film 12 is etched again to form contact hole openings corresponding to the top of the ohmic contact regions 141 and 142 and an alloy is deposited.

[0096] A front metal layer 15 is formed and patterned to form a source and a gate. The top of the source region 71 is connected to the source through a corresponding contact hole, and the corresponding contact hole at the top of the source region 71 is also in contact with the channel contact region 81. The heterojunction polysilicon layer 91 is also connected to the source through a corresponding contact hole at the top.

[0097] After completing the front-side process, it also includes: like Figure 2B As shown, a back metal layer 3 is formed on the back side of the drain region 1 and forms the drain electrode.

[0098] In the method of this embodiment, the back metal layer 3 is formed by back sputtering Ni alloy and annealing.

[0099] In the method of this embodiment, the trench-gate silicon carbide MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. Other embodiments may also use a P-type trench-gate silicon carbide MOSFET, with the first conductivity type being P-type and the second conductivity type being N-type.

[0100] This invention realizes a trench-gate silicon carbide MOSFET with integrated heterojunction diode. This invention forms a heterojunction structure by etching and depositing polysilicon near the source side of the trench-gate silicon carbide MOSFET, and connecting it to the source through front metal, thus forming a heterojunction diode with a current path of first lateral and then vertical. The heterojunction barrier between polysilicon and silicon carbide is lower than the PN junction barrier height of silicon carbide. Therefore, the trench-gate silicon carbide MOSFET with integrated heterojunction diode will have a lower third quadrant on-state voltage drop. Taking N-type devices as an example, in Figure 1 A P-type doped connection layer, namely the first connection layer 51, is also provided in the z direction. The un-implanted area is used for current flow when the third quadrant is turned on. The injected area is used to finally connect the P-type doped buried layer, namely the first buried layer 41, to the P-type doped channel contact region 81, and then to the source. When the third quadrant is turned on, the depletion region of the P-type doped buried layer and the N-type silicon carbide epitaxial layer can be contracted, which is conducive to current flow and reduces conduction loss. The embodiments of the present invention can adjust the ratio of implanted and non-implanted regions in the P-type doped interconnect layer by layout control. When the proportion of non-implanted regions is increased, the specific on-resistance of the device will be further reduced.

[0101] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A trench-gate silicon carbide MOSFET, characterized in that, include: A silicon carbide epitaxial layer doped with a first conductivity type has a drain region heavily doped with a first conductivity type formed on the back side of the silicon carbide epitaxial layer. A trench gate includes a gate dielectric layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench; A second conductivity type channel region is formed in the silicon carbide epitaxial layer, and the second side of the channel region, which is longitudinally passed through the channel region and covered by the side of the gate conductive material layer, is used to form the channel of the MOSFET. A heavily doped source region of the first conductivity type is formed in the surface region of the channel region and the second side of the source region is aligned with the side of the gate trench. A first buried layer doped with a second conductivity type, wherein the top surface of the first buried layer is lower than the bottom surface of the gate trench; A second trench is formed in the top region of the silicon carbide epitaxial layer on the outer side of the first side of the trench region, and a heterojunction polysilicon layer is filled in the second trench. The heterojunction polysilicon layer and the bottom silicon carbide epitaxial layer are in contact to form a heterojunction diode. The first side of the first buried layer extends to the first side of the second trench or to the outside, and the silicon carbide epitaxial layer located above the top surface of the first buried layer forms a lateral current path. The second side of the first buried layer is located outside the side of the corresponding gate trench and the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench forms a longitudinal current path. The lateral current path and the longitudinal current path form the current path of the heterojunction diode. In the overlapping region of the first buried layer and the channel region, a plurality of first interconnect layers doped with a second conductivity type are formed to connect the first buried layer to the channel region. There is a gap between each first interconnect layer along the length direction of the first buried layer. The gap between each first interconnect layer is part of the lateral current path. The length direction of the first buried layer is the same as the length direction of the gate trench.

2. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: The width of each of the first connecting layers is smaller than the width of the first buried layer.

3. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: A second conductivity type heavily doped channel contact region is also formed in the surface region of the channel region, and the channel contact region is located outside the source region; The top of the source region is connected to the source electrode composed of the front metal layer through a contact hole, and the contact hole corresponding to the top of the source region is also in contact with the channel contact region; The heterojunction polysilicon layer is also connected to the source electrode through the corresponding contact hole at the top.

4. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: The gate trench has a channel region, a source region, a heterojunction polysilicon layer, a first buried layer, and a first interconnect layer formed on both sides, and is symmetrical about the center of the gate trench.

5. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: A current spreading layer doped with a first conductivity type is also formed in the surface region of the silicon carbide epitaxial layer. The doping concentration of the current spreading layer is greater than that of the silicon carbide epitaxial layer and is used to reduce the specific on-resistance.

6. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: The formation area of ​​the first connection layer is defined by the layout. In the lateral current path, the on-resistance is adjusted by adjusting the area ratio of the first connection layer. The smaller the area ratio of the first connection layer, the lower the on-resistance.

7. The trench-gate silicon carbide MOSFET as described in claim 1, characterized in that: The heterojunction polycrystalline silicon layer is P-type doped or N-type doped.

8. The trench-gate silicon carbide MOSFET according to any one of claims 1 to 7, characterized in that: The trench-gate silicon carbide MOSFET is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the trench-gate silicon carbide MOSFET is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

9. A method for manufacturing a trench-gate silicon carbide MOSFET, characterized in that, include: A silicon carbide epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the silicon carbide epitaxial layer. A first buried layer is formed in a selected region within the silicon carbide epitaxial layer by implanting ions of a second conductivity type. A first interconnect layer is formed in a selected area on top of the first buried layer by implanting ions of a second conductivity type. There is a gap between each of the first connecting layers along the length direction of the first buried layer; A second conductivity type ion implantation is performed to form a channel region in a selected area of ​​the surface region of the silicon carbide epitaxial layer. The top surface of the first connecting layer and the bottom surface of the channel region are in contact to achieve the connection between the first buried layer and the channel region. A source region is formed in a selected area of ​​the surface region of the channel region by implanting ions heavily doped with the first conductivity type. A second trench is formed in the top region of the silicon carbide epitaxial layer on the outer side of the first side of the trench region by etching, and then a heterojunction polysilicon layer is filled in the second trench. The heterojunction polysilicon layer and the bottom silicon carbide epitaxial layer are in contact to form a heterojunction diode. Forming a trench gate includes forming a gate trench, forming a gate dielectric layer on the inner surface of the gate trench, and filling the gate trench with a gate conductive material layer; the second side of the channel region, which is longitudinally traversed by the gate trench and covered by the side of the gate conductive material layer, is used to form the channel of a MOSFET. The second side of the source region is aligned with the side of the gate trench; The top surface of the first buried layer is lower than the bottom surface of the gate trench, and the length direction of the first buried layer is the same as the length direction of the gate trench; The first side of the first buried layer extends to the first side or outside of the second trench, and a lateral current path is formed by the silicon carbide epitaxial layer located above the top surface of the first buried layer, with the spacing between each of the first interconnecting layers being a component of the lateral current path; the second side of the first buried layer is located outside the side of the corresponding gate trench and a longitudinal current path is formed by the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench, and the current path of the heterojunction diode is formed by the lateral current path and the longitudinal current path.

10. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that: The width of each of the first connecting layers is smaller than the width of the first buried layer.

11. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that, After forming the source region, the process also includes: Ions heavily doped with a second conductivity type are implanted to form a channel contact region in a selected area of ​​the surface region of the channel region, the channel contact region being located outside the source region.

12. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 11, characterized in that, Also includes: An interlayer film is formed, the interlayer film is etched to form contact holes, a front metal layer is formed, and the front metal layer is patterned to form the source and gate. The top of the source region is connected to the source electrode through a corresponding contact hole, and the contact hole corresponding to the top of the source region is also in contact with the channel contact region; The heterojunction polysilicon layer is also connected to the source electrode through the corresponding contact hole at the top; After completing the front-side process, it also includes: A back metal layer is formed on the back side of the leak area.

13. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that: The gate trench has a channel region, a source region, a heterojunction polysilicon layer, a first buried layer, and a first interconnect layer formed on both sides, and is symmetrical about the center of the gate trench.

14. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that: A current spreading layer doped with a first conductivity type is also formed in the surface region of the silicon carbide epitaxial layer. The doping concentration of the current spreading layer is greater than that of the silicon carbide epitaxial layer and is used to reduce the specific on-resistance.

15. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that: The formation area of ​​the first connection layer is defined by the layout. In the lateral current path, the on-resistance is adjusted by adjusting the area ratio of the first connection layer. The smaller the area ratio of the first connection layer, the lower the on-resistance.

16. The method for manufacturing a trench-gate silicon carbide MOSFET as described in claim 9, characterized in that: The heterojunction polycrystalline silicon layer is P-type doped or N-type doped.

17. The method for manufacturing a trench-gate silicon carbide MOSFET as described in any one of claims 9 to 16, characterized in that: The trench-gate silicon carbide MOSFET is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the trench-gate silicon carbide MOSFET is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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