Preparation method of high-absorptivity silicon-based passivation contact battery

Abstract

The invention discloses a preparation method of a high-absorptivity silicon-based passivation contact battery, which comprises the following steps: firstly, providing a strategy for reducing a B-O recombination problem in p +-poly, introducing a p +-poly-Si layer formed by taking Ga as an alternative dopant into a battery structure, and enabling the Ga to have a high separation coefficient, low solubility and a larger atomic radius; the oxide damage can be reduced, and the p < + >-poly-Si contact performance can be improved; researches show that Ga doped in the SiOx layer has no significant peak value, the doping concentration is close to the solid solubility limit of Ga in Si, and a high Jsc value and excellent Voc are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of the solar photovoltaic industry, and particularly relates to a preparation method of a high-absorption silicon-based passivated contact cell. Background Art

[0002] At the current stage, crystalline silicon cells still dominate the global photovoltaic market. The first large-scale production of crystalline silicon cells was aluminum back surface field (Al-BSF) cells, which have many advantages such as simple process flow, mature technology, and low cost. However, the full contact of silicon / aluminum on the back of the cell causes serious carrier recombination, and the relatively low reflectivity of the aluminum back surface field results in poor long-wavelength light response. These problems lead to low cell efficiency.

[0003] Subsequently, with the mature development of surface alumina passivation technology, it evolved to PERC cells (Passivated Emitter and Rear Cell). On the basis of conventional Al-BSF cells, a passivation layer was added, effectively reducing the carrier recombination rate on the back of the cell, reducing the recombination of electron-hole pairs, enabling more photo-generated carriers to be collected and form current. At the same time, combined with laser grooving technology, a local aluminum back surface field is formed in the contact area, improving the cell efficiency. PERC cells can also combine SE technology on the front surface, selectively heavily doping in the electrode contact area, reducing the recombination probability of carriers in the emitter, enhancing the collection efficiency of the cell for photo-generated carriers, and further improving the photoelectric conversion efficiency. Its optimization in the contact area makes the current transmission inside the cell smoother and improves the fill factor of the cell.

[0004] Later, it evolved to TOPCon cells (Tunnel Oxide Passivated Contact cells), with doped polysilicon thin film as the core, achieving efficient passivation and power transmission through an ultra-thin oxide layer. TOPCon cells adopt a tunnel oxide layer and a doped polysilicon layer, which can effectively reduce the surface recombination rate of the cell. This enables the cell to better collect and utilize carriers, and the photoelectric conversion efficiency is improved. Currently, its mass production efficiency has reached a relatively high level and there is still potential for further improvement. TOPCon cells also have the technical advantages of low temperature coefficient and high bifaciality. Its shortcoming mainly lies in its front surface. The front surface poly-silicon layer has strong optical absorption, while the doping concentration of the homojunction diffusion junction is relatively low, the contact resistance of the emitter is large, and the optical loss is caused by the shading of the grid lines.

[0005] Developing synchronously with TOPCon cells are HJT (Heterojunction with Intrinsic Thin-film) cells. HJT cells have a symmetric structure and an intrinsic amorphous silicon layer, with high carrier collection efficiency, which can effectively reduce carrier recombination. This structure enables it to have a relatively high level of photoelectric conversion efficiency and significant room for improvement, facilitating the enhancement of the output power of photovoltaic power generation. Both the front and back sides of HJT have achieved passivated contacts, thereby obtaining a relatively high open-circuit voltage. However, there is relatively serious parasitic absorption in the amorphous silicon layer on its front surface, and it is not advantageous in terms of short-circuit current.

[0006] To avoid the optical losses caused by the shading of the front grid lines of conventional cells, XBC (Interdigitated Back Contact) cells have emerged. Its metal electrodes are all arranged in an interdigitated pattern on the back of the cell, creating more light-absorbing area for the front side and further improving the overall photoelectric conversion efficiency of the cell. BC is not an isolated cell technology. TBC is essentially a combination of TOPCon and BC technologies; HBC is essentially a combination of HJT and BC technologies. The competition between TBC and HBC is essentially a further differentiated competition between TOPCon and HJT. However, the technical barrier of BC is high, and the production process of the cell is relatively long. In particular, the production of the back electrode is rather cumbersome, requiring 2 - 3 laser grooving processes. The leakage problem caused during the laser grooving process is an important bottleneck restricting the production yield of the cell. Due to the intercrossing of the back electrodes, corresponding adjustments also need to be made in the solder ribbon design / welding process and the encapsulation process.

[0007] Also being actively researched recently are tandem cells, which are battery structures that stack multiple cell units together. They have many advantages such as high energy density, high voltage output, strong battery performance stability, and a wide spectral absorption range.

[0008] As the battery technology roadmap continues to iterate and the efficiency continues to increase, the photovoltaic efficiency is approaching the limit, which has brought continuous breakthroughs in cost and scale. All types of cells are facing severe technical challenges.

[0009] In the conventional TOPCon cell structure, the contact performance of n + -poly-Si is excellent, approaching the limit of mass production. However, the contact recombination loss on its front surface is a bottleneck. In particular, limitations such as the separation of boron in the interfacial oxide and boron-induced damage affect its performance. At the same time, in the conventional TOPCon cell structure, the front parasitic absorption and transmission losses cannot be underestimated. Summary of the Invention

[0010] The purpose of this section is to outline some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract, and the title. However, such simplifications or omissions cannot be used to limit the scope of the present invention.

[0011] In view of the above problems and / or those existing in the prior art, the present invention is proposed.

[0012] Therefore, an object of the present invention is to overcome the deficiencies in the prior art and provide a method for preparing a high-absorption silicon-based passivated contact cell.

[0013] To solve the above technical problems, the present invention provides the following technical solutions: A method for preparing a high-absorption silicon-based passivated contact cell, comprising the following steps: Step (1): Using a single-crystalline silicon wafer as a silicon substrate, forming a worm-like uneven surface morphology to obtain a large-pit-shaped surface morphology with the damaged layer removed. Step (2): Forming a high-absorption hole morphology on the surface of the substrate prepared in the process of Step (1). Step (3): Forming a stacked p + layer on the surface prepared in Step (2), where the front side from top to bottom is a poly layer / tunneling layer / poly layer / tunneling layer. Step (4): Formation of the front poly finger structure: First, remove the BSG layer on the front surface, then form a patterned mask on the front surface, and finally perform an etch-back treatment in an alkaline etching solution to remove the B-doped a-Si in the unmasked area, that is, the top layer of the stacked p + layer. Step (5): Deposition of the front gallium-doped p ++ -poly-Si layer: Sputter-deposit on the front side using a Ga-doped Si target to form 10-50 nm of Ga-doped a-Si. Step (6): Remove the BSG and the diffusion barrier layer on the back side to expose the silicon substrate. Step (7): Back gallium-doped phosphorus (P) n + -poly-Si structure: Form 100-200 nm of P-doped a-Si and anneal. Step (8): Remove the mask layer on the front surface and the diffusion barrier layer and the PSG layer on the back surface in a 2-6% concentration HF solution to obtain a clean surface. Step (9): Deposition of the passivation layer AlO x / SiN x : First passivate the front surface of the single-crystalline silicon wafer with alumina, and then deposit silicon nitride on the front and back surfaces of the silicon wafer. The thickness of the silicon nitride is 70-90 nm and the refractive index is 1.8-2.1. Step (10): Simultaneously print the main grid and the fine grid on the front and back surfaces, use a non-burn-through type silver paste slurry, and complete the production of the battery finished product through a sintering process temperature of 700-850 °C.

[0014] As a preferred embodiment of the preparation method of the present invention, in step (1), a worm-like uneven surface topography is formed, and the surface reflectivity is 25% ± 3%.

[0015] As a preferred embodiment of the preparation method of the present invention, in step (2), a high-absorbance hole morphology is formed, where the reflectivity is controlled at 5% ± 2%, and the hole size is 200 - 400 nm.

[0016] As a preferred embodiment of the preparation method of the present invention, in step (3), a stacked p + layer is formed on the front side, and the top-down structure is: The poly layer has a thickness of 20 nm - 70 nm and a surface concentration of 1e 20 -1e 21 atoms / cm 3 ); The tunneling layer is 1 nm - 2 nm; The poly layer has a thickness of 20 nm - 50 nm and a surface concentration of 1e 20 -1e 21 atoms / cm 3 ; The tunneling layer is 1 nm - 2 nm.

[0017] As a preferred embodiment of the preparation method of the present invention, in step (4), the front-side polyfinger structure is formed. In the heavily doped region, due to the mask layer, the original stacked p + layer structure is maintained, and the top-down structure is: The poly layer has a thickness of 20 nm - 70 nm and a surface concentration of 1e 20 -1e 21 atoms / cm 3 ; The tunneling layer is 1 nm - 2 nm; The poly layer has a thickness of 20 nm - 50 nm and a surface concentration of 1e 20 -1e 21 atoms / cm 3 ; The tunneling layer is 1 nm - 2 nm; In the lightly doped region, the topmost layer of the stacked poly is removed, and the top-down structure is: The poly layer has a thickness of 20 nm - 50 nm and a surface concentration of 1e 20 -1e 21 atoms / cm 3 ; The tunneling layer is 1 nm - 2 nm.

[0018] As a preferred embodiment of the preparation method of the present invention, wherein: in the step (5), the structure is formed by sputtering deposition on the front side using a Ga-doped target to form a Ga-doped a-Si with a thickness of 10 - 50 nm and a doping concentration of 1×10 18 ~1×10 20 atom / cm 3 .

[0019] As a preferred embodiment of the preparation method of the present invention, wherein: the steps (6) - (8) include, first removing the backside BSG and the diffusion barrier layer, then preparing a tunneling layer on the backside and then forming a P-doped P-n + -poly-Si structure, wherein the concentration of P element is 1×10 20 ~1×10 21 atom / cm 3 ; Removing the diffusion barrier layer and the mask layer on the front surface and the PSG layer on the back surface to obtain a complete junction structure.

[0020] As a preferred embodiment of the preparation method of the present invention, wherein: in the step (9), first passivate the front side of the silicon wafer with alumina, wherein the thickness of the alumina is 2 - 20 nm; Then deposit silicon nitride films on the front and back sides, with a thickness of 70 - 90 nm and a refractive index of 1.8 - 2.1.

[0021] As a preferred embodiment of the preparation method of the present invention, wherein: for the electrode in the step (10), the front electrode is prepared in the heavily doped region, and the graphic structure matches the graphic structure of the laser oxidation, and the sintering temperature is 700 - 850 °C.

[0022] Another object of the present invention is to overcome the deficiencies in the prior art and provide a high-absorption silicon-based passivated contact battery, characterized in that: starting from the front side of the battery, from top to bottom in sequence are: Ag electrode (7), AlO x / SiN x stacked passivation and antireflection layer (6), Ga-doped p ++ -poly-Si layer (5), tunneling layer (4), B-doped p + -poly-Si to form finger layer (3), tunneling layer (2), substrate (1), tunneling layer (8), P-doped n + -poly-Si layer (9), SiN x stacked passivation layer (10) and back metal electrode (11); Wherein, Front structure: Surface morphology of the substrate (1): Formed in step (1) and step (2), first acid-etched to form worm-shaped large-size pits, and then a nano-scale high-absorbance hole-like morphology was prepared; Tunneling layer (2): Corresponding to the formation of the stacked p + layer, achieved by in-situ oxidation or non-in-situ oxidation; Boron-doped p + -poly-Si formed finger structure layer (3): Formed in step (3) during the formation of the stacked p + layer and step (4) during the formation of the front poly finger structure; Tunneling layer (4): Formed in step (5) during the deposition of the front gallium-doped layer. A tunneling layer was deposited first before preparing the p ++ layer, corresponding to the tunneling layer (4) in the battery structure; Gallium-doped p ++ -poly-Si layer (5): Formed in step (5) during the deposition of the front gallium-doped layer, corresponding to the gallium-doped p ++ -poly-Si layer (5) in the battery structure; AlO x / SiN x Stacked passivation and antireflection layer (6): Formed in step (9) during the deposition of the passivation layer. The passivation layer was deposited after the complete junction region structure was prepared, corresponding to the stacked passivation and antireflection layer (6) in the battery structure; Ag electrode (7): Formed in step (10) by screen printing. The electrode was prepared after passivation, corresponding to the Ag electrode (7) in the battery structure; Back structure: Tunneling layer (8): Formed in step (7) on the n + -poly-Si layer. After the complex front junction region structure was prepared, it was necessary to first remove the back BSG and the diffusion layer by step (6) to expose the silicon substrate, and then a tunneling layer was prepared on its surface, corresponding to the tunneling layer (8) in the battery structure; Phosphorus-doped n + -poly-Si layer (9): Formed in step (7) on the n + -poly-Si layer, corresponding to the phosphorus-doped n + -poly-Si layer (9) in the battery structure; SiN x Stacked passivation layer (10): Formed in step (9) during the deposition of the SiN passivation layer x ; Back metal electrode (11): Formed in step (10) by screen printing.

[0023] Advantages of the present invention: The present invention first presents a method to reduce p +Strategies for the B-O compound problem in poly-Si are presented. Secondly, a solution is given to balance the contradiction between parasitic absorption and metal contact recombination. At the same time, a surface morphology with high light absorption rate and low interface recombination is introduced, and the problems of high technical difficulty, high cost, and low yield of XBC cells are also avoided. Description of the Drawings

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. Among them: Figure 1 Structural diagram of a high-absorption P-type silicon-based passivated contact cell in an embodiment of the present invention.

[0025] Figure 2 Structural diagram of a conventional tunneling oxide passivated contact cell in the comparative example of the present invention.

[0026] Figure 3 Schematic diagram of the preparation method of a high-absorption P-type silicon-based passivated contact cell in an embodiment of the present invention.

[0027] Figure 4 High-absorption hole reflectivity curve graph in an embodiment of the present invention.

[0028] Figure 5 High-absorption hole surface morphology graph in an embodiment of the present invention.

[0029] Figure 6 Front-side gallium-doped p ++ -ECV curve graph of the lightly doped region during poly-Si layer deposition.

[0030] Figure 7 Front-side gallium-doped p ++ -ECV curve graph of the heavily doped region during poly-Si layer deposition.

[0031] Figure 8 Failure example graph of the high-absorption hole morphology in the comparative example of the present invention.

[0032] Figure 9 ECV test curve graph after the heavily doped region of the stacked poly fails in the comparative example of the present invention.

[0033] Figure 10 ECV test curve graph after the failure due to low Ga doping concentration in the comparative example of the present invention. Detailed Embodiments

[0034] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the embodiments of the specification.

[0035] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0036] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0037] In the conventional TOPCon cell structure, the n + -poly-Si contact performance is excellent, but the front surface contact recombination loss is a bottleneck. In particular, limitations such as the separation of boron in the interfacial oxide and boron-induced damage affect its performance. The present invention first presents a strategy to reduce the B-O recombination problem in p + -poly. A p ++ -poly-Si layer formed with Ga as a substitutional dopant is introduced into the cell structure. Ga has a high segregation coefficient, low solubility, and a relatively large atomic radius, which helps to reduce oxide damage and improve the p + -poly-Si contact performance. Research shows that Ga doping has no significant peak within the SiO x layer, and the doping concentration is close to its solid solubility limit in Si, achieving a relatively high Jsc value and excellent Voc. However, the low diffusivity and solubility of Ga in c-Si limit the doping concentration, and non-equilibrium doping methods are required to overcome this.

[0038] In the conventional TOPCon cell structure, the front parasitic absorption and transport losses cannot be underestimated either. The present invention also circumvents the problem of poor compatibility between front absorption and screen-printed metallization processes. To improve the p + -poly-Si contact performance, a thicker stacked p ++ -poly-Si structure is used in the metal contact region, and a thinner stacked p + -poly-Si structure is used in the non-contact region to reduce parasitic absorption. This solution aims to balance the contradiction between parasitic absorption and metal contact recombination.

[0039] The front surface morphology of the battery is a key factor in improving the light absorption efficiency. In the present invention, a nanoscale porous surface morphology is introduced. While having the advantage of high light absorption rate, this morphology avoids the pyramid morphology composed of <111> planes with a relatively high interface defect density. The sharp edges of the pyramid structure cause stress concentration and increase interface recombination, reducing the passivation performance.

[0040] In contrast, XBC solar cells show great potential because of the light absorption over the entire front area and the integration of two doped polysilicon contacts on the back. However, they also face the challenges of increased complexity in back doping and bipolar contacts. The process flow of BC cells is complex. The PN junction and metal contacts on the back need to be precisely patterned, involving multiple process matching problems, which require extremely high requirements for production equipment and process control, increasing the production difficulty and cost. At the same time, it is difficult to control the yield. In addition, factors such as a large amount of silver paste used, high R & D costs, and high technical thresholds further drive up the cost. At the same time, XBC cells usually require the use of high-quality silicon wafers, and have relatively strict requirements for indicators such as the minority carrier lifetime and impurity content of the silicon wafers.

[0041] The high absorption rate silicon-based passivated contact cell structure in the present invention is as Figure 1 shown. The structure of the crystalline silicon cell is as follows: Using a silicon wafer with a high minority carrier lifetime as the substrate (1), starting from the front, there are successively an Ag electrode (7), an AlO x / SiN x stacked passivation and antireflection layer (6), a gallium-doped p ++ -poly-Si layer (5), a tunneling layer (4), a boron-doped p + -poly-Si to form a finger layer (3), a tunneling layer (2), the substrate (1), a tunneling layer (8), a phosphorus-doped n+-poly-Si layer (9), a SiN x stacked passivation layer (10), and a metal electrode (11).

[0042] The process of the high absorption rate silicon-based passivated contact cell in the present invention is as Figure 3 shown. The heavily doped region is composed of a relatively thick stacked poly, which can effectively resist the corrosion of Ag in the paste and avoid the penetration of Ag in the paste. At the same time, the stacked poly can reduce the barrier height and is beneficial for metallization contact; the Ga doping in the lightly doped region can, to a certain extent, slow down the B-O recombination and parasitic absorption, and at the same time can also achieve the best match between the passivation performance and the lateral transport. The specific steps of the preparation method of the high absorption rate silicon-based passivated contact cell in the present invention are as follows: (1) Removing the damaged layer: Using a single crystal silicon wafer as the silicon substrate, in a chain texturing equipment, perform HNO 3HF etching treatment is carried out to form a worm-like uneven surface morphology. (Due to the anisotropic characteristics of acid etching, the corrosion pits are greatly affected by the laser line cutting marks on the silicon wafer surface, and the specific length and width dimensions are not statistically analyzed); This step aims to remove the damaged layer and form a silicon-based surface with different convexities and concavities on the silicon wafer surface; (2) Formation of high-absorbance hole morphology: It can be achieved by means of reactive ion etching (RIE) superimposed with BOE cleaning, wet black silicon texturing, etc. The reflectivity is controlled at 5% ± 2%, and the hole size is 200 - 400 nm; (3)Stacked p + layer formation: It can be achieved by LPCVD or PECVD methods. Through the process of tunneling oxide layer + amorphous silicon + phosphorus diffusion / annealing in sequence, controlling appropriate process parameters, from top to bottom are poly layer / tunneling layer / poly layer / tunneling layer, and the surface p + surface concentration is 1e 20 -1e 21 atoms / cm 3 , and the junction depth is 0.4 - 1.4 µm; (4)Formation of the front poly finger structure: Remove the BSG layer on the front surface, form a patterned mask on the front surface through laser oxidation and other methods, and then perform an etch-back treatment in an alkaline etching solution to remove the outermost p + -poly-Si in the unmasked area, and retain the p + -poly-Si in the masked area; (5)Deposition of the front gallium-doped p ++ -poly-Si layer: ① It is achieved by means of ion implantation plus annealing; ② It is achieved by sputtering deposition on the front surface using a Ga-doped Si target to form 10 - 50 nm of Ga-doped a-Si, and its doping concentration is 1×10 18 ~1×10 20 atom / cm 3 ; (6)Cleaning 1: Remove the BSG and the diffusion bypass layer on the back to expose the silicon substrate. First, use a single-sided chain equipment to pickle to remove the surface BSG, and then use a tank-type alkaline solution to wash away the back diffusion bypass layer; (7)Formation of the back phosphorus-doped (P) n + -poly-Si structure: It can be achieved by in-situ doping or non-in-situ doping methods. Under pure oxygen conditions at 550 - 650 °C, a 1 - 3 nm tunneling oxide layer is prepared on the back surface, and then 100 - 200 nm of P-doped a-Si is formed at a temperature of 500 - 700 °C; The P element concentration is 1×10 20 ~1×10 21 atom / cm 3Finally, anneal in nitrogen atmosphere for 20min~60min, temperature control: 775~1000℃; (8) Cleaning 2: Remove the mask layer on the front surface and the BSG layer on the plating layer and the back surface in a 2~6% concentration HF solution to obtain a clean surface; (9) Passivation layer deposition AlO x / SiN x : The passivation layer is generated by PECVD / ALD: aluminum oxide is passivated on the front side of the single crystal silicon wafer, and the thickness of the aluminum oxide is 2-20 nm; then silicon nitride is plated on the front and back sides of the single crystal silicon wafer, and the thickness of the silicon nitride is 70-90 nm and the refractive index is 1.8-2.1; (10) Screen printing: The main grid and fine grid are printed on the front and back sides at the same time, using non-burn-through silver paste, and the battery is manufactured after a sintering process temperature of 700~850℃.

[0043] Conventional tunnel oxide layer passivation contact cell structures in this field are as follows Figure 2 As shown, the structure of the crystalline silicon cell is as follows: starting from the front side, there are Ag electrode (5), AlO x / SiN x Multilayer passivation anti-reflection layer (4), boron-doped p + -poly-Si layer (3), tunneling layer (2), substrate (1), tunneling layer (6), phosphorus-doped n + -poly-Si layer (7), SiN x A laminated passivation layer (8), a metal electrode (9); The specific steps of its preparation method are as follows: (1) Texturing: Using a single crystal silicon wafer as the silicon substrate, anisotropic etching is performed with KOH and additives in a trough texturing device to form a pyramid-shaped surface morphology. The formation of the pyramid is related to the different atomic arrangements of different crystal faces of the silicon wafer. The corrosion rates of different atomic close-packed faces in alkaline solution are different. Among them, the corrosion rate of the (111) crystal face is the slowest, while the corrosion rates of other crystal faces are relatively fast. The presence of additives will affect the wettability, corrosion rate and anisotropy ratio of the silicon wafer surface, thereby affecting the quality and performance of the velvet structure. (2) Boron diffusion: It is the process of diffusing boron atoms into silicon wafers to form a P-type emitter. Under high temperature conditions, BCl 3 After thermal decomposition, due to concentration differences, boron diffuses from the surface of the silicon wafer to the inside. By controlling the impurity source, oxygen, nitrogen and other gas flow, temperature and time, the oxidation of the silicon wafer surface and the deposition of boron atoms are achieved. To match the subsequent process, the thickness, density and uniformity of BSG are required because it needs to be used as a mask in the subsequent process. (3)Single-sided etching: Etch the edge part of the silicon wafer and the doped part on the back surface through chemical etching; This is achieved on a chain cleaning device. A masking water film is evenly covered on the upper surface of the diffused silicon wafer, and it passes smoothly through the HF etching tank through roller transmission. The lower surface of the silicon wafer contacts and is etched in a floating-on-water manner. This device can achieve a single-sided effect where the lower surface is etched and the upper surface is not affected. By precisely controlling the etching concentration and liquid level depth, the purpose of removing the back surface is achieved; (4)Polishing: Through alkaline polishing, a tower-base-like morphology similar to a square is formed on the back surface, and the front surface is not affected due to the protection of the BSG layer; In a trough-type texturing device, it is etched with KOH and additives. The additives play a role in corrosion inhibition, reducing the anisotropy factor and flattening the corrosion rate, which is beneficial for forming the tower-base-like morphology; The additives also have a protective effect on the BSG layer, making the front junction area not affected by corrosion; Currently, there are two mainstream technical solutions in the industry: polishing first and then texturing, and texturing first and then polishing. Different amorphous silicon deposition routes have different requirements for the back substrate morphology, and the amorphous silicon technology route still has uncertainties. Therefore, the polishing route needs to be adjusted in combination with the subsequent process technology route; (5)Forming the back junction (tunneling oxide layer + amorphous silicon + phosphorus diffusion): LPCVD and PECVD are two parallel technology routes developed in the industry; ① PECVD route: With the help of radio frequency, the reaction gas is formed into plasma locally, and the plasma's strong chemical activity is used to deposit a thin film on the substrate surface. It can achieve in-situ doping, in-situ dope the tunneling oxide layer to form an amorphous silicon layer, combine the steps of preparing the two layers of film, and then perform annealing; The advantages are slight overplating, high yield, fast film formation speed, high doping efficiency, no quartz tube, and low consumable cost; The disadvantages are poor film thickness uniformity, low film density, and easy film explosion because hydrogen is involved in the reaction. ② LPCVD route: Use an LPCVD device to grow a silicon oxide layer and deposit polysilicon through thermal oxidation, and then dope phosphorus into the polysilicon to form a PN junction to form a passivated contact structure. First, prepare the tunneling oxide layer and the intrinsic amorphous silicon layer, and then add P diffusion; The advantages are high process maturity, high film quality, and high production capacity; The disadvantages are the problem of overplating, and the quartz tube used during deposition needs to be cleaned, maintained, and replaced regularly, with a relatively high consumable cost; (6)Single-sided etching + cleaning of overplating: Single-sided etching is carried out on a chain single-sided etching device. The etching tank uses the floating-on-water method. A masking water film is evenly covered on the upper surface of the silicon wafer, and it passes smoothly through the etching tank through roller transmission. HF removes the PSG below and around, and removes the edge PSG of the phosphorus diffusion overdiffusion; Cleaning of overplating is carried out in a trough-type cleaning device. Through chemical etching and cleaning, the polysilicon overplated on the edge and surface impurities during the LPCVD or PECVD process are removed; (7)ALD: Deposit a layer of aluminum oxide by atomic layer deposition. Due to the front surface being in a textured state, atomic layer deposition with better passivation effect is required instead of deposition by plasma method. The coating has the advantages of three-dimensional conformality, uniformity (dense and pore-free), atomic-level thickness control, etc., and there is no damage to the texture by plasma, making it the current best choice for front surface aluminum oxide. (8)Coating: PECVD (SiNx) on both the front and back surfaces. Currently, most silicon nitride films are prepared by tube PECVD. Compared with plate PECVD, its ion bombardment will damage the surface and the uniformity is poor. However, while the ion bombardment causes damage, it can also make hydrogen ions penetrate into the silicon, providing good bulk passivation and bringing an efficiency advantage. (9)Metallization: Print silver electrodes on both the front and back surfaces to collect carriers of the positive and negative electrodes. Through the processes of drying, preheating, sintering, and cooling, the paste is dried, the organic components are burned out, the glass frit reacts with the silicon nitride layer, enabling the paste to form a good ohmic contact with the silicon substrate, and at the same time activating H passivation. Specific embodiments

[0044] In the embodiments of the present invention, the sources of commercially available materials are as shown in Table 1 below.

[0045] Table 1 To further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the structure proposed according to the present invention is described in detail as follows.

[0046] Example 1 The preparation steps of the novel high-absorption P-type silicon-based passivated contact battery are as follows: Use a P-type silicon wafer with a high minority carrier lifetime as the substrate, with a resistivity of 1.2 Ω·cm and a minority carrier lifetime > 1.5 ms.

[0047] (1)Removing damage from the silicon wafer: Using a P-type single-crystalline silicon wafer as the silicon substrate, in a chain texturing equipment, perform HNO 3 / HF etching treatment (etching solution system: HF / HNO 3 / H 2 O volume ratio 1:2.5:1.5) to form a worm-like textured surface with a reflectivity of 24%. (2)Forming a high-absorption hole morphology: ①Through reactive ion etching (RIE), with Cl2 / O2 / SF6 (gas ratio approximately 1:2:1.4), power approximately 1900 W, pressure approximately 20 Pa, and belt speed approximately 130 cm / min; a hole-like pit morphology is formed; the reflectivity is approximately 3.5% (Note: All reflectivity data in this article are obtained by testing with the Zhidong Optoelectronics D8 reflectometer. The reflectometer is qualified by the China National Metrology Bureau. Its working principle is: The common light source is a xenon lamp or a halogen lamp. The light source is incident on the surface of the test sample, and the battery cell is excited through diffuse reflection. The reflected light enters the diffuse reflection integrating sphere and is transmitted through an optical fiber to the spectrometer for detection; in actual operation, before testing with the D8 reflectometer, light intensity calibration is first performed, and then the background plate is measured. The background light sources include a white plate and a black plate. The emissivity of the white plate is 100%, and the reflectivity of the black plate is 0%. Then the reflected light intensity of the sample is measured, and finally, accurate calculations are performed based on the calibration parameters of the instrument, etc., to obtain the accurate reflectivity value. The calculation formula is: R = Ir / Ii * 100%, where Ir is the reflected light intensity and Ii is the incident light intensity); ②Through BOE cleaning to modify the morphology and clean the silicon wafer, with the BOE / H 2 O 2 / H 2 O volume ratio approximately 1 / 1.9 / 1.5, temperature approximately 35 °C, and cleaning time approximately 240 S; The reflectivity of the textured surface after cleaning and modification is approximately 6% (the reflectivity curve is as shown in Figure 4 , Note: The reflectivity curve of the D8 reflectometer is a curve obtained by measuring the reflectivity of the sample at different wavelengths. It can reflect the reflection ability of the sample to light of different wavelengths. The abscissa usually represents the wavelength of light, and the ordinate represents the reflectivity; when testing the surface reflectivity of crystalline silicon solar cells, the wavelength range usually taken is 350 nm - 1050 nm. Within this wavelength range, the reflectivity curve can provide information about the reflection characteristics of the sample in the visible and near-infrared light regions), and the hole diameter is approximately 200 nm - 250 nm (the surface morphology is as shown in Figure 5 ); (3)Formation of the stacked p + -poly-Si layer: Formed by the LPCVD + boron diffusion / annealing method, a tunneling layer and a boron-doped stacked poly are formed on the surface, with a thickness of approximately 50 nm (upper layer) + 20 nm (lower layer), and a surface concentration of 4e 20 atoms / cm 3 . Among them, the oxidation / LPCVD process temperature is 600 °C, the process time is 2.5 hours, the boron diffusion process temperature is 1000 °C, the annealing temperature is 900 °C, and the overall process time is 3 hours. One is doping, where the doped atoms diffuse into the amorphous silicon and form polycrystalline silicon under high-temperature conditions to achieve the crystallization process; (4)Formation of the front poly finger structure: ①Remove the surface BSG layer through a chain cleaning machine, with HF / H2 The volume ratio of O is about 1 / 5, and the cleaning time is about 500S; ② Form a patterned mask on the front surface by laser oxidation. The laser uses a purple skin laser with a power of 3W and an overlap rate of about 50%; ③ Perform an etching-back process in an alkaline etching solution (the alkaline solution ratio is KOH / ADD / H 2 O volume ratio 1:1:180, cleaning temperature 45°C, cleaning time 120S), to remove the B-doped a-Si in the maskless area; (5) Gallium-doped p ++ -poly-Si layer deposition: It is achieved by sputtering deposition on the front surface using a Ga-doped Si target. The vacuum degree during the process must reach 10 - 4 Pa order of magnitude, deposited in a high-purity argon atmosphere. The sputtering power is generally about 100W, the target-substrate distance is usually about 100mm, the temperature is controlled at about 200°C, and the time is about 20min according to the film thickness, and finally a Ga-doped a-Si with good crystallization performance of about 30nm is formed; The ECV of the finally formed lightly doped region is as Figure 6 shown, and the ECV of the heavily doped region is as Figure 7 shown; (6) Cleaning 1: ① Remove the back BSG layer by single-sided etching (the acid solution ratio is HF / H2O volume ratio 1:1.6); ② Remove the lower surface and the edge diffusion layer by trough alkaline cleaning to expose the silicon substrate. The upper surface is protected by the mask layer formed in the previous process and is not affected; (7) n + -poly-Si layer: Adopt LPCVD method to form a tunneling layer and a boron-doped poly layer on the surface; the growth temperature of the tunneling layer is 600°C, the oxygen flow rate is 2000sccm, and the time is 600S; the growth temperature of poly-si is 600°C, the gas flow rate of SiH 4 is about 0.5SLM, the gas flow rate of N 2 is about 0.2SLM, the annealing temperature is 780°C, and the time is 1000S; the tunneling layer is about 2nm, and the thickness of the n + -poly-Si layer is controlled at 220nm, and the surface concentration is 6e 20 atoms / cm 3 .

[0048] (8) Cleaning 2: Remove the doped oxide layers on both the front and back surfaces through alkaline and acid solutions respectively to obtain a clean surface; (9) Passivation layer deposition and antireflection layer deposition: Use ALD method to grow an AlO x layer on both sides, AlO xThickness: 4 nm; The stacked passivation and antireflection film is deposited on both the front and back sides by PECVD. On the front side: SiN x (30 nm) + SiO x N y (15 nm + 15 nm) + SiO x (8 nm). On the back side: SiN x (26 nm) + SiO x (10 nm) + SiN x (63 nm) + SiO x N y (7 nm); The reflectivity is 2%; (10) Screen-printed front electrode: By screen printing, Ag paste is deposited and then sintered to form the front and back electrodes.

[0049] Specifically, the battery structure and the preparation process are described as follows: Front structure: From the silicon substrate upwards, it is successively: The surface morphology of the substrate (1) is formed in: Step (1) removing the damaged layer and (2) forming the high-absorbance hole morphology; First, worm-shaped large pits are etched by acid, and then a nanoscale high-absorbance hole-like morphology is prepared; corresponding to the surface morphology layer between the substrate (1) and the tunneling layer (2) in the battery structure; The tunneling layer (2) is formed in: Step (3) forming the stacked p + layer, which can be achieved by in-situ oxidation or non-in-situ oxidation, etc., corresponding to the tunneling layer (2) in the battery structure; Boron-doped p + -poly-Si formed finger structure layer (3) is formed in: Step (3) forming the stacked p + layer and Step (4) forming the front poly finger structure; This layer is a composite layer in sub-regions, and its formation is relatively complex. First, a uniform stacked poly layer is formed in Step (3), then in Step (4), the front surface BSG layer (the BSG layer is a by-product layer in the process and needs to be removed first before proceeding to the next step) is removed, then a patterned mask layer is formed, and finally, an anti-etching treatment is carried out in an alkaline solution. The unmasked area is etched to form a lightly diffused area, and the masked area is protected by the mask and remains unchanged, which is the heavily diffused area; corresponding to the boron-doped p + -poly-Si formed finger structure layer (3) in the battery structure; The tunneling layer (4) is formed in: Step (5) depositing the front gallium-doped layer. The tunneling layer is deposited first before preparing p ++ corresponding to the tunneling layer (4) in the battery structure; Gallium-doped p ++- The poly-Si layer (5) is formed in: Step (5) deposition of the front gallium-doped layer, corresponding to the gallium-doped p in the cell structure ++ - The poly-Si layer (5); AlO x / SiN x - The stacked passivation and antireflection layer (6) is formed in: Step (9) deposition of the passivation layer, which is deposited after the complete junction region structure is prepared, corresponding to the stacked passivation and antireflection layer (6) in the cell structure; - The Ag electrode (7) is formed in: Step (10) screen printing, and the electrode is prepared after passivation, corresponding to the Ag electrode (7) in the cell structure; Back structure: From the silicon substrate downwards in sequence: - The tunneling layer (8) is formed in: Step (7) n + - poly-Si layer; After the complex front junction region structure is prepared, it is necessary to first remove the back BSG and the diffusion bypass layer through Step (6) to expose the silicon substrate, and then prepare the tunneling layer on its surface, corresponding to the tunneling layer (8) in the cell structure; Phosphorus-doped n + - The poly-Si layer (9) is formed in: Step (7) n + - poly-Si layer; Corresponding to the phosphorus-doped n + - poly-Si layer (9); After that, the complete front and back junction region structures have been prepared, and it is necessary to remove the mask layer and the diffusion bypass layer on the front surface and the PSG layer (as an accessory product layer) on the back surface in HF solution through Step (8) to obtain a clean surface and a complete junction region structure; SiN x - The stacked passivation layer (10) is formed in: Step (9) deposition of the passivation layer SiN x ; - The back metal electrode (11) is formed in: Step (10) screen printing.

[0050] Comparative Example 1 A TOPCon structure battery, starting from the front of the structure in sequence are the Ag electrode (5), AlO x / SiN x Stacked passivation and antireflection layer (4), boron-doped p + - poly-Si layer (3), tunneling layer (2), substrate (1), tunneling layer (6), phosphorus-doped n + - poly-Si layer (7), x Stacked passivation layer (8), metal electrode (9).

[0051] The specific manufacturing steps are as follows: Use an N-type silicon wafer with a high minority carrier lifetime, resistivity of 0.8 Ω·cm, and minority carrier lifetime > 1 ms; S01: Double-sided texturing. Alkaline texturing is carried out in a trough-type machine. The ratio in the solution is (DI:KOH:additive = 240:41:1), the temperature is maintained at 80 °C, and the texturing is carried out for about 11 min; the thinning amount is controlled at about 0.55 g, and the reflectivity is about 10.1%; S02: Front boron p+ diffusion region: Using BCl 3 as the boron source and introducing it into the furnace tube. High-temperature boron diffusion preparation is completed under the conditions of a temperature of 1000 °C to 1050 °C and a pressure of 90 to 150 mbar, forming a doped B a-Si layer with a surface doping concentration of about 2×10 18 atom / cm 3 , a junction depth of about 1.2 µm, and the front sheet resistance is roughly controlled at 500 ohm / cm 3 (test data of P-type monitoring wafers); S03: Backside cleaning. Remove the backside boron-silicate glass (generated in step S02) and the backside p+ diffusion region. Use a chain-type device to clean the backside with 2% concentration of HF, and use a trough-type device to remove the backside polysilicon and complete the backside alkaline polishing topography etching at 70 °C with 5% concentration of KOH. The weight loss is controlled at about 0.3 g, and the reflectivity is about 45.5%; S04: Deposition of doped phosphorus n+ Poly layer: On the backside, the tunneling oxide layer and the in-situ doped P a-Si layer are prepared in a tube-type LPCVD (low-pressure chemical vapor deposition) at 550 to 650 °C. The thickness of the tunneling oxide layer is 2 nm, the thickness of the doped P a-Si is 120 nm, the sheet resistance of the doped poly and the substrate is about 50 ohm / sqr, and the diffusion peak concentration is about 5e 20 atoms / cm 3 ; S05: Frontside cleaning: Remove the polysilicon deposited on the front side. Use a chain-type device to remove the frontside polysilicon with 6% concentration of KOH, and clean the front side with 2% concentration of HF to remove the surface mask layer and the tunneling oxide layer on the surface of the non-masked area. After cleaning, all the core junctions of the battery are formed, and p+(and the textured surface) / n+ should not be damaged.

[0052] S06: Generation of the passivation layer: Use atomic layer deposition (ALD) technology to passivate the front side with aluminum oxide, and the thickness is controlled at 6 nm; then deposit silicon nitride on both the front and back sides. The thickness of the front film is controlled at 75 nm, the refractive index is 2.1, the thickness of the back film is controlled at 7 nm, and the refractive index is 2.06; S07: Screen printing. Simultaneously print the main grid and the fine grid on the front and back sides. Use a non-burn-through type silver paste slurry. The weight gain of the positive electrode is 15 mg, the weight gain of the positive fine grid is 45 mg, the weight gain of the back electrode is 17 mg, and the weight gain of the back fine grid is 50 mg. The finished battery is made through a sintering process temperature of 800 °C.

[0053] Battery performance test results: Under the same test conditions (temperature 25 ± 3°C, light intensity 1000 ± 5 W / m 2 ), calibrated by the German Fraunhofer certified standard wafer, the batteries prepared in the examples were tested; The batteries of Comparative Example 1 were also tested. The summary of the electrical performance comparison gain of the two types of batteries is shown in Table 2 below. This data can reflect the feasibility of this solution.

[0054] Table 2 In the present invention, the formation of high-absorption hole morphology. If the process control is not good, the high-absorption hole morphology may fail. For example, when the temperature during BOE cleaning gets out of control and rises above 40°C, the nano-hole-like pits will be over-etched. The specific failure morphology diagram is as Figure 8 shown.

[0055] In the present invention, the formation of the front poly finger structure. If the process control is not good, the junction area may be damaged, and the oxidation layer mask protection fails during the back-etching process after laser oxidation, and the upper layer of the stacked poly is damaged. For example, when the concentration of KOH in the alkali solution ratio during back-etching cleaning is too high, when the volume ratio of KOH / ADD / H 2 O is 1.2:1:180, the oxidation layer mask failure will occur accidentally, resulting in the washing away of the upper layer of the heavily doped region. This kind of failure is reflected in the ECV test curve as Figure 9 shown.

[0056] In the present invention, a p ++ -poly-Si layer formed by introducing Ga as a substitutional dopant is introduced into the battery structure. If the process control is not good, the surface concentration may be too low or too high. A too low doping concentration will affect the contact performance, and a too high doping concentration will result in serious lattice distortion and atomic aggregation and precipitation; for example, when the temperature control during deposition is not accurate and is too low to 150°C, the doping will be insufficient and the concentration will be too low due to the low doping temperature. This kind of failure is reflected in the ECV test curve as Figure 10 shown.

[0057] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the present invention.

Claims

1. A method for preparing a high-absorption silicon-based passivated contact cell, characterized in that: The following steps are included: Step (1): using a single crystal silicon wafer as a silicon substrate, forming a worm-like uneven surface morphology, and obtaining a large pit-like surface morphology after removing the damaged layer; Step (2): forming a high-absorption rate hole morphology on the surface of the substrate prepared by the process of step (1); Step (3): forming a laminated layer on the surface prepared in step (2) above + Layers, wherein the front side is poly layer / tunneling layer / poly layer / tunneling layer from top to bottom; Step (4): Formation of the front poly finger structure: First remove the front surface BSG layer, then form a patterned mask on the front surface, and finally perform reverse etching in an alkaline etching solution to remove the B-doped a-Si in the unmasked area, i.e., the stacked p + The topmost layer of the layer; Step (5): Front-side Gallium doping ++ -Poly-Si layer deposition: Sputtering deposition is performed on the front side using Ga-doped Si target to form 10~50nm Ga-doped a-Si; Step (6): remove the back BSG and the wrap-around layer to expose the silicon substrate; Step (7): Back-side phosphorus doping (P) n + -poly-Si structure: 100~200nm P-doped a-Si is formed and annealed; Step (8): remove the mask layer on the front surface and the coating layer and the PSG layer on the back surface in a 2-6% concentration HF solution to obtain a clean surface; Step (9): Passivation layer deposition AlO x / SiN x : First, aluminum oxide is passivated on the front side of the single crystal silicon wafer, and then silicon nitride is plated on the front and back sides of the silicon wafer, wherein the thickness of the silicon nitride is 70-90 nm and the refractive index is 1.8-2.1; Step (10): Print the main grid and fine grid on the front and back sides simultaneously, use non-burn-through silver paste, and complete the battery product through a sintering process temperature of 700~850℃.

2. The preparation method according to claim 1, characterized in that: In the step (1), a worm-like uneven surface morphology is formed, wherein the surface reflectivity is 25%±3%.

3. The preparation method according to claim 1, characterized in that: In the step (2), the high-absorption hole morphology is controlled at a reflectivity of 5%±2% and a hole size of 200-400nm.

4. The preparation method according to claim 1, characterized in that: In the step (3), a laminate p is formed on the front side. + Layer, where the top-down structure is: Poly layer, thickness 20nm~70nm, surface concentration 1e 20 -1e 21 atoms / cm 3 ); Tunneling layer, 1nm~2nm; Poly layer, thickness 20nm~50nm, surface concentration 1e 20 -1e 21 atoms / cm 3 ; Tunneling layer, 1nm~2nm.

5. The preparation method according to claim 1, characterized in that: The front poly finger structure in step (4) wherein the heavily doped region is due to the mask layer maintaining the original stacked layers p + Layer structure, from top to bottom: Poly layer, thickness 20nm~70nm, surface concentration 1e 20 -1e 21 atoms / cm 3 ; Tunneling layer, 1nm~2nm; Poly layer, thickness 20nm~50nm, surface concentration 1e 20 -1e 21 atoms / cm 3 ; Tunneling layer, 1nm~2nm; The lightly doped area removes the top layer of the stacked poly, and the structure from top to bottom is: Poly layer, thickness 20nm~50nm, surface concentration 1e 20 -1e 21 atoms / cm 3 ; Tunneling layer, 1nm~2nm.

6. The preparation method according to claim 1, characterized in that: The structure in step (5) is formed by sputtering and depositing a Ga-doped target on the front side to form 10-50 nm Ga-doped a-Si with a doping concentration of 1×10 18 ~1×10 20 atom / cm 3 .

7. The preparation method according to claim 1, characterized in that: The steps (6) to (8) include: First remove the back BSG and the wrapping layer, then prepare the tunneling layer on the back and then form the phosphorus-doped Pn + -poly-Si structure, where the P element concentration is 1×10 20 ~1×10 21 atom / cm 3 ; The wrap-around layer and mask layer on the front surface and the PSG layer on the back surface are removed to obtain a complete junction region structure.

8. The preparation method according to claim 1, characterized in that: In the structure of step (9), aluminum oxide passivation is first performed on the front side of the silicon wafer, wherein the thickness of the aluminum oxide is 2 to 20 nm; Then a silicon nitride film is deposited on the front and back sides, with a thickness of 70~90 nm and a refractive index of 1.8~2.

1.

9. The preparation method according to claim 1, characterized in that: In the electrode of step (10), the front electrode is prepared in the heavily doped region, the pattern structure matches the laser oxidation pattern structure, and the sintering temperature is 700-850°C.

10. A high-absorption silicon-based passivated contact cell prepared by the preparation method according to any one of claims 1 to 9, characterized in that: The front of the battery is as follows from top to bottom: Ag electrode (7), AlO x / SiN x Multilayer passivation anti-reflection layer (6), gallium-doped p ++ -poly-Si layer (5), tunneling layer (4), boron-doped p + -poly-Si forms a finger layer (3), a tunneling layer (2), a substrate (1), a tunneling layer (8), a phosphorus-doped + -poly-Si layer (9), SiN x A laminated passivation layer (10) and a back metal electrode (11); in, Front structure: The surface morphology of the substrate (1) is formed in step (1) and step (2), firstly by acid etching to form worm-like large-sized pits, and then preparing nano-scale high-absorption hole-like morphology; Tunneling layer (2): corresponds to step (3) stacking layer p + Layer formation is achieved by in-situ oxidation or ex-situ oxidation; Boron-doped P + - Finger structure layer (3) formed by poly-Si: formed in step (3) stacking p + Layer formation and step (4) front poly finger structure formation; Tunneling layer (4): formed in step (5) by depositing the front-side gallium-doped layer. ++ A tunneling layer is first deposited, corresponding to the tunneling layer (4) in the battery structure; Gallium-doped p ++ -poly-Si layer (5): formed in step (5) of depositing the front gallium-doped layer, corresponding to the gallium-doped p-type layer in the cell structure ++ - poly-Si layer (5); AlO x / SiN x The laminated passivation anti-reflection layer (6) is formed in the passivation layer deposition step (9). The passivation layer is deposited after the complete junction structure is prepared, corresponding to the laminated passivation anti-reflection layer (6) in the battery structure. Ag electrode (7): formed by screen printing in step (10), the electrode is prepared after passivation is completed, corresponding to the Ag electrode (7) in the battery structure; Back structure: Tunneling layer (8): formed in step (7) + -poly-Si layer. After the complex junction structure on the front side is prepared, it is necessary to first remove the back BSG and the wrap-around layer through step (6) to expose the silicon substrate, and then prepare a tunneling layer on its surface, which corresponds to the tunneling layer (8) in the battery structure; Phosphorus-doped + -poly-Si layer (9): formed in step (7) + -poly-Si layer, corresponding to the phosphorus-doped n-Si layer in the battery structure + - poly-Si layer (9); S N x The stacked passivation layer (10) is formed by depositing SiN in step (9). x ; Back metal electrode (11): formed in step (10) by screen printing.

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