D2D-oriented software-defined interconnection core particle interface and interconnection system thereof

Abstract

The application discloses a D2D-oriented software-definable interconnection core particle interface and an interconnection system thereof, and relates to the technical field of computer software and hardware. The interconnection core particle interface comprises a bus bridging module, an autonomous protocol module, a mainstream protocol module, a protocol management module, a shared SERDES module and a processor configuration module, and a CRG module; wherein the bus bridging module is connected with the autonomous protocol module and the mainstream protocol module, the autonomous protocol module is connected with the protocol management module and the shared SERDES module in sequence, and the mainstream protocol module is connected with the protocol management module and the shared SERDES module in sequence. The application can better meet the requirements of low hardware cost and high compatibility by flexibly configuring and selecting the autonomous protocol interface and the mainstream protocol through software, and by using the shared SERDES module, the signal coding function and the bit width conversion function, and provides a good direction for the landing application of the core particle ecology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a D2D-oriented software-definable interconnection dielet interface and an interconnection system thereof. BACKGROUND

[0002] So far, with the gradual slowing down of Moore's Law, dielet technology is an important way to continuously improve the integration and chip computing power. Unlike traditional monolithic integrated circuit technology, dielet technology needs to mix dies from multiple chip manufacturers or multiple process nodes. If a good D2D (Die-to-Die) interface interconnection protocol is not established, IP / dielets from different manufacturers will not be able to interconnect.

[0003] Currently, the mainstream interconnection interface protocols include SRIO, PCIe and UCIe, etc. These mainstream protocols occupy most of the market of high-speed computer interconnection interface standards and have built a good and mature interconnection ecosystem. However, the above mainstream protocols have the problems of long training time, long transmission delay and complex protocol specification,

[0004] In view of the above problems, the market continues to develop alternative independent interconnection protocols different from the mainstream protocols. In order to meet more free and diverse data transmission modes, compatible with various data communication scenarios (such as general-purpose CPUs, GPUs and FPGAs, etc.), and support more extensive use modes, it is necessary to develop a software-flexible-definable-mode dielet interconnection interface that is compatible with independent protocols and also compatible with mainstream protocols such as SRIO, PCIe and UCIe, etc., without significantly increasing hardware overhead and pin count. SUMMARY

[0005] The present application relates to the technical field of chip design, in particular to a D2D-oriented software-definable interconnection dielet interface and an interconnection system thereof.

[0006] To solve the above technical problems, the present application provides a D2D-oriented software-definable interconnection dielet interface and an interconnection system thereof, which comprises a bus bridge module, an independent protocol module, a mainstream protocol module, a protocol management module, a shared SERDES module, a processor configuration module and a CRG module, wherein

[0007] The bus bridge module is connected with the independent protocol module and the mainstream protocol module, the independent protocol module is connected with the protocol management module and the shared SERDES module in sequence, and the mainstream protocol module is connected with the protocol management module and the shared SERDES module in sequence.

[0008] The processor configuration module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module and the shared SERDES module respectively; and the CRG module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module and the shared SERDES module respectively.

[0009] The D2D data packet of the on-chip bus data has two data flow directions, the first one is that the on-chip data enters the bus bridge module, passes through the autonomous protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES; the second one is that the on-chip data enters the bus bridge module, passes through the mainstream protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES.

[0010] The protocol management module comprises a protocol selection function, and the selection of a specific protocol is defined flexibly by software executed by the processor configuration module and updated by the JTAG interface.

[0011] In an embodiment, the protocol management module comprises a bit width conversion function, and the bit width conversion function is mapped in the circuit through parameter transmission, and the bit width parameter is defined flexibly by software executed by the processor configuration module and updated by the JTAG interface.

[0012] In an embodiment, the protocols of the two data flows are matched with a shared SERDES module, and the 64B / 66B and 8B / 10B signal coding functions with relatively large hardware overhead in the two original protocols are combined and transferred to the protocol management module, and the protocol management module comprises the 64B / 66B and 8B / 10B coding functions.

[0013] In an embodiment, when the protocol management module and the autonomous protocol module and the mainstream protocol module perform data packet transmission, parallel data transmission operation is performed through data signals, clock signals and ready signals.

[0014] In an embodiment, the serial bus rate and the number of links of the shared SERDES module are managed by the processor configuration module, and are processed by a default program in the processor configuration module or are adjusted by the JTAG interface.

[0015] In an embodiment, the interconnection die interface is connected with a cross-chip of a counterpart die, and when the counterpart die is compatible with the autonomous protocol, the current interconnection die interface is configured to communicate with the counterpart die through the autonomous protocol by software; and when the counterpart die is compatible with the mainstream protocol, the current interconnection die interface is configured to communicate with the counterpart die through the mainstream protocol by software.

[0016] The application also provides a D2D-oriented software definable interconnection core particle interface and an interconnection system thereof.

[0017] The application provides a D2D-oriented software definable interconnection core particle interface and an interconnection system thereof, which can flexibly select autonomous protocols and mainstream protocols by changing kernel software in a protocol management module, flexibly adapt different data bit widths in different protocols by software, use mainstream protocols in conventional application scenarios, use low-delay and lightweight autonomous protocols in appropriate application scenarios, and combine and transfer 64B / 66B and 8B / 10B information coding modules with large hardware overhead in the two types of protocols to the protocol management module and share the same electrical physical layer SERDES, thereby greatly reducing hardware overhead and reducing the number of pins by half. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a component diagram of the D2D-oriented software definable interconnection core particle interface provided by the application.

[0019] Figure 2 is a schematic diagram of a software configuration protocol management module circuit for realizing design functions.

[0020] Figure 3 is a system communication data flow of the application through autonomous protocols in a specific case.

[0021] Figure 4 is a system communication data flow of the application through mainstream protocols in a specific case.

[0022] Figure 5 is a use step of the core particle interface and the interconnection system thereof. DETAILED DESCRIPTION

[0023] The application provides a D2D-oriented software definable interconnection core particle interface and an interconnection system thereof, which are further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be noted that the drawings are greatly simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting in describing the embodiments of the application.

[0024] The application provides a D2D-oriented software definable interconnection core particle interface and an interconnection system thereof, which are used for data communication between on-chip dies, such as Figure 1As shown, the bus bridging module, the autonomous protocol module, the mainstream protocol module, the protocol management module, the shared SERDES module, the processor configuration module, and the CRG module are connected. The bus bridging module is connected with the autonomous protocol module and the mainstream protocol module. The autonomous protocol module is connected with the protocol management module and the shared SERDES module. The mainstream protocol module is connected with the protocol management module and the shared SERDES module. The processor configuration module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module, and the shared SERDES module, and is configured with a sideband signal for an initialization process. The CRG module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module, and the shared SERDES module, and provides necessary clock and reset signals for the working processes of the related modules.

[0025] The D2D data packet has two data flow directions. The first one is that the on-chip data enters the bus bridging module, passes through the autonomous protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES. The second one is that the on-chip data enters the bus bridging module, passes through the mainstream protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES. As shown in Figure 3 , if the autonomous protocol is selected, as shown in Figure 4 .

[0026] In order to match a shared SERDES module, the protocol management module includes 64B / 66B and 8B / 10B encoding functions. The 64B / 66B and 8B / 10B signal encoding functions originally existing in two protocols are combined and transferred to the protocol management module, as shown in Figure 2 . The related parameters can be changed in real time through software.

[0027] As shown in Figure 2 , the circuit schematic diagram of the software configured protocol management module is shown. In order to be compatible with the autonomous protocol and the mainstream protocol, the protocol management module includes a protocol selection function, and the protocol selection function is flexibly defined by the software executed by the processor configuration module. In order to be compatible with the autonomous protocol and the mainstream protocol, the protocol management module includes a bit width conversion function, and the bit width conversion function is fixed in the circuit through an asynchronous gearbox.

[0028] In addition, when the protocol management module transmits data packets with the autonomous protocol and the mainstream protocol, 4-way receiving data rx*_data, rx*_pck, rx*_rdy and 4-way sending data tx*_data, tx*_pck, tx*_rdy are needed for handshake operation, wherein * represents 0, 1, 2, and 3.

[0029] The serial bus rate of the shared SERDES module is also managed by the processor configuration module. When the opposite end die is connected across the chip, if the opposite end die is compatible with the autonomous protocol, the current interconnection die interface can communicate with the opposite end die by being configured as the autonomous protocol through software; when the opposite end die is connected across the chip, if the opposite end die is compatible with the mainstream protocol, the current interconnection die interface can communicate with the opposite end die by being configured as the mainstream protocol through software.

[0030] The application also provides a use step of the D2D-oriented software-defined interconnection die interface interconnection system, as shown in the figure. Figure 5 As shown in the figure, the first step is to obtain the application scenario, obtain the specific protocol and the required configuration information; the second step is to develop and compile software according to the configuration information of the first step, and burn the software into the flash through JTAG; the third step is to start the 2-end interconnection die interface by power-on, and the processor configuration module starts to configure until the interface definition is completed.

[0031] In an implementable case, the autonomous protocol is a low-delay lightweight AHB protocol form, and the mainstream protocol is an SRIO protocol form. The first step is to obtain the application scenario, and it is assumed that the opposite end die only supports the SRIO protocol form, and the high-speed serial port rate, bit width and other parameters have also been obtained; the second step is to develop and compile software according to the configuration information of the first step, and the software is to read and write the related registers in the processor configuration module which have been allocated with addresses, and the executable program is obtained by developing and compiling the software using the processor tool chain IDE, and the program is burned into the flash through the JTAG interface; the third step is to start the 2-end interconnection die interface by power-on, and after the reset is cancelled, the CRG module is started and the clock for driving the data stream and other necessary clock signals are generated, the processor configuration module is activated to start executing the instructions in the flash, and the software-defined related registers are configured, and when the instruction execution ends, the current end side is also an interconnection die interface supporting the SRIO protocol form, and can form a data path interconnection system with the opposite end die.

[0032] Compared with the conventional method, in order to simultaneously support the mainstream protocol and the autonomous protocol, two SERDES modules are needed, and there are two sets of interconnection interfaces, which brings more interconnection lines to the interconnection packaging substrate; in addition, there are 64B / 66B and 8B10B signal coding functions in the mainstream protocol module and the autonomous protocol module, which is to enable the SERDES module to reconstruct the corresponding clock signal from the signal.

[0033] The application utilizes the shared SERDES module, merges the signal coding and decoding functions, and simultaneously configures the autonomous protocol interface, the mainstream protocol interface and the bit width conversion through software, so that the high compatibility requirement can be met faster and better, and the hardware cost is reduced.

[0034] In addition, some steps in the embodiments of the present application are implemented by software, and the corresponding software programs can be stored in a readable storage medium, such as an optical disk or a hard disk.

[0035] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application in any way. Any modification or improvement made by a person of ordinary skill in the art based on the above disclosure is within the scope of protection of the claims.

Claims

1. A D2D-oriented software-defined-interconnected core grain interface, characterized in that, Comprise: bus bridge module, autonomous protocol module, mainstream protocol module, protocol management module, shared SERDES module, processor configuration module, CRG module; wherein, The bus bridge module is connected with the autonomous protocol module and the mainstream protocol module, the autonomous protocol module is connected with the protocol management module and the shared SERDES module in sequence, and the mainstream protocol module is connected with the protocol management module and the shared SERDES module in sequence. The processor configuration module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module and the shared SERDES module, and the CRG module is connected with the autonomous protocol module, the mainstream protocol module, the protocol management module and the shared SERDES module. The D2D data packet of the on-chip bus data has two data flow directions, the first one is that the on-chip data enters the bus bridge module, passes through the autonomous protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES; the second one is that the on-chip data enters the bus bridge module, passes through the mainstream protocol module and the protocol management module, and is finally sent out of the chip from the shared SERDES. The protocol management module comprises a protocol selection function, the specific protocol selection is defined flexibly by software executed by the processor configuration module, and the JTAG interface is used for updating and burning.

2. The D2D-oriented software-defined-interconnectable chiplet interface of claim 1, wherein, The protocol management module comprises a bit width conversion function, the bit width conversion function is mapped in the circuit through parameter transmission, and the bit width parameter is defined flexibly by software executed by the processor configuration module, and the JTAG interface is used for updating and burning.

3. The D2D-oriented software-defined-interconnectable chiplet interface of claim 1, wherein, The two data flows are protocols matched with a shared SERDES module, and the 64B / 66B and 8B / 10B signal coding functions with relatively large hardware overhead in the two original protocols are combined and transferred to the protocol management module, and the protocol management module comprises 64B / 66B and 8B / 10B coding functions.

4. The D2D-oriented software-defineable interconnect chiplet interface of claim 3, wherein, When the protocol management module and the autonomous protocol module and the mainstream protocol module perform data packet transmission, parallel data transmission operation is performed through data signals, clock signals and ready signals.

5. The D2D-oriented software-defined-interconnectable chiplet interface of claim 1, wherein, The serial bus rate and the number of link parameters of the shared SERDES module are managed by the processor configuration module, and are specifically processed by a default program in the processor configuration module or are released to the JTAG interface for burning adjustment.

6. The D2D-oriented software-defined-interconnectable chiplet interface of claim 1, wherein, The interconnection chip interface is connected with a cross-chip of a counterpart bare chip, when the counterpart bare chip is compatible with the autonomous protocol, the current interconnection chip interface is configured into the autonomous protocol through software to communicate with the counterpart bare chip, and when the counterpart bare chip is compatible with the mainstream protocol, the current interconnection chip interface is configured into the mainstream protocol through software to communicate with the counterpart bare chip.

7. A D2D-oriented software-defined-interconnectable core interface-interconnected system based on any one of claims 1-6, characterized in that: The use steps of the interconnection system comprise the following steps. In a first step, an application scenario is obtained, a specific protocol and required configuration information are obtained; in a second step, software is developed and compiled according to the configuration information in the first step, and is burned into a flash through a JTAG; in a third step, a power supply is started to start the 2-end interconnection chip interface, and the processor configuration module starts to configure until the interface definition is completed.

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