FPGA-based chip program issuing system

Abstract

The application provides a FPGA-based chip program issuing system and method, and belongs to the technical field of FPGA semiconductor testing, and the method comprises the following steps: a single-chip microcomputer download board is designed, IO pins of the single-chip microcomputer download board are connected with a tested FPGA and a testing machine; a corresponding test program is developed according to test requirements, and a bit program file is generated; a testing machine testing motherboard and a sub-board are designed according to testing machine requirements, download pins of the tested FPGA are connected with the single-chip microcomputer download master board, and corresponding test resources of the testing machine are connected to the tested FPGA in a combination mode of the motherboard or the sub-motherboard; and an at test program is developed. The FPGA-based chip program issuing system and method provided by the application simplify the automatic test process of the tested FPGA, solve the problems of an external download device and the need for a development environment for downloading, and improve the test efficiency and the degree of automation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA semiconductor testing technology, in particular to a chip program issuing system and method based on FPGA. BACKGROUND

[0002] The existing FPGA semiconductor testing based on ATE test program development has the following problems:

[0003] Test program development:

[0004] High development difficulty: FPGA chip functions are complex, and test program development requires a deep understanding of FPGA architecture and functional characteristics, as well as a mastery of relevant testing theories and methods, which makes the development difficult.

[0005] Long development cycle: Due to the difficulty of FPGA test program development, the development cycle is long, especially for complex FPGA chips, the development cycle may be longer.

[0006] Poor maintainability and scalability of test program: As the functions of FPGA chips continue to increase and change, the test program needs to be constantly maintained and expanded. However, due to the complexity of the test program, its maintainability and scalability are often poor, which brings great challenges to the testing work.

[0007] Test equipment and environment:

[0008] High equipment cost: ATE test equipment is expensive, especially for high-end FPGA test equipment, the cost is even higher, which is a big burden for some small test institutions and enterprises.

[0009] Fast equipment update: With the continuous development of FPGA technology, ATE test equipment also needs to be constantly updated to meet new testing needs. However, the update of equipment requires a large amount of investment, which is a big challenge for some testing institutions and enterprises.

[0010] Complex test environment setup: FPGA testing requires the setup of a complex test environment, including test equipment, test software, test fixtures, etc., which requires test personnel to have rich testing experience and professional knowledge. At the same time, the setup of the test environment also requires a large amount of time and effort, which brings great challenges to the testing work.

[0011] Test result analysis and processing:

[0012] Difficult test result analysis: FPGA test results often contain a large amount of data and information, how to accurately analyze the performance and function of the chip from these data and information whether it meets the requirements is a big challenge.

[0013] Test result processing efficiency is low: due to the difficulty of test result analysis, the test result processing efficiency is low, especially for large-scale FPGA testing, the test result processing may take a lot of time and effort. The existing atest test bench to test the FPGA different configuration file needs to switch different files through the FPGA development environment and the downloader, which cannot realize automatic testing and takes a long time

[0014] Visualization and report generation of test results are difficult: how to visualize the test results in an intuitive way and generate detailed test reports is a big challenge. This requires test personnel to have certain programming and data processing ability, and also needs to use some professional test result visualization and report generation tools.

[0015] Therefore, there is an urgent need in the art for a technical solution that can solve one or more of the above problems.

[0016] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It should not be taken as an acknowledgement or any form of suggestion that this information forms a prior art that is already known to those skilled in the art. SUMMARY

[0017] The purpose of the present application is to provide a technical solution for FPGA automatic testing.

[0018] To achieve the above-mentioned purpose, the present application provides the following scheme:

[0019] A chip program issuing system based on FPGA, comprising:

[0020] A single-chip microcomputer download board, the IO pin of the single-chip microcomputer download board is connected with the FPGA under test and the test machine;

[0021] The main control board includes a main control chip, a DDR3 and a QSPI FLASH; the main control board includes 1 gigabit Ethernet interface, 1 UART serial port interface, 1 SD card interface, 1 JTAG download interface, 2 100PIN connector interfaces, a BNAK power voltage switching interface and a plurality of keys LED;

[0022] The main frequency of the main control chip is 866MHz, supporting 200 I / Os at HR end and 120 I / Os at HP end as signal input and output channels; the main control chip includes a processing system with dual-core ARM Cortex-A9 as the core and a programmable logic part equivalent to a piece of FPGA;

[0023] The FPGA includes programmable input / output units, basic programmable logic units, embedded block RAM, a plurality of wiring resources, underlying embedded function units and embedded special hard cores.

[0024] A FPGA-based chip program issuing method, comprising:

[0025] A single-chip microcomputer download board is designed, and IO pins of the single-chip microcomputer download board are connected with a measured FPGA and a tester.

[0026] A corresponding test program is developed according to test requirements, and a bit program file is generated.

[0027] A tester test motherboard and a sub-board are designed according to tester requirements, a download pin of the measured FPGA is connected with the single-chip microcomputer download master board, and corresponding test resources of the tester are connected to the measured FPGA in a combination mode of the motherboard or the sub-motherboard.

[0028] An ATE test program is developed.

[0029] Compared with the prior art, the application has the following beneficial effects:

[0030] The FPGA-based chip program issuing system and method provided by the application simplify an automatic test process of a test FPGA, solve the problems of an external download device and the need for downloading by means of a development environment, solve the problem of how to automatically switch test configuration files in testing, and improve test efficiency and the degree of automation. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0032] Figure 1 A schematic diagram of a master control chip structure is provided for the embodiments of the present application.

[0033] Figure 2 A resource 500 area block pin circuit diagram is provided for the embodiments of the present application.

[0034] Figure 3 A resource 501 area block pin circuit diagram is provided for the embodiments of the present application.

[0035] Figure 4 A resource 502 area block pin circuit diagram is provided for the embodiments of the present application.

[0036] Figure 5 A resource 13 area block pin circuit diagram provided for an embodiment of the present application.

[0037] Figure 6 A resource 34 area block pin circuit diagram provided for an embodiment of the present application.

[0038] Figure 7 A resource 35 area block pin circuit diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0040] The purpose of the present application is to provide a technical solution capable of being used for FPGA automated testing.

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0042] Embodiment 1:

[0043] The present embodiment provides a chip program issuing system and method based on FPGA, which is developed by cooperating with various test machine programs, so that the test machine can be used without the aid of the development environment of FPGA and the downloader, and the developed FPGA configuration file is downloaded through the existing instructions, so as to realize various automated tests. Through the FPGA download board, the developed FPGA configuration file can be issued through the program of the single-chip microcomputer, and the test program of the ATE test machine only needs to issue serial port instructions to the single-chip microcomputer, and the single-chip microcomputer program can automatically issue the corresponding FPGA configuration program to the FPGA, thereby realizing automatic switching of the download file and improving the download efficiency.

[0044] 1. Design a single-chip microcomputer download board, and connect the IO pin of the single-chip microcomputer download board with the measured FPGA and the test machine.

[0045] The main control board is mainly composed of a minimum system of ZYNQ7020+2 DDR3+1 QSPI FLASH.

[0046] The ZYNQ7020 adopts the XC7Z020_2CLG400I chip of Xilinx Company, like Figures 1-7As shown, the ZYNQ7020 chip can be divided into a processor system part Processor System (PS) and a programmable logic part Programmable Logic (PL). In the PS of the ZYNQ7020 chip, two pieces of DDR3 are hung, each piece of DDR3 has a capacity of up to 2Gbit, so that the ARM system can independently process and store data functions. The PS end 1 piece of 32M QSPI FLASH is used to statically store the operating system, file system and user data.

[0047] The main control board has rich peripheral interfaces, including 1 Gbit Ethernet interface, 1 UART serial interface, 1 SD card interface, 1 JTAG download interface, 2 100PIN connector interfaces, BNAK power voltage switching interface and some key LEDs. The main control board includes resource 500 area block, resource 501 area block, resource 502 area block resource 13 area block, resource 34 area block and resource 35 area block and the like.

[0048] The main control chip ZYNQ on the board selects an embedded chip XC7Z020_2CLG400I, the main frequency is 866MHz, the chip core is Cortex-A9 core of ARM company, the on-chip resources are rich, and 200 HR ends and 120 HP ends I / O can be used as signal input and output channels.

[0049] ZYNQ is composed of two main parts: Processor System (PS) and Programmable Logic (PL); the simplified model of ZYNQ architecture is as shown in Figure 1 As shown: the dual-core ARM Cortex-A9 is the core of the processing system (PS, Processing System), and the programmable logic is equivalent to a piece of FPGA.

[0050] On ZYNQ, the core ARM Cortex-A9 is an application-level processor that can run an operating system like Linux, while the programmable logic is based on the FPGA architecture of Xilinx 7 series. ZYNQ architecture realizes the industry standard AXI interface, realizing high-bandwidth and low-delay connection between the two parts of the chip. This means that the processor and the logic part can each play the best use, without the interface overhead between two separate devices. At the same time, the benefits of simplifying the system into a single chip are obtained, including the reduction of physical size and overall cost.

[0051] The PS (Power Supply) component has a fixed architecture, including the processor and system memory. The PL (Power Placement) component is flexible, giving designers a "blank canvas" to create custom peripherals.

[0052] The simplified basic structure of an FPGA consists of six parts: programmable input / output units, basic programmable logic units, embedded block RAM, abundant routing resources, low-level embedded functional units, and embedded dedicated hard cores.

[0053] The highlight of the Zynq-7000 series is its inclusion of a complete ARM processor system, which integrates a memory controller and numerous peripherals, allowing the Cortex-A9 processor to operate completely independently of the programmable logic unit (PL). In Zynq, the power supply circuits for the PL and PS sections are independent, meaning either the PS or PL section can be powered off when not in use.

[0054] 2. FPGA engineers develop corresponding test programs according to test requirements and generate bit program files. These bit files only need to be placed into the corresponding SD card. The test machine program is developed, and the test machine sends corresponding instructions through the serial port. Then, it calls the corresponding bit file in the SD card and sends it to the FPGA under test to run the test program to perform functional tests on the FPGA under test.

[0055] 3. Design the test motherboard and daughterboard of the test machine according to the requirements of the test machine, connect the download pins of the FPGA under test to the microcontroller download main control board, and connect the corresponding test resources of the test machine to the FPGA under test through the motherboard or a combination of motherboard and daughterboard.

[0056] Equipment: General-purpose ATE testing machines, such as J750, V93000, and UltraFlex.

[0057] 4. Develop the test program for ATE. First, establish communication with the microcontroller main control board. Second, download the FPGA program to be tested through the main control board. Finally, set the test resources of the ATE test machine according to the functional test requirements, provide different stimuli, and then collect the test results.

[0058] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0059] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for the general technical personnel in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application. In conclusion, the content of the present specification should not be understood as the limitation of the present application.

Claims

1. A chip program delivery system based on FPGA, characterized in that, include: The microcontroller download board has I / O pins that are connected to the FPGA under test and the test bench. The microcontroller main control board includes a main control chip, two DDR3 and QSPI FLASH chips; the microcontroller main control board includes one Gigabit Ethernet interface, one UART serial port interface, one SD card interface, one JTAG download interface, two 100-pin connector interfaces, a BNAK power supply voltage switching interface, and several LED buttons. The main control chip has a main frequency of 866MHz and supports 200 HR terminals and 120 HP terminals as signal input / output channels; the main control chip includes a processing system based on a dual-core ARM Cortex-A9 and a programmable logic part equivalent to an FPGA. An FPGA includes programmable input / output units, basic programmable logic units, embedded block RAM, several routing resources, low-level embedded functional units, and embedded dedicated hard cores. The application method of the FPGA-based chip program delivery system includes: Develop corresponding test programs according to the test requirements and generate bit program files; Design the test motherboard and daughterboard of the test machine according to the requirements of the test machine, connect the download pins of the FPGA under test to the microcontroller download board, and connect the corresponding test resources of the test machine to the FPGA under test through the motherboard or a combination of motherboard and daughterboard; Develop test programs for ATED; The specific steps for developing the test program for ATED are as follows: First, establish communication between the test bench and the microcontroller main control board. Second, download the FPGA program under test through the microcontroller main control board. Then, set the test resources of the ATE test bench according to the functional test requirements, provide different stimuli, and collect the test results.

Images