Multi-channel arbiter

Abstract

The invention provides a multi-channel arbiter, which comprises a basic arbiter and a polling arbiter, and is characterized in that the basic arbiter is responsible for judging whether high-priority application signals exist in application signals or not, and arbitrating the high-priority signals in sequence until all the high-priority application signals are completed; during the period, the polling arbiter does not work; after the high-priority arbitration is completed, the polling arbitrator performs polling arbitration on the low-priority application signal, and the execution sequence is determined by a loop pointer; finally, arbitration results of the basic arbiter and the polling arbiter are output into an arbitration result signal through a first gate. According to the invention, efficient and ordered task scheduling can be realized.

Description

Technical Field

[0001] This application relates to the field of digital circuits, and particularly to a multi-channel arbiter. Background Art

[0002] In modern computer systems, embedded systems, and various real-time processing systems, task scheduling is a core and complex process. How to efficiently and orderly schedule these tasks to ensure that high-priority tasks are promptly responded to, while not neglecting the processing of low-priority tasks, is a major challenge faced by system designers. To address the above issues, researchers have proposed various task scheduling schemes, among which multi-arbiter is an effective and flexible solution.

[0003] However, the existing designs of multi-channel arbiters often have some limitations, such as low arbitration efficiency, inflexible priority configuration, limited scalability, etc. Therefore, a more efficient, flexible, and easily expandable design scheme for multi-channel arbiters is needed to meet the requirements of modern systems for task scheduling. Summary of the Invention

[0004] In view of this, the embodiments of this application provide a multi-channel arbiter that can achieve efficient and orderly task scheduling.

[0005] The technical solution of the embodiments of this application is implemented as follows:

[0006] In a first aspect, the embodiments of this application provide a multi-channel arbiter, which includes:

[0007] A basic arbiter and a polling arbiter;

[0008] The basic arbiter is used to determine whether there is a high-priority application signal in the application signals. If so, it sequentially performs a first arbitration on the high-priority application signals until all the high-priority application signals are arbitrated. Before all the high-priority application signals are arbitrated, the polling arbiter does not work, and the execution order of the first arbitration is determined based on the numbers of the application signals;

[0009] The polling arbiter is used to perform a second arbitration on the low-priority application signals in the application signals after all the high-priority application signals are arbitrated. The second arbitration is a polling arbitration, and the execution order of the polling arbitration is determined based on a circular pointer;

[0010] The arbitration results of the basic arbiter and the polling arbiter are output as an arbitration result signal after passing through a first multiplexer.

[0011] In a second aspect, the embodiments of this application also provide a system that schedules tasks based on the multi-channel arbiter described in the first aspect.

[0012] In a third aspect, an embodiment of the present application further provides a chip, and the chip is equipped with the system described in the second aspect.

[0013] The embodiments of the present application have the following beneficial effects:

[0014] (1) The high-priority arbitration mode and the low-priority arbitration mode are implemented separately:

[0015] Implementing the high-priority arbitration mode and the low-priority arbitration mode separately enables the system to give priority to processing high-priority application signals, ensuring that critical tasks or urgent requests can be quickly responded to, and improving the real-time performance and reliability of the system; after all high-priority application signals have been arbitrated, the system then turns to process low-priority application signals. This separate processing method avoids interference and conflicts between high-priority and low-priority application signals, and realizes the reasonable allocation and utilization of resources; the separate implementation of the high-priority arbitration mode and the low-priority arbitration mode enables the system to flexibly adjust the arbitration strategy according to actual needs. For example, when the system load is heavy, high-priority application signals can be given priority to ensure the stability and performance of the system; when the system load is light, more low-priority application signals can be processed to improve the utilization rate and efficiency of the system.

[0016] (2) Modify the design logic of the underlying arbitration module:

[0017] By modifying the design of the underlying arbitration module, such as using an arbitration mask to mask the lower-order application signals, the number of signals that the basic arbiter needs to process is reduced. This design simplifies the arbitration process, improves the arbitration efficiency, and enables the system to make arbitration decisions faster. In addition, modifying the design method of the underlying arbitration module can also improve the accuracy of arbitration. For example, by optimizing the logic circuit, errors and delays in the arbitration process are reduced, ensuring the accuracy and reliability of the arbitration result. Moreover, when the system needs to be expanded or upgraded in the future, new arbitration modules can be added or existing arbitration modules can be modified more conveniently, reducing the maintenance cost and complexity of the system.

[0018] In summary, the multi-channel arbiter design of the present invention, by implementing the high-priority arbitration mode and the low-priority arbitration mode separately and modifying the design method of the underlying arbitration module, has beneficial effects such as improving the response speed of the system, reasonable resource allocation, arbitration efficiency, arbitration accuracy, and facilitating expansion and maintenance. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0020] Figure 1 is the schematic diagram of the multi-channel arbiter provided by the embodiment of the present application;

[0021] Figure 2 is the schematic diagram of the basic arbiter provided by the embodiment of the present application;

[0022] Figure 3 is the schematic diagram of the polling arbiter provided by the embodiment of the present application. Specific Embodiments

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. It should be understood that the accompanying drawings in the present application only serve the purposes of illustration and description and are not used to limit the protection scope of the present application. Additionally, it should be understood that the schematic drawings are not drawn to the actual scale. The flowcharts used in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without logical context relationships may be reversed or implemented simultaneously. Furthermore, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of the present application.

[0024] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0025] In addition, the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application usually described and shown in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0026] In the following description, the terms "first", "second", and "third" only distinguish similar objects and do not represent a specific order for the objects. Understandably, "first", "second", and "third" can be interchanged in a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0027] It should be noted that the term "including" will be used in the embodiments of the present application to indicate the existence of the features stated thereafter, but does not exclude the addition of other features.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are for the purpose of describing the embodiments of the present application and are not intended to limit this application.

[0029] See Figure 1 , Figure 1 is the schematic diagram of the multi-channel arbiter provided by the embodiment of the present application, which will be described in conjunction with Figure 1 The present application provides a multi-channel arbiter, and the multi-channel arbiter includes:

[0030] A basic arbiter and a polling arbiter;

[0031] The basic arbiter is used to determine whether there is a high-priority application signal in the application signals. If so, the high-priority application signals are sequentially subjected to a first arbitration until all the high-priority application signals are arbitrated. Before all the high-priority application signals are arbitrated, the polling arbiter does not work, and the execution order of the first arbitration is determined based on the numbers of the application signals;

[0032] The polling arbiter is used to perform a second arbitration on the low-priority application signals in the application signals after all the high-priority application signals are arbitrated. The second arbitration is a polling arbitration, and the execution order of the polling arbitration is determined based on a cyclic pointer;

[0033] The arbitration results of the basic arbiter and the polling arbiter are output as an arbitration result signal after passing through a first selector.

[0034] As Figure 1 shown, the multi-channel arbiter mainly consists of two parts: a basic arbiter priority arbiter and a polling arbiter rr arbiter.

[0035] The basic arbiter first checks whether there is a high-priority application in the input application signal req.

[0036] If there are high-priority applications, it will arbitrate these high-priority applications in the order of the application signal numbers (or other predefined priority orders) until all high-priority applications are processed.

[0037] Before all high-priority applications are processed, the polling arbiter does not work, ensuring that high-priority applications can be processed first.

[0038] When all high-priority applications are processed by the basic arbiter, the polling arbiter starts to work and arbitrates the remaining low-priority applications.

[0039] The polling arbiter processes low-priority applications in a cyclic manner (implemented by a cyclic pointer) to ensure that each low-priority application has a chance to be processed.

[0040] The arbitration results of the basic arbiter and the polling arbiter are selected and integrated through a first multiplexer a. Finally, the integrated arbitration result signal is output to guide the subsequent resource allocation or processing flow.

[0041] The design of the above multi-channel arbiter aims to efficiently process application signals of different priorities. By the basic arbiter giving priority to processing high-priority applications and ensuring that they are not processed before low-priority applications, the response speed of the system and the rationality of resource allocation are guaranteed. At the same time, the polling arbiter ensures that low-priority applications also have a fair chance to be processed. The entire design integrates the results of the two arbiters through the first multiplexer to form the final arbitration output signal.

[0042] In some embodiments, the application signal and the priority configuration signal are ANDed and then enter the basic arbiter for arbitration;

[0043] The application signal and the inverted phase of the priority configuration signal are ANDed and then enter the second multiplexer. The other fixed input of the second multiplexer is 0, and the output signal of the second multiplexer enters the polling arbiter for arbitration;

[0044] Among them, the priority configuration signal is an internal signal, the high-priority application signal is represented as 1, and the low-priority application signal is represented as 0.

[0045] Please continue to refer to Figure 1, the request signal req and the priority configuration signal chn - mask first perform an AND operation. The resulting signal enters the basic arbiter for arbitration. The priority configuration signal is an internal signal used to indicate the priority of the request signal. A high - priority request signal is represented as 1 in the priority configuration signal, and a low - priority request signal is represented as 0. Therefore, when the request signal is ANDed with the priority configuration signal, only high - priority request signals (i.e., requests with the priority configuration signal being 1) will enter the basic arbiter for arbitration.

[0046] For the polling arbiter, the request signal and the inverted (NOT) priority configuration signal perform an AND operation, and the resulting signal enters the second multiplexer. The other fixed input of the second multiplexer is 0. The output signal of the second multiplexer enters the polling arbiter for arbitration. Since the high - priority part of the priority configuration signal is 1 and the low - priority part is 0, after inversion, the high - priority part is 0 and the low - priority part is 1. When the request signal is ANDed with the inverted priority configuration signal, only low - priority request signals (i.e., requests with the priority configuration signal being 0) will pass through the second multiplexer (since the other input is 0, it actually selects the low - priority request signal) and enter the polling arbiter for arbitration. In the embodiment of this application, the priority configuration signal is used to dynamically control the priority of the request signal. By changing the value of the priority configuration signal, the priority order of the request signals can be flexibly adjusted to meet the requirements of different application scenarios.

[0047] In some embodiments, before all high - priority request signals are arbitrated, the second multiplexer continuously receives a 0 signal to send a 0 signal to the polling arbiter, so that the polling arbiter does not work.

[0048] The second multiplexer is responsible for controlling the signal flow to the polling arbiter. Before all high - priority request signals are arbitrated, the second multiplexer continuously receives a fixed 0 signal as one of its inputs. Since the other input of the second multiplexer is from the AND result of the request signal and the inverted priority configuration signal (i.e., the selection path for low - priority request signals), but during high - priority arbitration, the signals on this path are not allowed to pass because the fixed 0 input of the second multiplexer acts as a blocking effect. Therefore, regardless of the state of the low - priority request signals, during high - priority arbitration, the polling arbiter always receives a 0 signal.

[0049] The polling arbiter is designed such that when it receives a 0 signal, it does not perform arbitration operations. Before all the high-priority request signals are arbitrated, the polling arbiter remains in an inactive state, thus ensuring the priority processing of high-priority request signals. In this way, high-priority request signals can be processed first. Only after all high-priority request signals are processed does the polling arbiter start working to process low-priority request signals. Through the control of the second multiplexer, the system can flexibly switch the working state of the arbiter to adapt to the processing requirements of request signals with different priorities.

[0050] Next, the basic arbiter and the polling arbiter provided by the embodiments of the present application will be described.

[0051] For the basic arbiter, in some embodiments, the basic arbiter determines the priority based on the bit order of the request signal, and the request signal with a lower bit has a higher priority.

[0052] Only 1 bit of 1 is included in the arbitration result of the basic arbiter, and the remaining bits are 0.

[0053] The basic arbiter determines the priority according to the bit order of the request signal. In this mechanism, the request signal with a lower bit is given a higher priority. When multiple request signals appear simultaneously, the signal at a lower position (or lower bit order) will be arbitrated and processed first. Through this mechanism, the system can quickly identify and process the request signal with the highest priority without complex priority judgment logic. The arbitration result of the basic arbiter is a signal containing multiple bits (bit), but only one bit is 1 and the remaining bits are 0. The 1 bit in the arbitration result represents the selected request signal, and its position (or bit order) corresponds to the position in the original request signal. The system can quickly locate and process the selected request signal according to this arbitration result.

[0054] In some embodiments, the input signals of the basic arbiter include an arbitration mask and the request signal, and the arbitration mask is an internal signal.

[0055] The first bit of the arbitration mask is set to 0 by grounding. The result of the logical OR operation between the first bit of the arbitration mask and the first bit of the request signal is used to modify the next bit of the arbitration mask, and the next bits of the arbitration mask are all modified to 1 to mask the request signals after the lower bits.

[0056] The arbitration result is generated by the logical AND operation between the inverted arbitration mask and the request signal.

[0057] Please refer to Figure 2 , Figure 2 which is the schematic diagram of the basic arbiter provided by the embodiments of the present application. As shown in Figure 2As shown, the arbitration mask masked_higher is an internal signal used to control the arbitration process. Each bit of it (corresponding to labels [0] - [i - 1]) is related to the corresponding bit of the request signal (corresponding to labels [0] - [i - 1]), and is used to determine which request signal bits should be considered and which should be masked. The request signal is an externally input signal representing the arbitration requests of each channel. Each bit represents the arbitration request of a channel, where 1 indicates a request and 0 indicates no request.

[0058] The first bit of the arbitration mask is set to 0 by grounding. Each bit of the arbitration mask (except the first bit) is modified based on the result of the OR operation between the previous bit and the corresponding bit of the request signal. Specifically, if the previous bit of the arbitration mask is 0 and the corresponding bit of the request signal is also 0, the current bit of the arbitration mask remains 0 (or may default to 0 according to the design because the 0 of the previous bit has determined that the current bit will not be considered). If the previous bit of the arbitration mask is 0 but the corresponding bit of the request signal is 1, the current bit of the arbitration mask is modified to 1, indicating that the lower - order request signals starting from this bit will be masked (because the AND result of the arbitration mask and the request signal will be considered in the subsequent arbitration process). When a certain bit of the arbitration mask is modified to 1, due to the nature of the OR operation, subsequent bits usually remain 1, thus masking all lower - order request signals.

[0059] The inversion of the arbitration mask is to invert each bit in the arbitration mask. The inverted arbitration mask is ANDed with the request signal. Since the masked bits in the arbitration mask (i.e., the bits originally 1) become 0 after inversion, the corresponding arbitration results of these bits will also be 0 after the AND operation. Only the unmasked bits (i.e., the bits originally 0 in the arbitration mask) become 1 after inversion and may produce an arbitration result of 1 when ANDed with the request signal.

[0060] The arbitration result is a signal with the same number of bits as the request signal, where only one bit (or possibly multiple bits, but usually designed to select only the highest - priority one bit) is 1, representing the selected request signal bit, and the remaining bits are 0, representing the unselected request signal bits.

[0061] The basic arbiter realizes the priority arbitration of the request signal through the interaction between the arbitration mask and the request signal. The arbitration mask is used to mask the lower - order request signals to ensure that only the highest - priority request signal can be selected and an arbitration result is generated.

[0062] For the polling arbiter, in some embodiments, the input signals of the polling arbiter include a cycle pointer and the request signal. The cycle pointer is an internal signal. In the initial state, the cycle pointer points to the first channel or a specific channel.

[0063] Please refer to Figure 3 ,Figure 3 This is the schematic diagram of the polling arbiter provided by the embodiments of the present application. As Figure 3 shown, the cyclic pointer rr_pointer is an internal signal used to indicate the currently polled channel. In the initial state, the cyclic pointer is set to point to the first channel or a specific channel. The role of the cyclic pointer is to move cyclically among multiple channels to ensure that each channel has the opportunity to be polled. The application signal is an externally input signal representing the arbitration requests of each channel. Each bit represents the arbitration request of one channel, where 1 indicates a request and 0 indicates no request.

[0064] In the initial state, the cyclic pointer points to the first channel or a specific channel, ready to start polling. The polling arbiter checks the application signals of each channel in sequence according to the indication of the cyclic pointer. If the application signal of the current channel is 1, indicating that the channel has an arbitration request, the polling arbiter will select this channel as the arbitration result. If the application signal of the current channel is 0, indicating that the channel has no arbitration request, the polling arbiter will continue to move to the next channel for polling.

[0065] The output of the polling arbiter indicates which channel is selected for subsequent processing or response. The arbitration result is a signal with the same number of bits as the application signal, where only one bit (representing the selected channel) is 1 and the remaining bits are 0.

[0066] In some embodiments, the polling arbiter includes two sets of basic arbiters. The application signal is subjected to polling arbitration by the first set of basic arbiters. After all the application signals are polled, the next application signal is subjected to priority arbitration by the second set of basic arbiters.

[0067] In some embodiments, the arbitration results of the first set of basic arbiters and the arbitration results of the second set of basic arbiters pass through a third multiplexer and then output the polling arbitration result signal.

[0068] Please continue to refer to Figure 3 , the polling arbiter includes two sets of basic arbiters, which are respectively used to perform different arbitration tasks. The first set of basic arbiters is responsible for polling arbitration, that is, checking the application signals of each channel in sequence to determine which channel has an arbitration request. The second set of basic arbiters is responsible for priority arbitration. After the first set of basic arbiters completes a round of polling, it makes a priority judgment on the next (or a specific set of) application signals and selects the channel with the highest priority.

[0069] In the polling arbitration stage, the application signal first undergoes polling arbitration by the first set of basic arbiters. The first set of basic arbiters checks the application signals of each channel in sequence according to the cycle. When all channels are polled, the first set of basic arbiters completes its task and is ready to enter the next stage.

[0070] After the polling arbitration stage is completed, the next (or a specific group of) request signals are subject to priority arbitration by the second group of basic arbitrators. The second group of basic arbitrators selects the channel with the highest priority according to the priority of the request signals (determined, for example, by bit order, weight, or other means). This stage is carried out at the end of each polling cycle, and polling arbitration is carried out at other times.

[0071] The arbitration results of the first group of basic arbitrators and the arbitration results of the second group of basic arbitrators are both input to the third mux c, and the third mux outputs the polling arbitration result signal.

[0072] The embodiment of the present application further provides a system, and the system schedules tasks based on the multi-channel arbitrator described in any one of the above embodiments.

[0073] The embodiment of the present application further provides a chip, and the chip is equipped with the system described in the above embodiment.

[0074] In summary, the embodiments of the present application have the following beneficial effects:

[0075] (1) The high-priority arbitration mode and the low-priority arbitration mode are implemented separately:

[0076] Implementing the high-priority arbitration mode and the low-priority arbitration mode separately enables the system to give priority to processing high-priority request signals, ensuring that critical tasks or urgent requests can be quickly responded to, improving the real-time performance and reliability of the system; after all high-priority request signals have been arbitrated, the system turns to process low-priority request signals. This separate processing method avoids interference and conflicts between high-priority and low-priority request signals, and realizes the reasonable allocation and utilization of resources; the separate implementation of the high-priority arbitration mode and the low-priority arbitration mode enables the system to flexibly adjust the arbitration strategy according to actual needs. For example, when the system load is heavy, high-priority request signals can be processed first to ensure the stability and performance of the system; when the system load is light, more low-priority request signals can be processed to improve the utilization rate and efficiency of the system.

[0077] (2) Modify the design logic of the underlying arbitration module:

[0078] By modifying the design of the underlying arbitration module, such as using an arbitration mask to shield the application signals after masking the lower bits, the number of signals that the basic arbiter needs to process is reduced. This design simplifies the arbitration process, improves the arbitration efficiency, and enables the system to make arbitration decisions faster. Additionally, the method of modifying the design of the underlying arbitration module can also improve the accuracy of arbitration. For example, through optimized logic circuits, the errors and delays in the arbitration process can be reduced to ensure the accuracy and reliability of the arbitration results. Moreover, when the system needs to be expanded or upgraded in the future, new arbitration modules can be added or existing arbitration modules can be modified more conveniently, reducing the maintenance cost and complexity of the system.

[0079] In summary, the multi-channel arbiter design of the present invention, by implementing the priority arbitration mode and the low-priority arbitration mode separately and modifying the design method of the underlying arbitration module, achieves beneficial effects such as improving the system's response speed, reasonable resource allocation, arbitration efficiency, arbitration accuracy, and facilitating expansion and maintenance.

[0080] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the method embodiments, which will not be elaborated herein. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there can be other division methods in actual implementation. Also, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or modules can be in electrical, mechanical, or other forms.

[0081] The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0082] In addition, in each embodiment of this application, the functional units can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0083] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A multi-channel arbitrator, characterized in that: The multi-channel arbiter comprises: Basic arbitrator and polling arbitrator; The basic arbitrator is used to determine whether there is a high-priority application signal in the application signal. If yes, the high-priority application signals are subjected to first arbitration in sequence until all the high-priority application signals are arbitrated. Before all the high-priority application signals are arbitrated, the polling arbitrator does not work. The execution order of the first arbitration is determined based on the serial number of the application signal. The polling arbitrator is used to perform a second arbitration on the low-priority application signals in the application signals after all the high-priority application signals have been arbitrated, the second arbitration is a polling arbitration, and the execution order of the polling arbitration is determined based on the loop pointer; The arbitration results of the basic arbitrator and the polling arbitrator are output as arbitration result signals after passing through a first selector.

2. The multi-channel arbiter according to claim 1, characterized in that: The application signal and the priority configuration signal are ANDed together and then enter the basic arbitrator for arbitration; The application signal and the priority configuration signal are ANDed together and then enter the second gate, another fixed input of the second gate is 0, and the output signal of the second gate enters the polling arbitrator for arbitration; Among them, the priority configuration signal is an internal signal, the high priority application signal is represented by 1, and the low priority application signal is represented by 0.

3. The multi-channel arbiter according to claim 2, characterized in that: Before all the high priority application signals are arbitrated, the second selector continues to receive a 0 signal to send a 0 signal to the polling arbitrator, thereby making the polling arbitrator inoperative.

4. The multi-channel arbiter according to claim 1, characterized in that: The basic arbiter determines the priority based on the bit order of the application signal, and the lower-order application signal has a higher priority; The arbitration result of the basic arbiter includes only 1 bit which is 1, and the remaining bits are 0.

5. The multi-channel arbiter according to claim 4, characterized in that: The input signal of the basic arbiter includes an arbitration mask and the application signal, and the arbitration mask is an internal signal; The first bit of the arbitration mask is generated by grounding and setting it to 0, and the next bit of the arbitration mask is modified by the result of the phase OR of the first bit of the arbitration mask and the first bit of the application signal, and the next bit of the arbitration mask is modified to 1 to shield the application signal after the low bit; The arbitration result is generated by performing AND operation on the inversion of the arbitration mask and the application signal.

6. The multi-channel arbiter according to claim 5, characterized in that: The input signal of the polling arbiter includes a loop pointer and the application signal. The loop pointer is an internal signal. In an initial state, the loop pointer points to the first channel or a specific channel.

7. The multi-channel arbiter according to claim 6, characterized in that: The polling arbitrator includes two groups of basic arbitrators. The application signal is subjected to polling arbitration by the first group of basic arbitrators. When all the application signals are polled, the next application signal is subjected to priority arbitration by the second group of basic arbitrators.

8. The multi-channel arbiter according to claim 7, characterized in that: The arbitration results of the first group of basic arbiters and the arbitration results of the second group of basic arbiters are output as polling arbitration result signals after passing through a third selector.

9. A system, characterized in that: The system schedules tasks based on the multi-channel arbiter described in any one of claims 1-8.

10. A chip, characterized in that: The chip carries the system as claimed in claim 9.

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