High-speed low-loss transverse power device with super junction structure

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a high-speed low-loss transverse power device with a super junction structure. Compared with a traditional SSA-LIGBT, the SSA-LIGBT has the advantages that additional transverse N strips and transverse P strips are introduced to the top of a drift region, and longitudinal P strips are introduced between an anode P + and an anode N +. At the beginning of forward conduction, high-concentration transverse N strips in a drift region provide low-resistance channels for electrons, so that more electron currents reach an anode P + region, and longitudinal P strips between the anode P + region and an anode N + region can increase anode distributed resistance, so that the new structure can eliminate a voltage turn-back effect and realize low conduction voltage drop under a smaller cellular size; in the turn-off process, the transverse N strips and the transverse P strips in the drift region are mutually depleted to accelerate the extraction of excess carriers in the drift region, and the distance between the anode P + region and the anode N + region is shortened, so that the turn-off loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and specifically relates to a high-speed and low-loss lateral power device with a superjunction structure. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a power semiconductor device widely used in the field of power electronics. It has the advantages of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and BJT (Bipolar Junction Transistor), such as simple drive, fast switching speed, low on-state voltage drop, and low loss. Currently, it has been widely used in aerospace, smart home appliances, power transmission and other fields. Compared with bulk silicon technology, SOI technology has many advantages such as high speed, low power consumption, high integration, easy isolation, and radiation resistance. In addition, lateral IGBT (LIGBT) is easy to monolithically integrate, which makes SOI LIGBT become the core component of monolithic power integration chips.

[0003] SOI LIGBT belongs to a bipolar device. During forward conduction, due to the conductivity modulation effect in the drift region, it can significantly reduce the on-state voltage drop (V on ) of the device during conduction. However, this also leads to the need to extract more carriers, resulting in a relatively obvious tail current during the turn-off process, increasing the turn-off time and turn-off loss (Turning off loss, E off ) of the device. To improve the trade-off relationship between the on-state voltage drop and the turn-off loss of the device, a common method is to introduce a short-circuit anode structure, but it leads to the snapback phenomenon, which is not conducive to the parallel use of devices. On this basis, a separated short-circuit anode structure is proposed. Compared with the traditional short-circuit anode structure, an anode N+ is introduced beside the anode P+. When the distance (L b ) between them is long enough, the corresponding anode distributed resistance enables the anode P+ / N-buffer junction to directly enter the bipolar conduction mode, but a relatively large L b size is required to eliminate the snapback effect, resulting in low chip area utilization. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a high-speed and low-loss lateral power device with a superjunction structure, which can greatly shorten the distance L between the anode N+ and the anode P+ b , thereby eliminating the snapback effect at a very short L b distance, improving the chip area utilization, and achieving the trade-off between low on-state voltage drop and low turn-off loss.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A high-speed and low-loss lateral power device with a superjunction structure, comprising a P substrate 1, a buried oxide layer 2, and an N-type drift region 3 stacked in sequence from bottom to top along the vertical direction of the device; on the upper layer of the N-type drift region 3, there are successively a cathode structure, a gate structure, a superjunction bar structure, and a separated short-circuit anode structure along the lateral direction of the device;

[0007] The cathode structure includes a P-well region 4, a P+ body contact region 5, and a cathode N+ region 6; the P+ body contact region 5 and the cathode N+ region 6 are in contact with each other and are juxtaposed on the upper layer of the P-well region 4, and the cathode N+ region 6 is on the side close to the separated short-circuit anode structure. The upper surfaces of the P+ body contact region 5 and the cathode N+ region 6 jointly lead out a terminal as the cathode electrode;

[0008] The superjunction bar structure is located on the upper layer of the N drift region 3 between the P-well region 4 and the separated short-circuit anode structure, and includes N bars 8 and first P bars 10 arranged longitudinally along the device; one end of the N bars 8 is in contact with the P-well 4, and there is a gap between the other end and the separated short-circuit anode structure; there are gaps between both ends of the first P bars 10 and the P-well region 4 and the separated short-circuit anode structure respectively;

[0009] The gate structure is a planar gate structure, including planar gate polysilicon 7 and a field oxide layer 9; the field oxide layer 9 covers the upper surfaces of the N bars 8 and the first P bars 10, and one end of the field oxide layer 9 extends along the upper surface of the P-well region 4 to the upper surface of part of the cathode N+ region 6, and the other end of the field oxide layer 9 extends along the upper surface of the N-type drift region 3 to the upper surface of part of the separated short-circuit anode structure; the planar gate polysilicon 7 is located on the upper surface of the field oxide layer 9, specifically extending from the end of the field oxide layer 9 on the upper surface of the N+ region 6 to the part of the field oxide layer 9 on the upper surfaces of the N bars 8 and the first P bars 10; the gate electrode is led out from the surface of the planar gate polysilicon 7;

[0010] The anode structure includes an N-type buffer layer 11, an anode P+ region 12, a second P bar 13, and an anode N+ region 14; the N-type buffer layer 11, the second P bar 13, and the anode N+ region 14 are arranged in sequence and juxtaposed, and the N-type buffer layer 11 is on the side close to the cathode structure, and the anode P+ region 12 is located inside the upper layer of the N-type buffer layer 11; the field oxide layer 9 covers part of the upper surface of the N-type buffer layer 11, but there is a gap between the field oxide layer 9 and the anode P+ region 12; the upper surfaces of the anode P+ region 12 and the anode N+ region 14 jointly lead out a terminal as the anode electrode.

[0011] Further, the N bars 8 and the first P bars 10 have the same width in the longitudinal direction.

[0012] Further, the N strips 8 and the first P strips 10 are of a gradient structure. Specifically, the width of the N strips 8 linearly increases from the side close to the cathode structure to the side close to the separated short-circuit anode structure, and the width of the first P strips 10 linearly decreases from the side close to the cathode structure to the side close to the separated short-circuit anode structure.

[0013] The beneficial effects of the present invention are as follows: Compared with the traditional separated anode short-circuit LIGBT structure, the present invention greatly reduces the area and size of the chip and improves the area utilization rate of the chip. It can eliminate the snapback phenomenon at a shorter short-circuit anode distance L b ; and during the turn-off process, since the distance between the anode P+ region and the anode N+ region is shortened, the turn-off loss of the device is reduced, and the device has a better trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the manufacturing process is compatible with the high- and low-voltage device processes of power integrated circuits, and the preparation cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of the cell structure of Embodiment 1 proposed by the present invention,

[0015] Figure 2 is Figure 1 the schematic cross-sectional view along AA1 in

[0016] Figure 3 is Figure 1 the schematic cross-sectional view along BB1 in

[0017] Figure 4 is the schematic diagram of Embodiment 2;

[0018] Figure 5 is Figure 4 the top view of the cell after removing the oxide layer and the polysilicon layer of

[0019] Figure 6 is the schematic diagram of Embodiment 3;

[0020] Figure 7 is Figure 6 the top view of the cell after removing the oxide layer and the polysilicon layer of DETAILED DESCRIPTION OF THE INVENTION

[0021] The technical solutions of the present invention will be described in detail below with reference to the drawings and embodiments.

[0022] Embodiment 1

[0023] As Figure 1As shown, the structure of this example is a high-speed and low-loss lateral power device with a superjunction structure, including a P substrate 1, a buried oxide layer 2, and an N-type drift region 3 stacked in sequence from bottom to top in the vertical direction of the device; the N-type drift region 3 includes a cathode structure, a gate structure, a superjunction bar structure (lateral N bars 8, lateral P bars 10), a separated short-circuit anode structure, and a second P bar 13 added to the separated short-circuit anode structure in sequence along the lateral direction of the device;

[0024] In Figure 1 , the lateral direction from the P-well region 4 of the device to the N-type buffer layer 11 is defined as the x direction, the vertical direction from the N-type drift region 3 to the P substrate 1 is defined as the y direction, and the longitudinal direction perpendicular to the xy plane is defined as the z direction;

[0025] The cathode structure is located at the upper left end of the upper semiconductor layer, including a P-well region 4, a P+ body contact region 5, and a cathode N+ region 6; the P+ body contact region 5 and the cathode N+ region 6 are in contact with each other and are arranged side by side on the upper surface of the P-well region 4, and the cathode N+ region 6 is on the side close to the N-type drift region 3, the P+ body contact region 5 is located at the leftmost side of the N-type drift region 3, and the common lead-out end on the upper surface of the P+ body contact region 5 and the cathode N+ region 6 is used as the cathode electrode;

[0026] The gate structure is a planar gate structure, including a planar gate polysilicon 7 and a field oxide layer 9; the field oxide layer 9 is in contact with the cathode N+ region 6, the P-well region 4, and the N-type buffer layer 11 and is located on the upper surface of the N-type drift region 3; the planar gate polysilicon 7 covers the upper surface of the field oxide layer 9, and the gate electrode is led out from the surface of the planar gate polysilicon 7;

[0027] The anode structure includes an N-type buffer layer 11, an anode P+ region 12, a second P bar 13, and an anode N+ region 14; the anode P+ region 12 is located in the upper layer of the N-type buffer layer 11; the second P bar 13 is located on the upper layer of the N-type drift region 3 between the N-type buffer layer 11 and the anode N+ region; one end of the second P bar 13 is connected to the N-type buffer layer 11, and the other end is connected to the anode N+ region 14, and the common lead-out end on the upper surface of the anode P+ region 12 and the anode N+ 14 region is used as the anode electrode;

[0028] It is characterized in that the superjunction bar structure is located on the upper layer of the N-drift region 3 between the P-well region 4 and the separated short-circuit anode structure, and includes transverse N-bars 8 and a first P-bar 10 arranged along the z-direction of the device. The transverse N-bars 8 and the first P-bar 10 have the same width in the z-direction. One end of the N-bars 8 is in contact with the P-well 4, and the other end is spaced from the N-type buffer layer 11 by a certain distance; one end of the first P-bar 10 is spaced from the P-well region 4 by a certain distance, and the other end is spaced from the N-buffer layer 11 by a certain distance; both the N-bars 8 and the first P-bar 10 are located on the lower surface of the field oxide layer 9. The second P-bar 13 is located on the upper layer of the N-type drift region 3 between the N-type buffer layer 11 and the anode N+ region; one end of the second P-bar 13 is spaced from the N-type buffer layer 11 by a certain distance, and the other end is spaced from the anode N+ region 14 by a certain distance.

[0029] The working principle of this example is as follows:

[0030] When the new device is in forward conduction and the anode voltage increases, electrons tend to flow more into the transverse N-bars with higher concentration, providing a low-resistance channel for the electron current. This leads to an increase in the electron current, enabling the anode P+ / N-buffer junction to turn on earlier. The device does not have a single-pole transmission mode, effectively avoiding the snapback phenomenon. At the same time, the longitudinal P-bars introduced in the anode P+ region and the anode N+ region also increase the distributed resistance of the anode, having a certain obstructive effect on electrons, making it more difficult for electrons to be collected by the anode N+ at the initial stage of forward conduction. This also avoids the device operating in the single-pole conduction mode. During the turn-off process of the device, as the anode voltage increases, since the distance between the anode P+ region and the anode N+ region is shortened, the turn-off loss of the device is reduced, and the device has a better trade-off relationship between the on-state voltage drop and the turn-off loss.

[0031] The beneficial effects of the present invention are that, compared with the traditional separated short-circuit anode LIGBT structure, the present invention enters the bipolar mode at a shorter short-circuit anode distance L b and the device has no snapback phenomenon, reducing the area and size of the device and improving the area utilization rate of the chip; due to the shortening of the distance between the anode P+ region and the anode N+ region, the turn-off loss of the device is reduced during the turn-off process.

[0032] Embodiment 2

[0033] As Figure 4As shown, compared with the structure of Embodiment 1, the difference in this example is that the superjunction structure (the first N stripes 8 and the first P stripe 10) of the LIGBT in this example is a stepped structure, that is, the widths of the N stripes 8 and the first P stripe 10 in the z direction are not equal. The width of the transverse N stripes 8 gradually linearly increases from the cathode to the anode, and the width of the first P stripe 10 gradually linearly narrows from the cathode to the anode. Moreover, one end of the N stripes 8 is in contact with the P well 4, and the other end is in contact with the N-type buffer layer 11; one end of the first P stripe 10 is in contact with the P well region 4, and the other end is in contact with the N buffer layer 11;

[0034] Compared with Embodiment 1, by controlling the widths and concentrations of the N stripes 8 and the first P stripe 10 in the z direction, on the basis of the advantages of Embodiment 1, the substrate-assisted depletion effect is effectively suppressed, the charge balance of the device is better maintained, the electric field distribution of the device is optimized, and the breakdown voltage of the device is increased.

[0035] Embodiment 3

[0036] As Figure 6 shown, compared with the structure of Embodiment 2, the difference in this example is that one end of the first P stripe 10 in the superjunction structure of the LIGBT in this example is spaced apart from the P well region 4 by a certain distance, and the other end is spaced apart from the N buffer layer 11 by a certain distance. One end of the N stripes 8 is in contact with the P well 4, and the other end is in contact with the N-type buffer layer 11;

[0037] Compared with Embodiment 2, one end of the first P stripe 10 is spaced apart from the P well region 4 by a certain distance, and the other end is spaced apart from the N buffer layer 11 by a certain distance, which can suppress the extraction of holes, enhance the conductivity modulation effect, and reduce the on-state voltage drop.

Claims

1. A high-speed, low-loss lateral power device with a superjunction structure, comprising a P substrate (1), a buried oxide layer (2) and an N-type drift region (3) stacked in sequence from bottom to top along the vertical direction of the device; characterized in that: The upper layer of the N-type drift region (3) has a cathode structure, a gate structure, a super junction strip structure and a separated short-circuit anode structure in sequence along the lateral direction of the device; The cathode structure comprises a P-well region (4), a P+ body contact region (5), and a cathode N+ region (6); the P+ body contact region (5) and the cathode N+ region (6) are in contact with each other and are arranged in parallel on the upper layer of the P-well region (4), and the cathode N+ region (6) is on one side of the separated short-circuit anode structure, and the upper surfaces of the P+ body contact region (5) and the cathode N+ region (6) have a common lead end as a cathode electrode; The super junction strip structure is located in the upper layer of the N drift region (3) between the P well region (4) and the separated short-circuit anode structure, and comprises an N strip (8) and a first P strip (10) arranged in the longitudinal direction of the device; one end of the N strip (8) is in contact with the P well (4), and the other end is spaced apart from the separated short-circuit anode structure; and both ends of the first P strip (10) are spaced apart from the P well region (4) and the separated short-circuit anode structure respectively; The gate structure is a planar gate structure, comprising a planar gate polysilicon (7) and a field oxide layer (9); the field oxide layer (9) covers the upper surfaces of the N strips (8) and the first P strips (10), and one end of the field oxide layer (9) extends along the upper surface of the P well region (4) to the upper surface of a portion of the cathode N+ region (6), and the other end of the field oxide layer (9) extends along the upper surface of the N-type drift region (3) to the upper surface of a portion of the separated short-circuit anode structure; the planar gate polysilicon (7) is located on the upper surface of the field oxide layer (9), specifically extending from one end of the field oxide layer (9) located on the upper surface of the N+ region (6) to the other end of the field oxide layer (9) to the portion of the field oxide layer (9) located on the upper surface of the N strips (8) and the first P strips (10); a gate electrode is drawn out from the surface of the planar gate polysilicon (7); The anode structure comprises an N-type buffer layer (11), an anode P+ region (12), a second P strip (13) and an anode N+ region (14); the N-type buffer layer (11), the second P strip (13) and the anode N+ region (14) are arranged in parallel in sequence, and the N-type buffer layer (11) is located on a side close to the cathode structure, and the anode P+ region (12) is located on an upper layer inside the N-type buffer layer (11); the field oxide layer (9) covers a portion of the upper surface of the N-type buffer layer (11), but there is a gap between the field oxide layer (9) and the anode P+ region (12); the upper surfaces of the anode P+ region (12) and the anode N+ region (14) have a common lead end as an anode electrode.

2. A high-speed, low-loss lateral power device with a super junction structure according to claim 1, characterized in that: The widths of the N strips (8) and the first P strips (10) in the longitudinal direction are equal.

3. The high-speed, low-loss lateral power device with a super junction structure according to claim 1, characterized in that: The N strips (8) and the first P strips (10) are of a gradual structure, specifically, the width of the N strips (8) increases linearly from the side close to the cathode structure to the side close to the separated short-circuit anode structure, and the width of the first P strips (10) decreases linearly from the side close to the cathode structure to the side close to the separated short-circuit anode structure.

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