Garbage recycling method and device of storage device, medium and computer equipment

Abstract

The invention provides a garbage collection method and device for a storage device, a medium and computer equipment. The garbage collection method comprises the steps that a write-in command issued by a host and a GC operation command triggered by a system are cached through a cache actuator; the GC operation command is evaluated through a dynamic priority scoring model according to the invalid data proportion and the block wear proportion, the number of high-priority GC tasks can be adjusted through a dynamic adjustment coefficient of the dynamic priority scoring model, and bandwidth occupation of the GC operation command is restrained in a high-load scene. And the maximum bandwidth occupation of the GC operation command is kept in a low-load scene. The real-time bandwidth load of the I / O channel is monitored and processed, the execution number and the bandwidth occupancy rate of the high-priority GC tasks are cooperatively adjusted, the processing number of the high-priority tasks is considered, and the high load occupied by the resources of the GC tasks is effectively limited.

Description

Technical Field

[0001] The present invention relates to a garbage collection method, device, medium and computer device for a storage device, and belongs to the technical field of GC recovery methods for NandFlash. Background Art

[0002] Common storage media include various categories such as hard disk drives (HDDs), solid state drives (SSDs), USB flash drives, optical discs, etc. Among them, the core technologies of SSDs are Nand Flash and the main control chip. Nand Flash stores data through floating gate transistors, and compared with traditional hard disk drives, it has a significant improvement in random read and write speeds and outstanding physical properties (no mechanical components, strong earthquake resistance, low power consumption, no noise). The storage unit of Nand Flash is a floating gate transistor, and its physical characteristics determine the following limitations: Erasure is required before writing: The storage unit of Nand Flash can only change from 1 to 0, but the erasure operation will restore the entire block to the all-1 state. Therefore, if data needs to be updated on a page where data has already been written, the entire block needs to be erased first, and then the updated data needs to be rewritten. Minimum operation unit limitation: Writing is in units of pages (for example, 4KB), and erasure is in units of blocks (for example, 64 pages, a total of 256KB). If only 1 page of data needs to be modified, the valid data of the entire block needs to be migrated to a new block, and then the old block needs to be erased, which results in the inability to directly overwrite. Therefore, a large number of invalid data blocks will be generated in the storage module of Nand Flash with continuous write, delete and other operations. In order to reclaim the space occupied by these invalid data and improve storage utilization, garbage collection (GC) operations are required. When moving valid data to a new block, the storage space of the old block needs to be released again after erasing the old block. During the GC operation, operations such as data migration and erasure are usually involved, and these operations will occupy a certain amount of system resources and storage bandwidth, resulting in a significant decrease in write performance. In some application scenarios with high requirements for write performance, such as real-time data recording and high-speed data transmission, this decrease in write performance will seriously affect the overall performance of the system and lead to a decline in user experience.

[0003] Existing GC strategies are mostly triggered based on fixed thresholds (such as when the remaining space is insufficient) or periodically, resulting in competition for bandwidth between GC operations and host write commands, and a sharp drop in I / O throughput in high-load scenarios, even lower than the minimum performance requirements of the host. Summary of the Invention

[0004] Aiming at the deficiencies of the above-mentioned existing technologies, the purpose of the present invention is to provide a garbage collection method, device, medium and computer device for a storage device. According to an embodiment of the present invention, a first solution is provided: a garbage collection method for a storage device, including the following steps: Cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; Obtain the real-time bandwidth load of the I / O channel through a load monitoring module, obtain the write real-time bandwidth occupancy rate (B_host) and the total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and the block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command through a flash memory management unit; Evaluate the GC operation command through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation command in a high-load scenario, and maintain the maximum bandwidth occupancy of the GC operation command in a low-load scenario; Calculate the parallel gap execution window and the fragmented idle execution window available for the GC operation command according to the real-time bandwidth load of the I / O channel obtained by the load detection module; Granularize the high-priority GC task into the smallest operation unit instructions, incorporate the granularized smallest operation unit instructions into the cached write commands in the parallel gap execution window through a DMA controller to generate a first instruction, generate a second instruction for the low-priority GC task in the fragmented execution window through a background GC processor, and generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write commands; Send and execute the parallel instructions.

[0005] Furthermore, the process of evaluating through the dynamic priority scoring model includes: Calculate the invalid data ratio R_invalid of the data blocks to be recycled as: R_invalid = D_invalid / D_total, where D_invalid is the amount of invalid data in the data blocks to be recycled, and D_total is the total amount of data in the data blocks to be recycled; Calculate the block wear ratio W_ratio of the data blocks to be recycled as: W_ratio = W_current / W_max, where W_current is the number of erase times of the current data block, and W_max is the maximum allowable number of erase times of the current data block; The process of calculating the priority score by the dynamic priority scoring model includes: S_GC = ω_1·R_invalid + ω_2·(1 - W_ratio), where ω_1 and ω_2 are the first weight coefficient and the second weight coefficient respectively; When S_GC ≥ S_threshold, the GC operation command is evaluated as a high-priority GC task; when S_GC < S_threshold, the GC operation command is evaluated as a low-priority GC task, where S_threshold is a dynamically adjustable coefficient.

[0006] Furthermore, the calculation steps of the dynamically adjustable coefficient S_threshold include: Obtain the real-time bandwidth load of the I / O channel through the load monitoring module, and calculate the load coefficient for the real-time bandwidth load: S_load = α·B_host / B_total + β·ΔT / T_safe + γ·L_GC / L_max, where B_host is the real-time bandwidth occupancy rate, B_total is the total bandwidth, ΔT is the latency increment of the I / O channel, T_safe is the latency safety threshold, L_GC is the queue length of the GC operation commands in the cache, L_max is the maximum capacity of the queue of GC operation commands in the cache, α is the bandwidth calibration coefficient, β is the latency increment calibration coefficient, γ is the GC queue length calibration coefficient, and the sum of the three satisfies: α + β + γ = 1; When the load coefficient S_load is lower than 0.5, the real-time bandwidth load of the I / O channel is defined as low load; when the load coefficient S_load is greater than or equal to 0.5, the real-time bandwidth load of the I / O channel is defined as medium-high load; When the I / O channel is in medium-high load, S_threshold = S_base - κ·S_load; when the I / O channel is in low load, S_threshold = S_base, where S_base is the load base threshold and κ is the load sensitivity coefficient.

[0007] Furthermore, the steps to suppress the bandwidth occupancy of the GC operation command in a high-load scenario include: The bandwidth occupancy rate B_GC1 of the high-priority GC task = δ·(B_total - B_host), where δ is the high-bandwidth suppression coefficient, 0 < δ ≤ 1.

[0008] Furthermore, the steps to maintain the maximum bandwidth occupancy of the GC operation command in a low-load scenario include: The bandwidth occupancy rate B_GC2 of the low-priority GC task = ε·(B_total - B_host), where ε is 0.8.

[0009] Furthermore, the δ is dynamically adjusted according to the latency increment ΔT: When ΔT ≤ T_safe, δ = 0.8; when ΔT > T_safe, δ = 0.3.

[0010] Further, the δ is dynamically adjusted according to the delay increment ΔT and the throughput fluctuation σ: When ΔT ≤ 10ms and σ < 5%, δ = 0.8; When 10 < ΔT ≤ 20ms or 5% ≤ σ < 10%, δ = 0.5; When ΔT > 20ms or σ > 10%, δ = 0.3.

[0011] According to the embodiments of the present invention, using the garbage collection method of the storage device in the first solution provided by the present invention, the second solution is provided as follows: A garbage collection device for a storage device, comprising: A cache module, configured to cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; A load monitoring module, configured to obtain the real-time bandwidth load of the I / O channel, obtain the real-time bandwidth occupancy rate (B_host) and the total bandwidth (B_total) of the write commands according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and the block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation commands through a flash memory management unit; A GC operation processing module, configured to evaluate the GC operation commands through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation commands in high-load scenarios, and maintain the maximum bandwidth occupancy of the GC operation commands in low-load scenarios; A time window calculation module, configured to calculate the parallel gap execution window and the fragmented idle execution window available for the GC operation commands according to the real-time bandwidth load of the I / O channel obtained by the load detection module; A parallel instruction generation module, configured to granulate the high-priority GC tasks into the smallest operation unit instructions, incorporate the granulated smallest operation unit instructions into the cached write commands in the parallel gap execution window through a DMA controller to generate a first instruction, generate a second instruction for the low-priority GC tasks in the fragmented execution window through a background GC processor, and generate parallel instructions according to the execution order of the cached write commands for the first instruction and the second instruction; A parallel instruction execution module, configured to send and execute the parallel instructions.

[0012] A computer device includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor performs the following steps: Cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; Obtain the real-time bandwidth load of the I / O channel through a load monitoring module, obtain the write real-time bandwidth occupancy rate (B_host) and the total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and the block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command through a flash memory management unit; Evaluate the GC operation commands through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation commands in high-load scenarios, and maintain the maximum bandwidth occupancy of the GC operation commands in low-load scenarios; Calculate the parallel gap execution window and the fragmented idle execution window available for the GC operation commands according to the real-time bandwidth load of the I / O channel obtained by the load detection module; Granularize the high-priority GC tasks into the smallest operation unit instructions, incorporate the granularized smallest operation unit instructions into the cached write commands in the parallel gap execution window through a DMA controller to generate a first instruction, generate a second instruction for the low-priority GC tasks in the fragmented execution window through a background GC processor, and generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write commands; Send and execute the parallel instructions.

[0013] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the processor performs the following steps: Cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; Obtain the real-time bandwidth load of the I / O channel through a load monitoring module, obtain the write real-time bandwidth occupancy rate (B_host) and the total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and the block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command through a flash memory management unit; Evaluate the GC operation commands through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupation of GC operation commands in high-load scenarios, and maintain the maximum bandwidth occupation of GC operation commands in low-load scenarios; Calculate the parallel gap execution window and the fragmented idle execution window available for GC operation commands based on the real-time bandwidth load of the I / O channel obtained by the load detection module; Granularize the high-priority GC tasks into the smallest operation unit instructions. Incorporate the granularized smallest operation unit instructions into the write commands cached in the parallel gap execution window through the DMA controller to generate the first instruction. Generate the second instruction for the low-priority GC tasks in the fragmented execution window through the background GC processor. Generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write commands; Send and execute the parallel instructions.

[0014] Compared with the prior art, the beneficial effects of the independent claim of the technical solution provided by this application are: 1. Evaluate the GC operation commands cached through a dynamic priority scoring model, integrate the invalid data ratio and the block wear ratio, scientifically quantify the urgency of GC operation tasks, and preferentially recycle blocks with high returns or low wear. The so-called high returns include GC operation tasks with a large amount of space released, effectively improving the space recovery efficiency by 15% - 30% and extending the service life of the SSD hard disk by more than 10%; 2. Dynamically adjust the bandwidth occupation of GC operation commands, suppress the bandwidth occupation of GC operation commands in high-load scenarios, maximize the GC operation efficiency in low-load scenarios, and ensure that the write performance of write commands is always higher than the minimum requirements of the host; 3. The high-priority GC tasks perform single-page migration during the execution gap of the write commands through the DMA controller, reducing the intervention of the main control chip and reducing the latency increment to within 5 ms. The low-priority GC tasks are centrally processed by a dedicated GC processor in the idle execution window, avoiding blocking the I / O channel, and improving the bandwidth occupation rate by more than 20% through the collaborative execution of software and hardware; 4. By monitoring and processing the real-time bandwidth load of the I / O channel, coordinately adjust the execution quantity and bandwidth occupation rate of high-priority GC tasks, taking into account the processing quantity of high-priority tasks and effectively restricting the high load of resource occupation of GC tasks. Description of the Drawings

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0016] Wherein: Figure 1 It is a flowchart of the garbage collection method of the storage device in an embodiment; Figure 2 It is a structural block diagram of the garbage collection device of the storage device in an embodiment; Figure 3 It is a structural block diagram of a computer device in an embodiment. Detailed implementation manners

[0017] In order to enable those skilled in the art to better understand the technical solutions in this application, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0018] Embodiment 1 The technical problem solved in this embodiment is that existing GC strategies are mostly based on fixed thresholds (such as triggering when the remaining space is insufficient) or periodic triggering, resulting in competition for bandwidth between GC operations and host write commands, and a sharp drop in I / O throughput in high-load scenarios, even lower than the minimum performance requirements of the host.

[0019] For example, the conflict between GC operations and write performance: Traditional GC triggering mechanisms (such as fixed thresholds, periodic triggering) cannot dynamically adjust the priority of GC tasks according to real-time load, resulting in excessive bandwidth occupation by GC during high load and a sharp increase in write latency; Low resource utilization efficiency: Centralized GC operations (such as whole-block migration) occupy the continuous I / O channel time, exacerbating the write performance fluctuation; Insufficient block lifetime management: GC tasks are not dynamically allocated in combination with the wear state of the block, and frequent erasure of high-wear blocks may cause premature failure.

[0020] Therefore, this embodiment provides a garbage collection method for a storage device, including the steps of: S101: Cache the write commands issued by the host and the GC operation commands triggered by the system through the cache executor; Obtain the real-time bandwidth load of the I / O channel through the load monitoring module, and obtain the real-time bandwidth occupancy rate (B_host) and total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel. The flash management unit counts the invalid data ratio (R_invalid) and block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command; S102: Evaluate the GC operation command through the dynamic priority scoring model according to the invalid data ratio (R_invalid) and block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, and suppress the bandwidth occupancy of the GC operation command in high-load scenarios, and maintain the maximum bandwidth occupancy of the GC operation command in low-load scenarios; S103: Calculate the parallel gap execution window and fragmented idle execution window available for the GC operation command according to the real-time bandwidth load of the I / O channel obtained by the load detection module; S104: Granularize the high-priority GC task into the smallest operation unit instructions. The granularized smallest operation unit instructions are incorporated into the cached write command in the parallel gap execution window through the DMA controller to generate the first instruction. The low-priority GC task is generated into the second instruction in the fragmented execution window through the background GC processor. The first instruction and the second instruction are generated into parallel instructions according to the execution order of the cached write command; The working process of the DMA controller (Direct Memory Access Controller) includes: initialization, transfer start and completion notification.

[0021] S105: Send and execute the parallel instructions.

[0022] Specifically, the process of evaluating through the dynamic priority scoring model includes: calculating the invalid data ratio R_invalid of the data blocks to be recycled as: R_invalid = D_invalid / D_total, where D_invalid is the amount of invalid data of the data blocks to be recycled, and D_total is the total amount of data of the data blocks to be recycled; calculating the block wear ratio W_ratio of the data blocks to be recycled as: W_ratio = W_current / W_max, where W_current is the number of erasure times of the current data block, and W_max is the maximum allowable number of erasure times of the current data block; In the SSD calibration test, the flash memory management unit periodically scans the modules to be recycled, reads the valid page tags in the material block metadata, counts the amount of invalid data and the total amount of data, and updates the statistics of invalid pages through the L2P table every 10 ms. The wear leveling controller records the number of erase cycles of each block and combines it with the maximum number of erase cycles provided by the manufacturer (such as 10,000 times).

[0023] The process of calculating the priority score by the dynamic priority scoring model includes: S_GC = ω_1·R_invalid + ω_2·(1 - W_ratio), where ω_1 and ω_2 are the first weight coefficient and the second weight coefficient respectively; when S_GC ≥ S_threshold, the GC operation command is evaluated as a high-priority GC task, and when S_GC < S_threshold, the GC operation command is evaluated as a low-priority GC task, where S_threshold is a dynamic adjustment coefficient.

[0024] For example, S_GC = 0.6·R_invalid + 0.4·(1 - W_ratio). Through the SSD calibration test, when R_invalid ≥ 0.5 and W_ratio < 0.3, combining the first weight coefficient 0.6 and the second weight coefficient 0.4 can improve the space recycling efficiency by 25%.

[0025] Preferably, the dynamic adjustment coefficient S_threshold is 0.7. When S_GC ≥ 0.7, it is marked as a high-priority GC task, and when S_GC < 0.7, it is marked as a low-priority GC task.

[0026] Specifically, the calculation steps of the dynamic adjustment coefficient S_threshold include: obtaining the real-time bandwidth load of the I / O channel through the load monitoring module and calculating the load coefficient for the real-time bandwidth load: S_load = α·B_host / B_total + β·ΔT / T_safe + γ·L_GC / L_max, where B_host is the real-time bandwidth occupancy rate, B_total is the total bandwidth, ΔT is the delay increment of the I / O channel, T_safe is the delay safety threshold, L_GC is the queue length of the cached GC operation commands, L_max is the maximum capacity of the queue of the cached GC operation commands, α is the bandwidth calibration coefficient, β is the delay increment calibration coefficient, γ is the GC queue length calibration coefficient, and the three satisfy: α + β + γ = 1; When the load factor S_load is lower than 0.5, the real-time bandwidth load of the I / O channel is defined as low load. When the load factor S_load is greater than or equal to 0.5, the real-time bandwidth load of the I / O channel is defined as medium-high load. When the I / O channel is in medium-high load, S_threshold = S_base - κ·S_load. When the I / O channel is in low load, S_threshold = S_base, where S_base is the load base threshold and κ is the load sensitivity coefficient.

[0027] For example, S_load = 0.5·B_host / B_total + 0.3·ΔT / T_safe + 0.2·L_GC / L_max. In the SSD calibration experiment, when S_load ≥ 0.5, the real-time bandwidth load of the I / O channel is defined as medium-high load and dynamic threshold adjustment is triggered. When S_load is less than 0.5, the real-time bandwidth load of the I / O channel is defined as low load.

[0028] Specifically, the steps to suppress the bandwidth occupancy of the GC operation command in the high-load scenario include: the bandwidth occupancy rate of the high-priority GC task B_GC1 = δ·(B_total - B_host), where δ is the high-bandwidth suppression coefficient and 0 < δ ≤ 1.

[0029] The bandwidth suppression logic is that when the high-priority GC task is executing, if the real-time bandwidth load of the I / O channel is high load, the high-bandwidth suppression coefficient is very small. The high-load judgment basis usually includes the increase in the delay increment of the I / O channel. When it exceeds the safety threshold, the high-bandwidth suppression coefficient is adjusted smaller, so that although the number of high-priority GC tasks is large, the priority execution of the write command must also be ensured. The DMA controller seamlessly switches the write command and the high-priority GC task through the double-buffer mechanism, and the delay increment is controlled within 5 ms.

[0030] Specifically, the steps to maintain the maximum bandwidth occupancy of the GC operation command in the low-load scenario include: the bandwidth occupancy rate of the low-priority GC task B_GC2 = ε·(B_total - B_host), where ε is 0.8.

[0031] The bandwidth acceleration logic is that when the low-priority GC task is executing, if the real-time bandwidth load of the I / O channel is low load, the low-bandwidth suppression coefficient is increased. The low-load judgment basis usually includes the decrease in the delay increment of the I / O channel. The execution efficiency of the low-priority GC task is accelerated through the background GC task processor. For example, when it is detected that the real-time bandwidth occupancy rate B_host ≤ B_total, an asynchronous thread is started to erase the whole block (in units of 256 KB), and the real-time bandwidth utilization rate is increased from 60% to 80% without write performance fluctuations.

[0032] Specifically, the δ is dynamically adjusted according to the delay increment ΔT: when ΔT ≤ T_safe, δ = 0.8; when ΔT > T_safe, δ = 0.3.

[0033] When considering throughput fluctuations, the δ is dynamically adjusted according to the delay increment ΔT and the throughput fluctuation σ: when ΔT ≤ 10 ms and σ < 5%, δ = 0.8; when 10 < ΔT ≤ 20 ms or 5% ≤ σ < 10%, δ = 0.5; when ΔT > 20 ms or σ > 10%, δ = 0.3.

[0034] 1. Evaluate the cached GC operation commands through a dynamic priority scoring model, integrate the proportion of invalid data and the block wear proportion, scientifically quantify the urgency of the GC operation tasks, and preferentially recycle high-yield or low-wear blocks. The so-called high yield includes GC operation tasks with a large amount of space released, effectively improving the space recovery efficiency by 15% - 30% and extending the service life of the SSD hard disk by more than 10%; 2. Dynamically adjust the bandwidth occupation of the GC operation commands, suppress the bandwidth occupation of the GC operation commands in high-load scenarios, maximize the GC operation efficiency in low-load scenarios, and ensure that the writing performance of the write commands is always higher than the minimum requirements of the host; 3. High-priority GC tasks perform single-page migration during the execution gap of write commands through the DMA controller, reducing the intervention of the main control chip and reducing the delay increment to within 5 ms. Low-priority GC tasks are centrally processed by a dedicated GC processor in the idle execution window to avoid blocking the I / O channel, and the bandwidth occupation rate is increased by more than 20% through the collaborative execution of software and hardware; 4. By monitoring and processing the real-time bandwidth load of the I / O channel, coordinately adjust the execution quantity and bandwidth occupation rate of high-priority GC tasks, taking into account the processing quantity of high-priority tasks and effectively limiting the high load of resource occupation by GC tasks.

[0035] 5. In high-load scenarios, the bandwidth of the GC task is limited to 0.04B_total, and the number of invalid blocks recycled per hour is increased by 30%. In low-load scenarios, the whole-block erasure speed is increased by 50%, and the standard deviation of block wear balance drops from 15% to 8%.

[0036] Embodiment 2 As Figure 2 shown, a garbage collection device for a storage device includes: A cache module 100, configured to cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; The load monitoring module 200 is used to obtain the real-time bandwidth load of the I / O channel, obtain the real-time bandwidth occupancy rate (B_host) and the total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and the block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command through the flash memory management unit; The GC operation processing module 300 is used to evaluate the GC operation command through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation command in a high-load scenario, and maintain the maximum bandwidth occupancy of the GC operation command in a low-load scenario; The time window calculation module 400 is used to calculate the parallel gap execution window and the fragmented idle execution window available for the GC operation command according to the real-time bandwidth load of the I / O channel obtained by the load detection module; The parallel instruction generation module 500 is used to granulate the high-priority GC task into the smallest operation unit instructions, incorporate the granulated smallest operation unit instructions into the cached write command in the parallel gap execution window through the DMA controller to generate the first instruction, generate the second instruction for the low-priority GC task in the fragmented execution window through the background GC processor, and generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write command; The parallel instruction execution module 600 is used to send and execute the parallel instructions.

[0037] Embodiment 4 Figure 3 shows the internal structure diagram of a computer device in an embodiment. The computer device may specifically be a terminal or a server. As Figure 3 shown, the computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement the garbage collection method of the storage device. The memory may also store a computer program. When the computer program is executed by the processor, the processor can execute the garbage collection method of the storage device. Those skilled in the art can understand, Figure 3The structure shown is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0038] In one embodiment, a computer device is proposed, including a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor is caused to perform the following steps: Cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; Obtain the real-time bandwidth load of the I / O channel through a load monitoring module, obtain the real-time bandwidth occupancy rate (B_host) and total bandwidth (B_total) of the write commands according to the real-time bandwidth load of the I / O channel, and count the invalid data ratio (R_invalid) and block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation commands through a flash memory management unit; Evaluate the GC operation commands through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, and suppress the bandwidth occupancy of the GC operation commands in high-load scenarios and maintain the maximum bandwidth occupancy of the GC operation commands in low-load scenarios; Calculate the parallel gap execution window and fragmented idle execution window available for the GC operation commands according to the real-time bandwidth load of the I / O channel obtained by the load detection module; Granularize the high-priority GC tasks into the smallest operation unit instructions, incorporate the granularized smallest operation unit instructions into the cached write commands in the parallel gap execution window through a DMA controller to generate a first instruction, generate a second instruction for the low-priority GC tasks in the fragmented execution window through a background GC processor, and generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write commands; Send and execute the parallel instructions.

[0039] In one embodiment, a computer-readable storage medium is proposed, storing a computer program. When the computer program is executed by a processor, the processor is caused to perform the following steps: Cache the write commands issued by the host and the GC operation commands triggered by the system through a cache executor; Obtain the real-time bandwidth load of the I / O channel through the load monitoring module, and obtain the real-time bandwidth occupancy rate (B_host) and total bandwidth (B_total) of the write command according to the real-time bandwidth load of the I / O channel. The flash management unit counts the invalid data ratio (R_invalid) and block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation command; Evaluate the GC operation command through the dynamic priority scoring model according to the invalid data ratio (R_invalid) and block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation command in high-load scenarios, and maintain the maximum bandwidth occupancy of the GC operation command in low-load scenarios; Calculate the parallel gap execution window and fragmented idle execution window available for the GC operation command according to the real-time bandwidth load of the I / O channel obtained by the load detection module; Granularize the high-priority GC task into the smallest operation unit instructions. Through the DMA controller, incorporate the granularized smallest operation unit instructions into the cached write command in the parallel gap execution window and generate the first instruction. Through the background GC processor, generate the second instruction for the low-priority GC task in the fragmented execution window, and generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write command; Send and execute the parallel instructions.

[0040] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0041] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0042] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A garbage collection method for a storage device, characterized in that It includes the following steps: Cache the write commands sent by the host and the GC operation commands triggered by the system through the cache executor; Obtain the real-time bandwidth load of the I / O channel through the load monitoring module, and obtain the real-time bandwidth occupancy rate (B_host) and total bandwidth (B_total) of the write commands according to the real-time bandwidth load of the I / O channel. The flash management unit counts the invalid data ratio (R_invalid) and block wear ratio (W_ratio) of the data blocks to be recycled in the GC operation commands; Evaluate the GC operation commands through the dynamic priority scoring model according to the invalid data ratio (R_invalid) and block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, and suppress the bandwidth occupancy of the GC operation commands in high-load scenarios and maintain the maximum bandwidth occupancy of the GC operation commands in low-load scenarios; Calculate the parallel gap execution window and fragmented idle execution window available for the GC operation commands based on the real-time bandwidth load of the I / O channel obtained by the load detection module; The unit instruction granulates the high-priority GC tasks into the smallest operation unit instructions during the parallel gap, incorporates the granulated smallest operation execution window into the cached write commands through the DMA controller to generate the first instruction, and generates the second instruction for the low-priority GC tasks in the fragmented execution window through the background GC processor. Generate parallel instructions for the first instruction and the second instruction according to the execution order of the cached write commands; Send and execute the parallel instructions.

2. The garbage collection method of the storage device according to claim 1, wherein The process of evaluating by the dynamic priority scoring model includes: Calculate the invalid data ratio R_invalid of the data blocks to be recycled as: R_invalid = D_invalid / D_total, where D_invalid is the amount of invalid data in the data blocks to be recycled, and D_total is the total amount of data in the data blocks to be recycled; Calculate the block wear ratio W_ratio of the data blocks to be recycled as: W_ratio = W_current / W_max, where W_current is the number of erase times of the current data block, and W_max is the maximum allowable number of erase times of the current data block; The process of calculating the priority score by the dynamic priority scoring model includes: S_GC = ω_1·R_invalid + ω_2·(1 - W_ratio), where ω_1 and ω_2 are the first weight coefficient and the second weight coefficient respectively; When S_GC ≥ S_threshold, evaluate the GC operation command as a high-priority GC task, and when S_GC < S_threshold, evaluate the GC operation command as a low-priority GC task, where S_threshold is the dynamic adjustment coefficient.

3. The garbage collection method of the storage device according to claim 2, characterized in that, The calculation steps of the dynamic adjustment coefficient S_threshold include: Obtain the real-time bandwidth load of the I / O channel through the load monitoring module, and calculate the load coefficient for the real-time bandwidth load: S_load = α·B_host / B_total + β·ΔT / T_safe + γ·L_GC / L_max, where B_host is the real-time bandwidth occupancy rate, B_total is the total bandwidth, ΔT is the latency increment of the I / O channel, T_safe is the latency safety threshold, L_GC is the queue length of the GC operation commands in the cache, L_max is the maximum queue capacity of the GC operation commands in the cache, α is the bandwidth calibration coefficient, β is the latency increment calibration coefficient, γ is the GC queue length calibration coefficient, and the three satisfy: α + β + γ = 1; When the load factor S_load is lower than 0.5, the real-time bandwidth load of the I / O channel is defined as low load, and when the load factor S_load is greater than or equal to 0.5, the real-time bandwidth load of the I / O channel is defined as medium-high load; When the I / O channel is in medium-high load, S_threshold = S_base - κ·S_load, and when the I / O channel is in low load, S_threshold = S_base, where S_base is the load base threshold and κ is the load sensitivity coefficient.

4. The garbage collection method of the storage device according to claim 3, wherein The steps to suppress the bandwidth occupancy of GC operation commands in high-load scenarios include: The bandwidth occupancy rate of high-priority GC tasks B_GC1 = δ·(B_total - B_host), where δ is the high-bandwidth suppression coefficient, 0 < δ ≤ 1.

5. The garbage collection method of the storage device according to claim 4, wherein The steps to maintain the maximum bandwidth occupancy of GC operation commands in low-load scenarios include: The bandwidth occupancy rate of low-priority GC tasks B_GC2 = ε·(B_total - B_host), where ε is 0.

8.

6. The garbage collection method of the storage device according to claim 5, wherein The δ is dynamically adjusted according to the latency increment ΔT: When ΔT ≤ T_safe, δ = 0.8, and when ΔT > T_safe, δ = 0.

3.

7. The garbage collection method of the storage device according to claim 4, characterized in that, The δ is dynamically adjusted according to the latency increment ΔT and the throughput fluctuation σ: When ΔT ≤ 10ms and σ < 5%, δ = 0.8; When 10 < ΔT ≤ 20ms or 5% ≤ σ < 10%, δ = 0.5; When ΔT > 20ms or σ > 10%, δ = 0.

3.

8. A garbage collection device for a storage device, characterized in that, Include: A cache module for caching the write commands sent by the host and the GC operation commands triggered by the system through a cache executor; A load monitoring module for obtaining the real-time bandwidth load of the I / O channel, obtaining the real-time bandwidth occupancy rate (B_host) and total bandwidth (B_total) of the write commands according to the real-time bandwidth load of the I / O channel, and statistically calculating the invalid data ratio (R_invalid) and block wear ratio (W_ratio) of the data blocks to be recycled of the GC operation commands through a flash memory management unit; The GC operation processing module is used to evaluate the GC operation command through a dynamic priority scoring model according to the invalid data ratio (R_invalid) and the block wear ratio (W_ratio), and output high-priority GC tasks and low-priority GC tasks. The dynamic adjustment coefficient of the dynamic priority scoring model can adjust the number of high-priority GC tasks, suppress the bandwidth occupancy of the GC operation command in high-load scenarios, and maintain the maximum bandwidth occupancy of the GC operation command in low-load scenarios; The time window calculation module is used to calculate the parallel gap execution window and the fragmented idle execution window available for the GC operation command through the real-time bandwidth load of the I / O channel obtained by the load detection module; The parallel instruction generation module is used to granulate the high-priority GC task into the smallest operation unit instructions, incorporate the granulated smallest operation unit instructions into the write command cached in the parallel gap execution window through the DMA controller and generate the first instruction, generate the second instruction for the low-priority GC task in the fragmented execution window through the background GC processor, and generate parallel instructions from the first instruction and the second instruction according to the execution order of the write command cached; The parallel instruction execution module is used to send and execute the parallel instructions.

9. A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 7.

10. A computer device includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 7.

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