LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with asymmetric stepped field oxide

Abstract

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with asymmetric stepped field oxide. The field oxide structure of the LDMOS device is in an asymmetric step shape, asymmetric coordinated regulation and control of the STI thickness are achieved, the step side expands the field oxide boundary through the gradient, electric field concentration at the STI corner is weakened, breakdown voltage is improved, the inclination angle of the non-step side keeps a thick field oxide area, the electric field peak of the source side is restrained, avalanche breakdown is delayed, and the device performance is improved. And meanwhile, the hot carrier injection risk is reduced. The structure gives consideration to the collaborative optimization of the breakdown capability and the conduction efficiency, is especially suitable for a high-voltage BCD platform with low loss and high reliability requirements, and is a structural innovation scheme with high process compatibility and high design flexibility.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to an LDMOS device with an asymmetric stepped field oxide. Background Art

[0002] With the development of integrated circuit technology in the post-Moore era, the industry has put forward higher requirements for system integration, energy efficiency ratio and chip area. The evolution of integrated circuits has gradually shifted from "size scaling" to "function integration". Under this background, power integrated circuits (Power IC) are widely used in multiple fields such as power management, motor drive, automotive electronics, and communication terminals, becoming the core foundation to support modern electronic systems. And BCD (Bipolar-CMOS-DMOS) technology, as the most representative single-chip power system platform at present, has become the mainstream solution by virtue of its ability to integrate bipolar junction transistors (BJTs), complementary metal oxide semiconductors (CMOS), and diffused power MOSFETs (DMOS) simultaneously.

[0003] In the BCD process system, the lateral double-diffused metal oxide semiconductor field effect transistor LDMOS (Lateral Double-Diffused MOSFET) is a typical high-voltage power device structure, with high breakdown voltage, low on-resistance, and good thermal stability. The LDMOS device forms a channel structure through lateral diffusion, and its source, drain, and gate are all located on the silicon wafer surface, facilitating coplanar integration with other devices. This device not only has a high input impedance and is suitable for high-current drive applications, but also has a negative temperature coefficient characteristic, with good current sharing ability at high temperatures, further enhancing its thermal reliability and service life.

[0004] To further improve the integration density and size control ability of power devices, modern BCD platforms widely adopt shallow trench isolation (STI) technology to replace the traditional LOCOS isolation process. The STI structure realizes electrical isolation by deeply etching trenches and filling oxides, and has excellent planarization and boundary control capabilities. As the key and difficult point of device design in BCD technology, and STI technology being the widely adopted key isolation process in modern BCD platforms, it is of great economic significance to study how to develop a stable STI-LDMOS process.

[0005] How to balance the off-state breakdown voltage and on-state conduction resistance of LDMOS is a difficult point in the research and development of LDMOS devices. The traditional LDMOS structure relies on a drift region with a lower doping concentration to bear the voltage. The lower doping concentration means a decrease in the number of carriers, resulting in an increase in resistivity, a larger conduction resistance, and a smaller conduction current. If one wants to reduce the conduction resistance, the doping concentration of the drift region needs to be increased, which in turn leads to an increase in the peak value of the internal electric field of the device when under off-state voltage, resulting in a decrease in the off-state breakdown voltage. In addition, after introducing STI into the LDMOS structure, a series of key problems are also caused: The interface structure between the STI oxide and silicon is relatively complex. Especially at the junction of the STI and the drift region or the channel region, due to the differences in the dielectric constant and thermal expansion coefficient of the materials, it is easy to cause the electric field to concentrate violently at the STI corner, forming a local high-field region, which seriously affects the breakdown voltage and reliability of the device. At the same time, the stress in the STI region may also cause a decrease in the channel mobility, resulting in an increase in the conduction resistance of the device. In addition, the traditional STI structure has a fixed vertical boundary, which is not conducive to the lateral buffering and spatial redistribution of the electric field, and local breakdown phenomena are particularly likely to occur under high-voltage working conditions.

[0006] Existing studies have tried to optimize the electric field distribution by introducing field plate structures, segmented doping control, or local implantation, etc. However, it often causes a significant increase in the conduction resistance while increasing the breakdown voltage, and it is difficult to balance the trade-off between the conduction performance and the breakdown voltage characteristics at the same time. Therefore, there is an irreconcilable contradiction between the on-state conduction resistance and the off-state breakdown voltage of traditional LDMOS. When developing the device, a choice has to be made between the two, and this contradiction can only be solved through the research and development of a new LDMOS device structure. Summary of the Invention

[0007] The purpose of the present invention is to overcome the deficiencies of the above-mentioned existing technologies and provide an LDMOS device with an asymmetric stepped field oxide structure.

[0008] The LDMOS device of the present invention with an asymmetric stepped field oxide structure includes: A substrate; A gate formed above the substrate; A drift region and a first well region are respectively formed on both sides of the substrate, and there is a distance between the first well region and the drift region; A second well region formed in the drift region; A body region formed in the first well region; An asymmetric stepped field oxide structure formed in the drift region; A drain formed in the second well region; A source and a body electrode formed in the body region.

[0009] Preferably, a gate oxide layer is formed between the gate and the substrate; sidewalls are formed on both sides of the gate.

[0010] Preferably, the doping concentration of the second well region is less than that of the first well region.

[0011] Preferably, the asymmetric stepped field oxide structure extends to a partial top region of the second well region and a region other than the second well region.

[0012] Preferably, the drain is close to the asymmetric stepped field oxide structure; the body electrode is located outside the source electrode, and the two are short-circuited.

[0013] Preferably, the side of the asymmetric stepped field oxide structure facing the second well region is an inverted stepped structure, and the side facing the first well region is a non-stepped structure.

[0014] More preferably, the side of the asymmetric stepped field oxide structure facing the second well region is a two-layer stepped structure; the top angle of the side facing the first well region is less than 90 degrees.

[0015] Preferably, the asymmetric stepped field oxide structure is an integrally formed structure, including a bottom trapezoidal structure and a top trapezoidal structure arranged from bottom to top; the sidewall of the bottom trapezoidal structure facing the first well region and the sidewall of the top trapezoidal structure facing the first well region are on the same straight line; the lower end of the top trapezoidal structure is connected to the upper end of the bottom trapezoidal structure, and the length of the lower end of the top trapezoidal structure is greater than that of the upper end of the bottom trapezoidal structure.

[0016] More preferably, the thickness of the top trapezoidal structure is thicker than that of the bottom trapezoidal structure.

[0017] Preferably, one end of the gate is located above a partial region of the asymmetric stepped field oxide structure, and the other end is located above a partial region of the body region.

[0018] The beneficial effects of the present invention at least include: In the LDMOS device of the present invention, the field oxide structure adopts an asymmetric stepped shape to realize the asymmetric cooperative regulation of the STI thickness. The stepped side extends the field oxide boundary through gradient, weakens the electric field concentration at the STI corner, and improves the breakdown voltage (BV). The inclined angle of the non-stepped side retains the thick field oxide region, suppresses the electric field peak on the source side, delays the avalanche breakdown, and reduces the risk of hot carrier injection (HCI) at the same time.

[0019] Through the cooperative design of the field oxide thickness and the doping concentration, the present invention realizes the uniform distribution of the electric field in the drift region, shortens the conduction path, and improves the figure of merit of power.

[0020] The present invention introduces SSTI (bottom trapezoidal structure) with the same inclination angle in the thick field oxide region near the first well region, so that the morphology of the entire field oxide is a thickened and inclined STI segment near the first well region, and the thick field oxide region near the second well region is a reserved thinner STI segment, realizing the asymmetric collaborative regulation of the STI thickness, effectively delaying the position of the high electric field concentration region, realizing the gradient broadening and distribution balance of the electric field in the drift region, and significantly suppressing the electric field spike at the STI corner on the source side. In terms of device electrical properties, while maintaining or slightly increasing the breakdown voltage (BV), this structure significantly reduces the increasing trend of the specific on-resistance (Rsp) caused by the thick STI, and improves the figure of merit (FOM) of the device power performance. This structure takes into account the collaborative optimization of the breakdown ability and the conduction efficiency, and is particularly suitable for high-voltage BCD platforms that require both low loss and high reliability. It is a structural innovation solution with strong process compatibility and high design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic structural diagram of an LDMOS device (denoted as leftsti) with an asymmetric stepped field oxide structure provided by an embodiment of the present invention.

[0023] Figure 2 It is a schematic structural diagram of an LDMOS device (denoted as basesti) with a thin trapezoidal field oxide structure.

[0024] Figure 3 It is a schematic structural diagram of an LDMOS device (denoted as basesti1) with a thick trapezoidal field oxide structure.

[0025] Figure 4 It is the manufacturing process flow of the LDMOS device leftsti.

[0026] Figure 5 It is the BV breakdown characteristic curves of three different field oxide structure LDMOS devices (leftsti, basesti, basesti1).

[0027] Figure 6 It is the Id–Vds conduction characteristic curves of three different field oxide structure LDMOS devices (leftsti, basesti, basesti1).

[0028] Figure 7It is the impact ionization rate distribution diagram of the LDMOS device (leftsti).

[0029] Figure 8 It is the impact ionization rate distribution diagram of the LDMOS device (basesti).

[0030] Figure 9 It is the impact ionization rate distribution diagram of the LDMOS device (basesti1).

[0031] Figure 10 It is the electric field strength distribution diagram of the LDMOS device (leftsti).

[0032] Figure 11 It is the electric field strength distribution diagram of the LDMOS device (basesti).

[0033] Figure 12 It is the electric field strength distribution diagram of the LDMOS device (basesti1).

[0034] Figure 13 It is a schematic diagram of the electric field strength curve intercepted along the X direction of the device at Y = 0.387um of the LDMOS device (leftsti).

[0035] Figure 14 It is a schematic diagram of the electric field strength curve intercepted along the X direction of the device at Y = 0.387um of the LDMOS device (basesti).

[0036] Figure 15 It is a schematic diagram of the electric field strength curve intercepted along the X direction of the device at Y = 0.387um of the LDMOS device (basesti1).

[0037] Figure 16 It is the electric field strength curve intercepted along the X direction of the device at Y = 0.387um of three different field-oxide structure LDMOS devices (leftsti, basesti, basesti1).

[0038] Markings in the figure: 1. Substrate; 2. Drift region; 3. Asymmetric stepped field-oxide structure; 3-1. Top trapezoidal structure; 3-2. Bottom trapezoidal structure; 4. First well region; 5. Second well region; 6. Gate oxide layer; 7. Gate; 8. Body region; 9. Sidewall; 10. Source; 11. Drain; 12. Body terminal. Specific implementation mode

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] Such as Figure 1As shown in the figure, an LDMOS device with an asymmetric stepped field oxide structure provided by an embodiment of the present invention, denoted as leftsti, is used to solve the contradiction that when the STI thickness is increased to improve the off-state breakdown voltage of STI LDMOS, the on-resistance will be greatly increased. It includes: Substrate 1; Gate 7, the gate 7 is formed above the substrate 1, and a gate oxide layer 6 is formed between the gate 7 and the substrate 1; sidewalls 9 are respectively formed on both sides of the gate 7; A drift region 2 is formed on one side of the substrate 1, and a first well region 4 is formed on the other side, and there is a distance between the first well region 4 and the drift region 2; A second well region 5 is formed at the outer end inside the drift region 2, and the doping concentration of the second well region 5 is less than that of the first well region 4; A body region is formed at the outer end inside the first well region 4; An asymmetric stepped field oxide structure 3 is formed at the top inside the drift region 2, and the asymmetric stepped field oxide structure 3 extends to a part of the top region of the second well region 5; A drain 11 is provided at the outer end of the top of the second well region 5; A source 10 and a body electrode 12 are further provided at the top of the body region, and the body electrode 12 is located outside the source 10, and the two are usually short-circuited.

[0041] In one embodiment, the side of the asymmetric stepped field oxide structure 3 facing the second well region 5 is an inverted stepped structure, and the side facing the first well region 4 is a non-stepped structure.

[0042] In one embodiment, the side of the asymmetric stepped field oxide structure 3 facing the second well region 5 is a two-layer stepped structure; the top angle of the side facing the first well region 4 is less than 90 degrees.

[0043] As an example, the asymmetric stepped field oxide structure 3 is an integrally formed structure, including a bottom trapezoidal structure 3-2 and a top trapezoidal structure 3-1 arranged from bottom to top; the sidewall of the bottom trapezoidal structure 3-2 facing the first well region 4 and the sidewall of the top trapezoidal structure 3-1 facing the first well region 4 are on the same straight line; the lower end of the top trapezoidal structure 3-1 is connected to the upper end of the bottom trapezoidal structure 3-2, and the length L1 of the lower end of the top trapezoidal structure 3-1 is greater than the upper end L2 of the bottom trapezoidal structure 3-2. For example, L1 = 3.7um and L2 = 1.5um.

[0044] More specifically, the thickness of the top trapezoidal structure 3-1 is greater than that of the bottom trapezoidal structure 3-2. In one embodiment, the thickness ratio of the top trapezoidal structure 3-1 to the bottom trapezoidal structure 3-2 is about 4:1. For example, the thickness of the top trapezoidal structure 3-1 is greater than 0.3 microns.

[0045] In one embodiment, one end of the gate 7 is located above a partial area of the asymmetric stepped field oxide structure 3, and the other end is located above a partial area of the body region.

[0046] This embodiment also provides a manufacturing process for the LDMOS device leftsti. See Appendix Figure 4 including: 1. Doping the substrate 1; 2. Doping the drift region 2 on the doped substrate 1 (for example, N-type doping to form the N-type drift region 2); 3. Forming the asymmetric stepped field oxide structure 3 (i.e., shallow trench isolation) by etching in two steps: In the first step, first etch to form the top trapezoidal structure in the asymmetric stepped field oxide structure, and then further etch to form the bottom trapezoidal structure on this basis by adding an SSTI mask; 4. Doping to form a first well region 4 with a slightly higher doping concentration (for example, a P-type Well region) and a second well region 5 (for example, an N-type Well region with a slightly higher doping concentration); 5. Growing the gate oxide layer 6; 6. Depositing a layer of polysilicon, etching to form the gate 7, and a part of the raised portion of the gate 7 can be polished flat by CMP (chemical mechanical polishing); 7. Doping to form a body region 8 with a slightly higher doping concentration (for example, a P-type body region); 8. Forming the sidewall 9; 9. Doping to form the source 10, drain 11, and body electrode 12.

[0047] Meanwhile, this embodiment also sets up a comparison structure: an LDMOS device with a thin trapezoidal field oxide structure, denoted as basesti; an LDMOS device with a thick trapezoidal field oxide structure, denoted as basesti1; Compared with the leftsti device of this embodiment, the field oxide structure of the basesti device adopts an isosceles trapezoidal structure with the thickness h1 of the top trapezoidal structure. See Appendix Figure 2 . The field oxide structure of the basesti1 device adopts an isosceles trapezoidal structure with the thickness h1 of the top trapezoidal structure + the thickness h2 of the bottom trapezoidal structure. See Appendix Figure 3 . The top angles of the field oxide structures of the basesti device and the basesti1 device are both α, where α < 90°, and it can be 80°.

[0048] Analysis of the breakdown conduction characteristics advantages of three types of devices: 1. The breakdown capability of leftsti devices is significantly improved compared with basesti devices, and the conduction performance is moderately controllable: like Figure 5 As shown in the BV curve, under the same doping conditions, the breakdown voltage of leftsti reaches 112 V (red line), which is about 8 V higher than that of basesti (about 104 V (green line). Figure 10 and electric field distribution Figure 11 The comparison shows that the bottom trapezoidal structure of leftsti effectively moves the electric field concentration area backward, reduces the peak electric field at the gate edge, and thus delays the occurrence of avalanche breakdown. Figure 7 It also shows that the high ionization region of leftsti shifts more obviously to the right, which delays the ionization start position, is beneficial to improving the breakdown capability and can effectively reduce the risk of hot carrier injection (HCI).

[0049] At the same time, through the Id-Vds curve ( Figure 6 ) It can be seen that under the same drain-source voltage Vds condition, the drain current Ids (red line) of leftsti is lower than that of basesti (green line), indicating that the on-resistance is slightly increased. However, the substantial increase in the breakdown voltage BV far exceeds the slight degradation of the on-resistance (Rsp), which ultimately greatly increases the power figure of merit FOM of leftsti from about 144.2 to 154.3, achieving an overall performance gain. It can be seen that its comprehensive optimization effect is obvious.

[0050] 2. Compared with basesti1 devices, leftsti devices can maintain breakdown voltage and significantly reduce conduction losses: See also Figure 5 , the breakdown voltage BV of leftsti and basesti1 (the red line and the blue line basically overlap) are both around 112V, indicating that the same thickness on the left side of the field oxygen structure can maintain equivalent breakdown performance. That is, only the bottom trapezoidal structure can meet the electric field suppression requirements, and the right side of the bottom trapezoidal structure has limited contribution to the breakdown voltage. Compared with basesti1, leftsti can still effectively regulate the electric field distribution because it retains the thickness and angle structure of the STI on the left side of the bottom trapezoidal structure. From the electric field distribution diagram ( Figure 10 , Figure 12), it can be observed that both leftsti and basesti1 exhibit obvious characteristics of weakened electric fields in the source STI corner region. Although the right side of the trapezoidal structure at the bottom of leftsti lacks a part of SSTI, the thick STI structure with an inclined angle is still retained on its left side, which is sufficient to undertake the control function of the high-electric-field region, keeping the electric field distribution at a level similar to that of basesti1 without significant spikes. The impact ionization rate graph ( Figures 7 - 9 ) further corroborates this. The distributions of the high-ionization-rate regions of both are almost the same in the breakdown state (the darker red parts), especially in the middle of the drift region and near the source STI corner where the ionization intensities are comparable. This indicates that although the leftsti structure is geometrically simplified, its electric field control ability has not decreased, and it can still support an approximate breakdown path and ionization expansion.

[0051] From Figure 6 the Id-Vd curve, it can be seen that the Ids current of leftsti is higher than that of basesti1 (the red line is higher than the blue line), indicating a lower on-resistance (Rsp). This benefits from the shortening of the current path during device conduction due to the missing part on the right side of the trapezoidal structure at the bottom of leftsti. The electric field intensity distribution graph intercepted at Y = 0.387um ( Figure 16 ) can further verify that the electric field of the missing part of SSTI on the right side of the trapezoidal structure at the bottom of leftsti drops to be basically the same as that of basesti with a thinner STI, significantly reducing the current suppression effect and thus maintaining a higher conduction ability. Leftsti also has the same BV as basesti1, but its conduction performance is significantly improved, enabling a greater improvement space for FOM (BV² / Rsp). Figures 13 - 15 is a schematic diagram of the electric field intensity curves along the X direction of the device intercepted at Y = 0.387um for the three devices leftsti, basesti, and basesti1.

[0052] Compared with the traditional symmetric STI structure, leftsti adopts an asymmetric stepped STI design. While retaining the left-side thickness and angled STI to ensure the electric field relaxation effect, it omits part of the STI on the right side to reduce the resistance of the conduction path. The simulation results show that compared with the thinner STI structure (basesti), leftsti can effectively suppress electric field concentration and reduce the impact ionization rate at the tip of the drift region, increasing the device breakdown voltage by about 9V and significantly improving FOM; while compared with the thicker STI structure (basesti1), leftsti significantly reduces the on-resistance while maintaining a similar breakdown voltage, improving the conduction efficiency. While taking into account the breakdown characteristics and conduction performance, this structure also has a better ability to regulate the electric field distribution, meeting the integration requirements for both power device performance and reliability in the high-voltage BCD platform.

[0053] Table 1: Comparison of Characteristics of Three Types of Devices

[0054] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. An LDMOS device with an asymmetric stepped field oxide structure, characterized in that, The LDMOS device includes: a substrate (1); a gate (7) formed above the substrate (1); a drift region (2) and a first well region (4) formed on both sides of the substrate (1) respectively, and there is a distance between the first well region (4) and the drift region (2); a second well region (5) formed in the drift region (2); a body region (8) formed in the first well region (4); an asymmetric stepped field oxide structure (3) formed in the drift region (2); a drain (11) formed in the second well region (5); a source (10) and a body electrode (12) formed in the body region (8).

2. The LDMOS device according to claim 1, wherein A gate oxide layer (6) is formed between the gate (7) and the substrate (1); sidewalls (9) are formed on both sides of the gate (7).

3. The LDMOS device according to claim 1, wherein The doping concentration of the second well region (5) is less than that of the first well region (4).

4. The LDMOS device according to claim 1, characterized in that, The asymmetric stepped field oxide structure (3) extends to a partial top region of the second well region (5) and a region other than the second well region (5).

5. The LDMOS device according to claim 1, wherein The drain (11) is close to the asymmetric stepped field oxide structure (3); the body electrode (12) is located outside the source (10), and the two are short-circuited.

6. The LDMOS device according to claim 1, wherein The side of the asymmetric stepped field oxide structure (3) facing the second well region (5) is an inverted stepped structure, and the side facing the first well region (4) is a non-stepped structure.

7. The LDMOS device according to claim 6, wherein The side of the asymmetric stepped field oxide structure (3) facing the second well region (5) is a two-layer stepped structure; the top angle of the side facing the first well region (4) is less than 90 degrees.

8. The LDMOS device according to claim 1, wherein The asymmetric stepped field oxide structure (3) is an integrally formed structure, including a bottom trapezoidal structure (3-2) and a top trapezoidal structure (3-1) arranged from bottom to top; the sidewall of the bottom trapezoidal structure (3-2) facing the first well region (4) and the sidewall of the top trapezoidal structure (3-1) facing the first well region (4) are on the same straight line; the lower end of the top trapezoidal structure (3-1) is connected to the upper end of the bottom trapezoidal structure (3-2), and the length of the lower end of the top trapezoidal structure (3-1) is greater than the upper end of the bottom trapezoidal structure (3-2).

9. The LDMOS device according to claim 8, wherein, The thickness of the top trapezoidal structure (3-1) is thicker than that of the bottom trapezoidal structure (3-2).

10. The LDMOS device according to claim 1, wherein One end of the gate (7) is located above a partial region of the asymmetric stepped field oxide structure (3), and the other end is located above a partial region of the body region (8).

Images