Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method thereof. The preparation method of the solar cell comprises the following steps: providing a silicon substrate with first doping atoms of a first conductive type; a first tunneling oxide layer and an intrinsic polycrystalline silicon layer are formed on the back face of a silicon substrate, second doping atoms with the conduction type opposite to that of the first doping atoms are diffused into the silicon substrate at a first temperature, and a first doping layer of a second conduction type is formed on the side, close to the back face, of the silicon substrate, converting the intrinsic polycrystalline silicon layer into a first doped polycrystalline silicon layer of a second conductive type; removing the first doped polycrystalline silicon layer; and growing an intrinsic amorphous silicon layer on one side, opposite to the silicon substrate, of the first tunneling oxide layer, and diffusing second doping atoms into the silicon substrate at a second temperature, the first temperature being higher than the second temperature. According to the preparation method of the solar cell, the passivation performance and the contact performance of the solar cell can be considered at the same time, and the cell conversion efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and in particular to a solar cell and a method for manufacturing the same. Background Art

[0002] Currently, with the development of the photovoltaic industry, the need to reduce costs and improve efficiency has become increasingly urgent. The TBC battery product is one of the important solutions for cost reduction and efficiency improvement, and mass production has been achieved. The TBC solar cell is a high-efficiency cell structure that combines the advantages of Topcon (Tunnel Oxide Passivated Contact) and IBC (Interdigitated Back Contact) cells. The general structure of the TBC cell includes: an N-type silicon substrate, and the back surface of the N-type silicon substrate includes alternately arranged P-type doped regions, isolation regions, and N-type doped regions. Among them, in the P-type doped region, a P-type doped layer, a tunneling oxide layer, and a P-type doped polysilicon layer (P + -Si / SiO2 / P + oly-Si structure) are sequentially arranged from the inside of the silicon substrate to the outside. A metal electrode is provided on the P-type doped polysilicon layer, and the metal electrode forms an ohmic contact with the P-type doped polysilicon layer. This P + -Si / SiO2 / P + oly-Si structure and the N-type silicon substrate constitute the PN junction of the battery.

[0003] Currently, one method for preparing the P + -Si / SiO2 / P + oly-Si structure is to sequentially prepare a tunneling oxide layer and an intrinsic amorphous silicon layer on the N-type silicon substrate, and then perform boron atom diffusion at a high temperature above 960 °C, so that boron atoms diffuse into the N-type silicon substrate to form the above-mentioned P-type doped layer, and the intrinsic amorphous silicon layer is transformed into a P-type doped polysilicon layer.

[0004] The above preparation method has the following technical problems. When the doping concentration of the P-type doped layer is increased to improve the contact performance of the P + -Si / SiO2 / P + oly-Si structure, the doping concentration of the P-type doped polysilicon layer will also increase accordingly, resulting in a decrease in passivation performance. Summary of the Invention

[0005] The first aspect of this application provides a method for manufacturing a solar cell, including:

[0006] S10: Provide a silicon substrate, the silicon substrate includes a light-receiving surface and a back surface arranged opposite to each other, and the silicon substrate has first doping atoms of a first conductivity type;

[0007] S20: Form a first tunneling oxide layer and an intrinsic polysilicon layer on the back surface, and diffuse second doping atoms of a second conductivity type into the silicon substrate at a first temperature to form a first doped layer of the second conductivity type on the side of the silicon substrate close to the back surface, convert the intrinsic polysilicon layer into a first doped polysilicon layer of the second conductivity type, and form pinhole channels in the first tunneling oxide layer; the first conductivity type and the second conductivity type have opposite electrical polarities.

[0008] S30: Remove the first doped polysilicon layer.

[0009] S40: Grow an intrinsic amorphous silicon layer on the side of the first tunneling oxide layer facing away from the silicon substrate, and diffuse second doping atoms of a second conductivity type into the silicon substrate at a second temperature to convert the first doped layer into a second doped layer of the second conductivity type and convert the intrinsic amorphous silicon layer into a second doped polysilicon layer of the second conductivity type; the doping concentration of the second doped layer is greater than that of the first doped layer; the first temperature is greater than the second temperature.

[0010] Optionally, in step S10: Texture and polish both sides of a monocrystalline silicon wafer to obtain a silicon substrate, and both the light-receiving surface and the back surface are polished surfaces.

[0011] Optionally, in step S20, grow the first tunneling oxide layer and the intrinsic polysilicon layer on both polished surfaces; in step S30, remove the first doped polysilicon layer on the light-receiving surface and the back surface of the silicon substrate; in step S40, grow an intrinsic amorphous silicon layer on the side of the first tunneling oxide layer on the light-receiving surface and the back surface of the silicon substrate facing away from the silicon substrate.

[0012] Optionally, the monocrystalline silicon wafer is an N-type monocrystalline silicon wafer doped with phosphorus atoms, the resistivity of the monocrystalline silicon wafer is 0.5 - 2 Ω·cm, and the thickness is 50 - 300 μm.

[0013] Optionally, the difference ΔT between the first temperature and the second temperature is 30 °C - 50 °C.

[0014] Optionally, in step S20: Grow the first tunneling oxide layer and the intrinsic polysilicon layer by low-pressure chemical vapor deposition, the thickness of the first tunneling oxide layer is 1.2 nm - 1.8 nm, and the thickness of the intrinsic polysilicon layer is 100 nm - 250 nm.

[0015] Optionally, the first temperature is 900 °C - 970 °C.

[0016] Optionally, the second doping atoms are boron atoms, and the active doping concentration of boron atoms in the first doped layer is 5×10 17 ~3×10 18 atoms / cm 3 , and the junction depth is 0.1 μm - 0.3 μm.

[0017] Optionally, in step S40, an intrinsic amorphous silicon layer is grown by low-pressure chemical vapor deposition, and the thickness of the intrinsic amorphous silicon layer is 150 nm to 300 nm.

[0018] Optionally, in step S40, the second temperature is 860 °C to 910 °C.

[0019] Optionally, the second doping atom is a boron atom, and the active doping concentration of boron atoms in the second doping layer is 3×10 18 ~1×10 20 atoms / cm 3 , and the junction depth is 0.2 μm to 0.4 μm.

[0020] Optionally, the active doping concentration of boron atoms in the second doped polysilicon layer is 3×10 19 ~1×10 20 atoms / cm 3 .

[0021] Optionally, the back surface of the silicon substrate includes alternately distributed first conductivity type regions and second conductivity type regions, and an isolation region is further provided between adjacent first conductivity type regions and second conductivity type regions; after step S40, the following steps are further included:

[0022] S50: Removing the second doping layer, the first tunneling oxide layer, and the second doped polysilicon layer corresponding to the first conductivity type region on the back surface of the silicon substrate;

[0023] S60: Sequentially forming a third doping layer of the first conductivity type, a second tunneling oxide layer, and a third doped polysilicon layer of the first conductivity type on the first conductivity type region of the back surface of the silicon substrate.

[0024] Optionally, the first conductivity type is N-type and the second conductivity type is P-type.

[0025] Optionally, the method for manufacturing a solar cell further includes:

[0026] S70: Forming a textured structure on the light-receiving surface of the silicon substrate and the surface of the back isolation region.

[0027] Optionally, after step S70, the following steps are further included:

[0028] Step S80: Respectively forming a front surface passivation and antireflection layer and a back surface passivation and antireflection layer on the light-receiving surface and the back surface, forming a first electrode at a position corresponding to the first conductivity type region on the back surface passivation and antireflection layer, and forming a second electrode at a position corresponding to the second conductivity type region on the back surface passivation and antireflection layer.

[0029] Optionally, the passivation and antireflection layer includes an alumina layer and a silicon nitride layer, wherein the alumina layer is located between the silicon substrate and the silicon nitride layer.

[0030] Optionally, the thickness of the second tunneling oxide layer is 1.2 - 1.8 nm, and the thickness of the third doped polysilicon layer is 150 - 300 nm.

[0031] Optionally, the surfaces of the first conductivity type region and the second conductivity type region on the back surface of the silicon substrate are polished surfaces with a tower base structure, and the size of the tower base structure is 5 - 30 μm.

[0032] The second aspect of the present application provides a solar cell prepared by the above preparation method, specifically including:

[0033] A silicon substrate having an opposite light-receiving surface and a back surface, and having first doping atoms of a first conductivity type in the silicon substrate;

[0034] A doped layer of a second conductivity type provided on the back surface of the silicon substrate;

[0035] A first tunneling oxide layer provided on the doped layer, and having pinhole channels in the first tunneling oxide layer;

[0036] A doped polysilicon layer of a second conductivity type provided on the first tunneling oxide layer; the first conductivity type and the second conductivity type have opposite electricities;

[0037] The active doping concentration of the doping atoms in the doped layer of the second conductivity type is 3×10 18 ~1×10 20 atoms / cm 3 , and the junction depth is 0.2 μm - 0.4 μm; the active doping concentration of the doping atoms in the doped polysilicon layer of the second conductivity type is 3×10 19 ~1×10 20 atoms / cm 3 .

[0038] Optionally, the back surface of the silicon substrate includes an alternately distributed first conductivity type region and a second conductivity type region, and an isolation region is further provided between adjacent first conductivity type regions and second conductivity type regions; the doped layer of the second conductivity type, the first tunneling oxide layer, and the doped polysilicon layer of the second conductivity type are provided in the second conductivity type region;

[0039] The solar cell further includes: a doped layer of a first conductivity type, a second tunneling oxide layer, and a doped polysilicon layer of a first conductivity type provided in the first conductivity type region on the back surface of the silicon substrate.

[0040] Optionally, the surface of the isolation region is a matte surface, and the surfaces of the first conductivity type region and the second conductivity type region are polished surfaces with a tower base structure.

[0041] Optionally, the size of the tower base structure is 5 - 30 μm.

[0042] Optionally, the first tunneling oxide layer and the second tunneling oxide layer are silicon oxide.

[0043] Preferably, the thickness of the first tunneling oxide layer is 1.2 nm to 1.8 nm, and the thickness of the doped polysilicon layer of the second conductivity type is 150 nm to 300 nm.

[0044] Optionally, the thickness of the second tunneling oxide layer is 1.2 to 1.8 nm, and the thickness of the doped polysilicon layer of the first conductivity type is 150 to 300 nm.

[0045] Optionally, the light-receiving surface of the silicon substrate is a textured surface.

[0046] Optionally, the solar cell further includes a passivation and antireflection layer disposed on the light-receiving surface and the back surface of the silicon substrate;

[0047] Optionally, the passivation and antireflection layer includes an alumina layer and a silicon nitride layer, wherein the alumina layer is located between the silicon substrate and the silicon nitride layer.

[0048] Advantageous effects:

[0049] The preparation method of the solar cell in the first aspect of the present application employs two doping atom diffusion processes, including a first high-temperature diffusion and a second low-temperature diffusion. The first high-temperature diffusion forms pinhole channels (also known as Pinholes channels) in the first tunneling oxide layer. For the second diffusion, only at a lower temperature, the second doping atoms can enter the silicon substrate through the pre-formed Pinholes channels in the first tunneling oxide layer to form a second doping layer with a conductivity type opposite to that of the silicon substrate. Although the decrease in the diffusion temperature will reduce the concentration of the doping atoms diffused into the silicon substrate, the pre-formed Pinholes channels facilitate the diffusion into the silicon substrate, so the concentration of the doping atoms diffused into the silicon substrate will not decrease, and the finally formed second doping layer can still provide good contact performance. Considering the first doping layer formed by pre-diffusion when forming the first doped polysilicon layer for the first time, compared with the doping layer formed by only one diffusion in the prior art, it has a lower concentration and a shallower junction depth, and will not increase Auger recombination, so it will not affect the passivation performance. The decrease in the second diffusion temperature will reduce the doping concentration in the second doped polysilicon layer, thereby reducing parasitic absorption and increasing the current. As the concentration of the doping atoms in the second doped polysilicon layer decreases, the doping concentration near the first tunneling oxide layer will also decrease, and the recombination near the first tunneling oxide layer decreases, improving the passivation performance.

[0050] The solar cell provided in the second aspect of the present invention is prepared by the above preparation method, and this solar cell has both good contact performance and passivation performance. Description of the Drawings

[0051] Figure 1 It is a schematic diagram of the layer structure of the solar cell intermediate obtained by completing step S20 in the first aspect embodiment of the present application;

[0052] Figure 2 It is a schematic diagram of the layer structure of the solar cell intermediate obtained by completing step S30 in the first aspect embodiment of the present application;

[0053] Figure 3 It is a schematic diagram of the layer structure of the solar cell intermediate obtained by completing step S40 in the first aspect embodiment of the present application;

[0054] Figure 4 It is a schematic diagram of the layer structure of the solar cell obtained in the first aspect embodiment of the present application;

[0055] Figure 5 It is a schematic diagram of the preparation process of the solar cell in the first aspect embodiment of the present application.

[0056] Explanation of reference numerals:

[0057] 1 - silicon substrate; 2 - first doping layer; 21 - emitter; 3 - first tunneling oxide layer; 4 - first doped polysilicon layer; 5 - second doping layer; 6 - second doped polysilicon layer; 7 - borosilicate glass BSG; 8 - third doping layer; 9 - second tunneling oxide layer; 10 - third doped polysilicon layer; 11 - back surface passivation and antireflection layer; 12 - front surface passivation and antireflection layer; 13 - first electrode; 14 - second electrode. Detailed implementation manners

[0058] Next, the technical solutions of the present application will be described in detail in conjunction with the attached Figures 1 to 5 to the technical solutions of the present application.

[0059] The general structure of a TBC cell includes: an N-type silicon substrate, and the back surface of the N-type silicon substrate includes alternately arranged P-type doped regions, isolation regions, and N-type doped regions. Among them, in the P-type doped region, a P-type doping layer, a tunneling oxide layer, and a P-type doped polysilicon layer (P + -Si / SiO2 / P + -Poly-Si structure) are sequentially arranged from the inside of the silicon substrate to the outside. A metal electrode is arranged on the P-type doped polysilicon layer, and the metal electrode forms an ohmic contact with the P-type doped polysilicon layer. The inventor found through in-depth research that the contact and passivation performance of the P-type doped region of the TBC cell is determined by the boron atom doping concentration and junction depth in P + -Si, the boron atom doping concentration in the SiO2 layer, the density of pinholes in the SiO2 layer, and P +It is jointly determined by the doping concentration of boron atoms in poly-Si. Among them, the contact performance in a solar cell mainly refers to the contact quality between the metal electrode and the internal materials of the cell. The quality of the contact directly affects the output efficiency and lifespan of the cell. The contact resistance is a key parameter for measuring the contact quality, which reflects the transmission efficiency of current between the electrode and the semiconductor. The smaller the contact resistance, the smoother the current transmission, and the higher the output power and efficiency of the cell. Currently, to prepare P + -Si / SiO2 / P + One method for the Poly-Si structure is to sequentially prepare a tunneling oxide layer and an intrinsic amorphous silicon layer on an N-type silicon substrate, and then perform boron atom diffusion at a high temperature above 960 °C, so that boron atoms diffuse into the N-type silicon substrate to form the above-mentioned P-type doping layer, and the intrinsic amorphous silicon layer is transformed into a P-type doped polycrystalline silicon layer. By the above one-step boron diffusion to form P + -Si / SiO2 / P + -Si / SiO2 / P + -Si, in order to improve the contact performance, it is necessary to appropriately increase the concentration of P + -Si is positively correlated with the density of pinholes. A high boron diffusion temperature increases the density of pinholes at the tunneling layer, thereby increasing the concentration of P + -Si, but the doping concentration of boron atoms in P + -Si will also increase, resulting in an increase in parasitic absorption and a decrease in current. And because the boron source will accumulate at the tunneling layer, the increase in the doping concentration at the tunneling layer increases the probability of recombination, resulting in a decline in passivation performance.

[0060] It can be seen that the above preparation method of the solar cell cannot simultaneously achieve a high doping concentration of P + -Si and a low doping concentration of P + -Si.

[0061] To solve the above technical problems, a first aspect of the present application provides a preparation method of a solar cell, as Figures 1 to 5 shown, this preparation method includes:

[0062] S10: Provide a silicon substrate 1, the silicon substrate 1 includes a light-receiving surface and a back surface arranged oppositely, and the silicon substrate 1 has first doping atoms of a first conductivity type;

[0063] S20: Form a first tunneling oxide layer 3 and an intrinsic polycrystalline silicon layer on the back surface, and diffuse second doping atoms of a second conductivity type into the silicon substrate 1 at a first temperature, form a first doping layer 2 of the second conductivity type on the side of the silicon substrate 1 close to the back surface, transform the intrinsic polycrystalline silicon layer into a first doped polycrystalline silicon layer 4 of the second conductivity type, and form pinhole channels in the first tunneling oxide layer 3; The first conductivity type and the second conductivity type have opposite electrical properties;

[0064] S30: Remove the first doped polysilicon layer 4;

[0065] S40: Grow an intrinsic amorphous silicon layer on the side of the first tunneling oxide layer 3 facing away from the silicon substrate 1, and diffuse second doping atoms of a second conductivity type into the silicon substrate 1 at a second temperature, so that the first doped layer is transformed into a second doped layer 5 of the second conductivity type, and the intrinsic amorphous silicon layer is transformed into a second doped polysilicon layer 6 of the second conductivity type; the doping concentration of the second doped layer 5 is greater than the doping concentration of the first doped layer 2; the first temperature is greater than the second temperature.

[0066] In the method for preparing a solar cell provided by the embodiment of the present application, the silicon substrate 1 itself exhibits a first conductivity type due to the presence of first doping atoms. When the doping atoms are phosphorus, the silicon substrate 1 is of N type; when the doping atoms are boron, the silicon substrate 1 is of P type.

[0067] In the embodiments of the present application, two diffusion processes are adopted to diffuse doping atoms with the opposite conductivity type into the silicon substrate, including the first high-temperature diffusion and the second low-temperature diffusion. For example, for the N-type silicon substrate 1, boron diffusion is performed to form a P-type first doped layer 2 and a P-type first doped polysilicon layer; for the P-type silicon substrate 1, phosphorus diffusion is performed to form an N-type first doped layer 2 and an N-type first doped polysilicon layer. Among them, in step S20, the first tunneling oxide layer 3 and the intrinsic polysilicon layer are used as barriers to diffuse into the silicon substrate 1 to form the first doped layer 2. The first high-temperature diffusion forms pinhole channels (also called Pinholes channels) in the first tunneling oxide layer 3. For the second diffusion, only at a lower temperature, the doping source can enter the silicon substrate 1 through the Pinholes channels pre-formed in the first tunneling oxide layer 3 to form the second doped layer 5. Although the decrease in the diffusion temperature will reduce the concentration of the doping atoms diffused into the silicon substrate, the pre-formed Pinholes channels are conducive to diffusion (when diffusion is performed at a higher first temperature, the density of Pinholes formed in the first tunneling oxide layer is relatively high. On this basis, the diffusion at a lower second temperature will not significantly increase the density of Pinholes formed in the first tunneling oxide layer), so the concentration diffused into the silicon substrate will not decrease, and the finally formed second doped layer 5 can still provide good contact performance. Moreover, when the first high-temperature diffusion forms the first doped polysilicon layer 4, a pre-diffused first doped layer 2 is formed inside the silicon substrate 1. Compared with the doped layer directly diffused into the silicon substrate, it has a lower concentration and a shallower junction depth, and will not increase Auger recombination, so it will not affect the passivation performance. The decrease in the second diffusion temperature will reduce the doping concentration in the second doped polysilicon layer 6, thereby reducing parasitic absorption and increasing the current. As the doping atom concentration in the second doped polysilicon layer decreases, the doping concentration near the first tunneling oxide layer 3 will also decrease, and the recombination near the first tunneling oxide layer 3 will decrease, improving the passivation performance. In addition, when diffusion is performed, silicon glass containing doping atoms (such as phosphosilicate glass PSG or borosilicate glass BSG) will be generated. The decrease in the second diffusion temperature makes the formed silicon glass thinner, making it easier to remove the silicon glass by subsequent laser, and the laser power can be appropriately reduced to reduce the damage to the silicon wafer surface.

[0068] In the embodiments of the present application, the difference ΔT between the first temperature and the second temperature can be 30°C to 50°C, such as 35°C, 40°C, 45°C, etc. The first temperature can be 900°C to 970°C, such as 905°C, 910°C, 915°C, 920°C, 925°C, 930°C, 935°C, 940°C, 945°C, 950°C, 955°C, 960°C, 965°C, etc. The second temperature can be 860°C to 910°C, such as 865°C, 870°C, 875°C, 880°C, 890°C, 895°C, 900°C, 905°C, 910°C, etc.

[0069] In the solar cell prepared by the method provided in the embodiments of the present application, for the case where the N-type silicon substrate and the second doping atom is a boron atom, in the second doping layer formed by diffusion inside the silicon substrate 1, the active doping concentration of boron atoms can be 3×10 18 ~1×10 20 atoms / cm 3 , for example, 4×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 , 8×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 , 2×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 etc., and further can be 3×10 18 ~6×10 18 atoms / cm 3 . The junction depth can be 0.2 μm to 0.4 μm, such as 0.25 μm, 0.30 μm, 0.35 μm, etc. The active doping concentration of boron atoms in the second doped polysilicon layer 6 can be 3×10 19 ~1×10 20 atoms / cm 3 , for example, 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 7×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 , 9×10 19 atoms / cm 3 etc.

[0070] In the embodiment of the present application, in step S10, the silicon substrate is obtained by subjecting a single-crystal silicon wafer to double-sided texturing and polishing, and both the light-receiving surface and the back surface are polished surfaces. The resistivity of the single-crystal silicon wafer can be 0.5 - 2 Ω, and the thickness can be 50 - 300 μm. In step S20, a first tunneling oxide layer and an intrinsic polysilicon layer are grown on the two polished surfaces, and the diffusion at the first temperature can also be performed simultaneously on both sides of the silicon substrate 1. Then, after completing step S20, a structure of a first doped layer 2 / a first tunneling oxide layer 3 / a first doped polysilicon layer 4 is formed simultaneously on both sides of the silicon substrate 1. Moreover, a silicon glass layer with a second doped atom will be formed on the surface of the first doped polysilicon layer 6. For example, when boron diffusion is performed, boron silicate glass BSG is formed, and when phosphorus diffusion is performed, phosphosilicate glass PSG is formed.

[0071] In step S20, the first tunneling oxide layer and the intrinsic polysilicon layer can be grown by low-pressure chemical vapor deposition (LPCVD). Among them, the first tunneling oxide layer 3 can be a silicon oxide layer, and its thickness can be 1.2 nm - 1.8 nm (such as 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, etc.), and the thickness of the intrinsic polysilicon layer can be 100 nm - 250 nm (such as 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, etc.). For the case of an N-type silicon substrate and the second doped atom being a boron atom, the active doping concentration of boron atoms in the first doped layer 2 formed in step S20 can be 5×10 17 ~3×10 18 atoms / cm 3 (such as 6×10 17 atoms / cm 3 、7×10 17 atoms / cm 3 、8×10 17 atoms / cm 3 、9×10 17 atoms / cm 3 、10 18 atoms / cm 3 、2×10 18 atoms / cm 3 etc.), and the junction depth can be 0.1 μm - 0.3 μm (such as 0.12 μm, 0.14 μm, 0.15 μm, 0.16 μm, 0.18 μm, 0.2 μm, 0.22 μm, 0.24 μm, 0.25 μm, 0.26 μm, 0.28 μm, etc.).

[0072] Further, in step S30, before removing the first doped polysilicon layer 4, the above-mentioned silicon glass layer needs to be removed first. The silicon glass layer can be removed by an acidic cleaning solution (such as hydrofluoric acid) first, and then the first doped polysilicon layer 4 can be removed by an alkaline cleaning solution (such as sodium hydroxide or potassium hydroxide solution).

[0073] Further, in step S40, an intrinsic amorphous silicon layer α-Si is grown by the LPCVD method. The thickness of the intrinsic amorphous silicon layer α-Si can be 150 nm to 300 nm (such as 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 250 nm, 260 nm, 280 nm, etc.). The intrinsic amorphous silicon layer can be grown only on the back surface of the silicon substrate 1, or on both sides of the silicon substrate 1. After the second diffusion, a silicon glass layer containing a second doped atom (such as borosilicate glass BSG7) is also formed on the second doped polysilicon layer 6. It can be understood that amorphous silicon is transformed into polysilicon during the diffusion process.

[0074] For a TBC cell, generally, a first conductive type region and a second conductive type region are alternately defined on the back surface of the silicon substrate 1, and an isolation region is also provided between adjacent first conductive type regions and second conductive type regions. For an N-type silicon substrate, the first conductive type region is the N-type region, and the second conductive type region is the P-type region. For a P-type silicon substrate, the first conductive type region is the P-type region, and the second conductive type region is the N-type region.

[0075] After the above steps 10 to 40, a structure of a second doped layer 5 / first tunneling oxide layer 3 / second doped polysilicon layer 6 is formed on the entire back surface of the silicon substrate 1. For a TBC cell, the structure of the second doped layer 5 / first tunneling oxide layer 3 / second doped polysilicon layer 7 serves as the emitter 21 of the TBC cell and is correspondingly disposed in the second conductive type region. It is necessary to further remove the structure of the second doped layer 5 / first tunneling oxide layer 3 / second doped polysilicon layer 7 corresponding to the first conductive type region and the isolation region, and form a third doped layer 8 of the first conductive type, a second tunneling oxide layer 9, and a third doped polysilicon layer 10 of the first conductive type on the first conductive type region.

[0076] Specifically, it is realized through the following steps.

[0077] Step S50: Remove the second doped layer 5, the first tunneling oxide layer 3, and the second doped polysilicon layer 6 corresponding to the first conductive type region on the back surface of the silicon substrate 1.

[0078] As described above, a silicon glass layer is further formed on the second doped polysilicon layer 6. First, the silicon glass layer at the corresponding positions of the first conductive type region and the isolation region is removed by laser (the first laser), and then the silicon glass layer on the light-receiving surface is removed by an acidic cleaning solution (such as hydrofluoric acid). Then, the second doped layer 5, the first tunneling oxide layer 3, and the second doped polysilicon layer 6 corresponding to the first conductive type region near the light-receiving surface and the back surface are removed by an alkaline cleaning solution (such as sodium hydroxide solution or potassium hydroxide solution) and an acidic cleaning solution (such as hydrofluoric acid).

[0079] Step S60: A third doped layer 8 of the first conductive type, a second tunneling oxide layer 9, and a third doped polysilicon layer 10 of the first conductive type are sequentially formed on the first conductive type region on the back surface of the silicon substrate.

[0080] The second tunneling oxide layer 9 and the intrinsic polysilicon layer (or intrinsic amorphous silicon layer) can be grown on the surface of the silicon substrate 1 by LPCVD method. Then, the doping atoms of the first conductive type diffuse, and the third doped layer 8 is formed at the position corresponding to the first conductive type region inside the silicon substrate 1, and the third doped polysilicon layer 10 is formed on the second tunneling oxide layer 9. A silicon glass layer containing the first doping atoms is further formed on the third doped polysilicon layer 10. And it can be understood that the third doped layer 8 / the second tunneling oxide layer 9 / the third doped polysilicon 10 / the silicon glass layer containing the first doping atoms are also formed on the light-receiving surface of the silicon substrate 1. And the above structure is also formed on the silicon glass layer containing the second doping atoms formed on the second conductive type region on the back surface and the surface of the isolation region before.

[0081] In the embodiment of the present application, the thickness of the second tunneling oxide layer 9 can be 1.2 - 1.8 nm, such as 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, etc. The thickness of the third doped polysilicon layer 10 can be 150 - 300 nm, such as 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 250 nm, 260 nm, 280 nm, etc.

[0082] Step S70: A textured structure is formed on the surfaces of the light-receiving surface and the back surface isolation region of the silicon substrate 1.

[0083] Specifically, the silicon glass layer on the second-conductivity-type region and the isolation region on the back surface is removed by a second laser, and the silicon glass layer containing the first doped atoms on the light-receiving surface is removed by an acidic cleaning solution (such as hydrofluoric acid); then, the second tunneling oxide layer 9 and the third doped polysilicon layer 10 corresponding to the light-receiving surface, the second-conductivity-type region, and the isolation region on the back surface, and the third doped layer 8 on the light-receiving surface and the isolation region are removed by an alkaline cleaning solution (such as sodium hydroxide solution or potassium hydroxide solution) and an acidic cleaning solution (such as hydrofluoric acid). Then, texturing is performed to make the surface of the silicon substrate 1 exposed on the light-receiving surface and the isolation region have a textured structure.

[0084] It can be understood that during texturing, the second doped polysilicon layer 6 is protected by the silicon glass layer containing the second doped atoms, and the third doped polysilicon layer 8 is protected by the silicon glass layer containing the first doped atoms. Only the surfaces of the isolation region on the back surface and the light-receiving surface are exposed. After texturing, the silicon glass layer containing the first doped atoms and the silicon glass layer containing the second doped atoms located on the back surface are removed by using an acidic cleaning solution (such as hydrofluoric acid solution).

[0085] Step S80: A front surface passivation and antireflection layer 12 and a back surface passivation and antireflection layer 11 are respectively formed on the light-receiving surface and the back surface. A first electrode 13 is formed at a position corresponding to the first-conductivity-type region on the back surface passivation and antireflection layer 11, and a second electrode 14 is formed at a position corresponding to the second-conductivity-type region on the back surface passivation and antireflection layer 11.

[0086] The passivation and antireflection layer can be a stacked structure of aluminum oxide Al2O3 and silicon nitride SiN x and the aluminum oxide layer is disposed on the surface of the doped polysilicon layer and the surface of the silicon substrate in the isolation region, that is, between the silicon substrate 1 and the silicon nitride layer. The first electrode 13 and the second electrode 14 can be formed by screen-printing a paste and sintering. The first electrode 13 makes an ohmic contact with the third doped polysilicon layer 10, and the second electrode 14 makes an ohmic contact with the second doped polysilicon layer 6.

[0087] In the embodiment of the present application, the structure of the doped layer / tunneling oxide layer / doped polysilicon on the first-conductivity-type region and the second-conductivity-type region on the back surface is established on the polished surface. The size of the base of the tower on the polished surface can be 5 - 30 μm, such as 10 μm, 15 μm, 20 μm, 25 μm, etc. The base size within this range can enable the silicon substrate to have better light absorption ability, which helps to improve the photoelectric conversion efficiency. The base is a rectangular plane formed after the textured surface is polished. When the base size exceeds 30 microns, the surface of the cell is very flat, and it can be considered almost a plane with very small roughness.

[0088] In these embodiments, the silicon wafer is polished to form a tower base structure. Looking down at the silicon wafer and seeing each tower base as a rectangle under magnification, the size of the tower base refers to the shortest straight-line distance between two opposite sides of the rectangle.

[0089] After step S80, an optical injection step may further be included.

[0090] The second aspect of the present application provides a solar cell, which is prepared by using the preparation method of the solar cell in the first aspect of the present application.

[0091] This solar cell includes:

[0092] A silicon substrate 1, having an opposite light-receiving surface and a back surface, and having first doping atoms of a first conductivity type in the silicon substrate;

[0093] A doping layer of a second conductivity type (i.e., the second doping layer 5) provided on the back surface of the silicon substrate 1;

[0094] A first tunneling oxide layer 3 provided on the second doping layer 5, and having pinhole channels in the first tunneling oxide layer 3;

[0095] A doped polysilicon layer of a second conductivity type (i.e., the second doped polysilicon layer 6) provided on the first tunneling oxide layer 3; the first conductivity type and the second conductivity type have opposite electrical properties;

[0096] The active doping concentration of the doping atoms in the above-mentioned second doping layer 5 may be 3×10 18 ~1×10 20 atoms / cm 3 , and further may be 3×10 18 ~6×10 18 atoms / cm 3 , and the junction depth may be 0.2 μm to 0.4 μm; the active doping concentration of the doping atoms in the above-mentioned second doped polysilicon layer 6 may be 3×10 19 ~1×10 20 atoms / cm 3 .

[0097] Optionally, in the embodiments of the present application, the back surface of the silicon substrate 1 includes alternately distributed first conductivity type regions and second conductivity type regions, and an isolation region is further provided between adjacent first conductivity type regions and second conductivity type regions; the doping layer of the second conductivity type (the second doping layer 5), the first tunneling oxide layer 3, and the doped polysilicon layer of the second conductivity type (the second doped polysilicon layer 6) are provided in the second conductivity type regions.

[0098] Optionally, the solar cell according to an embodiment of the present application may further include: a doping layer (third doping layer 8) of a first conductivity type provided on the back surface of the silicon substrate 1 in a first conductivity type region, a second tunneling oxide layer 9, and a doped polysilicon layer of a first conductivity type (third doped polysilicon layer 10).

[0099] Optionally, the surface of the isolation region is a matte surface, and the surfaces of the first conductivity type region and the second conductivity type region are polished surfaces having a tower base structure. The size of the tower base structure may be 5 - 30 μm.

[0100] Optionally, the first tunneling oxide layer 3 and the second tunneling oxide layer 9 may be silicon oxide.

[0101] Optionally, the thickness of the first tunneling oxide layer 3 may be 1.2 nm - 1.8 nm, and the thickness of the doped polysilicon layer of the second conductivity type (second doped polysilicon layer 6) may be 150 nm - 300 nm.

[0102] Optionally, the thickness of the second tunneling oxide layer 9 may be 1.2 - 1.8 nm, and the thickness of the doped polysilicon layer of the first conductivity type (third doped polysilicon layer 10) may be 150 - 300 nm.

[0103] Optionally, the light-receiving surface of the silicon substrate 1 is a matte surface.

[0104] Optionally, the solar cell according to an embodiment of the present application further includes a front surface passivation and antireflection layer 12 provided on the light-receiving surface of the silicon substrate 1 and a back surface passivation and antireflection layer 11 provided on the back surface. The passivation and antireflection layer may be a stacked structure including an alumina layer and a silicon nitride layer, where the alumina layer is located between the silicon substrate 1 and the silicon nitride layer.

[0105] In the solar cell structure provided by the embodiment of the present application, the second doping layer 5 of the second conductivity type / the first tunneling oxide layer 3 / the second doped polysilicon 6 of the second conductivity type serves as an emitter, forming a PN junction with the silicon substrate 1 of the first conductivity type. In this solar cell, the second doping layer 5 located in the silicon substrate 1 has a relatively high doping concentration, thereby providing good contact performance; at the same time, the second doped polysilicon layer 6 has a relatively low doping concentration, which can reduce parasitic absorption and increase the current of the solar cell. And as the doping concentration in the second doped polysilicon layer 6 decreases, the doping concentration near the first tunneling oxide layer 3 also decreases, the recombination near the first tunneling oxide layer 3 decreases, and the passivation performance is improved.

[0106] Taking an N-type silicon substrate as an example, the preparation method and the prepared solar cell provided by the embodiment of the present application will be further described in detail below.

[0107]

Example 1

[0108] Step S10: A N-type silicon wafer with a resistivity of 1.2 Ωcm and a thickness of 150 μm is textured and polished to obtain a silicon substrate 1. The silicon substrate 1 includes a light-receiving surface and a back surface that are oppositely arranged and are both polished surfaces, and the polished surfaces have pyramid bases with a size of 18 μm.

[0109] Step S20: Subsequently, the polished silicon wafer is loaded into an LPCVD quartz boat, and a first tunneling oxide layer 3 with a thickness of 1.6 nm and an intrinsic polysilicon layer i-Poly-Si with a thickness of 250 nm are grown on the polished surface. Then, boron diffusion is performed at a high temperature of 950 °C to form an internally diffused P + 1-Si region (P + 1-Si region, i.e., the first doped layer 2), and the intrinsic polysilicon layer i-Poly-Si is transformed into a first P-type doped polysilicon layer P + 1Poly-Si (the first P-type doped polysilicon layer P + 1Poly-Si, i.e., the first doped polysilicon layer 4), and the active doping concentration of boron atoms in the P + 1-Si region is 1×10 18 atoms / cm 3 .

[0110] As Figure 1 shown, in step S20, a first tunneling oxide layer SiO 2-1 and an intrinsic polysilicon layer i-Poly-Si are grown on the two polished surfaces. After completing step S20, boron sources are internally diffused on the side of the silicon substrate close to the back surface and the side close to the light-receiving surface to form a P + 1-Si region.

[0111] Step S30: Remove the borosilicate glass BSG7 and the first P-type doped polysilicon layer P + 1Poly-Si on the light-receiving surface and the back surface of the silicon substrate by alkali cleaning. As Figure 2 shown, after completing step S30, the boron sources on the side of the silicon substrate close to the back surface and the side close to the light-receiving surface have a P + 1-Si region, and the first tunneling oxide layer SiO 2-1 is retained on both the back surface and the light-receiving surface.

[0112] Step S40: Grow a 250-nm amorphous silicon layer α-Si on the side of the first tunneling oxide layer SiO 2-1 3 facing away from the silicon substrate by LPCVD. Then, boron diffusion is performed at a low temperature of 890 °C to form a second P-type doped polysilicon layer P 2-1 2Poly-Si (the second doped polysilicon layer 6) on the side of the first tunneling oxide layer SiO + 3 facing away from the silicon substrate, and activate the second P-type doped polysilicon layer P + 2Poly-Si. The second P-type doped polysilicon layer P+ The active doping concentration of boron atoms in 2Poly-Si is 6×10 19 atoms / cm 3 , and the boron source enters the silicon substrate 1 through the Pinholes channels pre-formed in SiO 2-1 . At this time, the inward diffusion forms a P + 2-Si region (the second doping layer 5). The active doping concentration of boron atoms in the P + 2-Si region is 5×10 18 atoms / cm 3 , and the junction depth is 0.3μm, as Figure 3 shown.

[0113] In this step, when heating up to the preset boron diffusion temperature stage before the second boron diffusion, the amorphous silicon layer α-Si will crystallize to form a polysilicon layer.

[0114] Step S50: In the preset N region, that is, the region where the N-type doped polysilicon layer N + Poly-Si (the third doped polysilicon layer 10) needs to be prepared. Remove the BSG on the front side by the first laser, and remove the boron silicate glass BSG 7 on the light-receiving surface on the front side by single-sided etching. Then, wash away the P + 2-Si region, the first tunneling oxide layer SiO 2-1 and the second P-type doped polysilicon layer P + 2Poly-Si in the light-receiving surface and the preset N region by alkaline polishing.

[0115] In these embodiments, during the process from step S10 to step S40, the light-receiving surface (front side) and the back side of the silicon substrate have a symmetric layer structure, and the layer structure on the front side is removed in step S50.

[0116] Step S60: Use LPCVD and a diffusion furnace to prepare an N + -Si / SiO 2-2 / N + Poly-Si structure. The N + -Si / SiO 2-2 / N + Poly-Si structure includes an N + -Si region 8 near the back side of the silicon substrate 1, the second tunneling oxide layer SiO 2-2 on the back side, and the N-type doped polysilicon layer N + Poly-Si 10. The thickness of the second tunneling oxide layer SiO 2-2 9 is 1.4nm, and the thickness of the N-type doped polysilicon layer N + Poly-Si10 is 200nm.

[0117] Step S70: Remove the phosphosilicate glass (PSG) in the spacer between the P region and the N region and the PSG in the P region through a second laser. Remove the PSG on the front side by single-sided etching, and then perform texturing. After the textured surfaces are formed on the light-receiving surface of the silicon substrate and the exposed backside portion of the silicon substrate in the spacer region, use an HF bath to remove the PSG and borosilicate glass (BSG7) on the backside.

[0118] The laser removes the PSG on the surface of the P region on the backside of the cell, as well as the PSG on the surface of the spacer between the P region and the N region. The single-sided etching removes the PSG on the front side (referred to as the light-receiving surface) of the cell. The light-receiving surface of the cell (the surface exposed to sunlight) generally needs to be textured to achieve an antireflection effect.

[0119] In addition, during texturing, the P region on the backside is protected by BSG, and the N region is protected by PSG. Therefore, only the light-receiving surface (front side) and the spacer region on the backside will form textured surfaces.

[0120] Step S80: Finally, deposit 5 nm of Al2O3 and 75 nm of SiN on the light-receiving surface and the backside of the silicon substrate x 、screen printing, sintering, and light injection to obtain the TBC cell structure as Figure 4 shown.

[0121]

Comparative Example 1

[0122] In Comparative Example 1, there is only one boron diffusion step, and the boron diffusion temperature is relatively high.

[0123] The differences from the embodiment are in steps S20, S30, and S40. Comparative Example 1 does not have steps S20 and S30, and for step S40: it is necessary to prepare a tunneling oxide layer and an amorphous silicon layer (α-Si) by LPCVD method, and perform boron diffusion at a temperature above 960 °C. In Comparative Example 1, the concentration of the P-type doped polycrystalline silicon layer P + Poly-Si and the doping concentration at the tunneling oxide layer are both higher than those in Example 1, and the BSG thickness and the doping concentration in the BSG are also higher than those in Example 1.

[0124] Table 1: Comparative table of the electrical performance data of the TBC back-contact solar cells in Example 1 and Comparative Example 1

[0125] Isc (A) Voc (V) FF (%) Eta (%) Example 1 14.2573 0.7335 78.7241 24.8566 Comparative Example 1 14.2436 0.7323 78.5685 24.7431

[0126] As shown in Table 1, the rated capacity Eta, fill factor FF, open-circuit voltage Voc, and short-circuit current Isc of the TBC battery obtained in Example 1 are respectively higher than those of the TBC battery obtained in Comparative Example 1. A high Eta value indicates that the device can provide a higher power output under standard operating conditions, which usually means that the device is more efficient and can provide more energy under the same conditions. The fill factor is an important parameter for measuring the performance of a solar cell, representing the ratio of the photocurrent and voltage corresponding to the maximum power point to the open-circuit voltage and short-circuit current. The higher the FF value, the higher the efficiency of the solar cell, the smaller the energy loss, and the better the overall performance. The open-circuit voltage is the voltage value of the solar cell in the open-circuit state. A high Voc value indicates that the solar cell can provide a larger voltage under the same light conditions, which is beneficial to improving the energy conversion efficiency of the battery. A high Voc value means that the battery can output a higher voltage under light conditions, thereby improving the overall energy conversion efficiency. The short-circuit current is the current value of the solar cell in the short-circuit state. A high Isc value indicates that the battery can provide a larger current under the same light conditions, which is of great significance for improving the overall output power of the solar cell. A high Isc value means that the battery can output more current under light conditions, thereby improving the overall energy conversion efficiency. Thus, the battery prepared by the method for preparing a solar cell of the present application has both good passivation performance and contact performance, and the conversion efficiency of the battery is further improved.

[0127] The above description is only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for preparing a solar cell, characterized in that, Including: S10: Provide a silicon substrate, the silicon substrate includes a light-receiving surface and a back surface which are oppositely arranged, and the silicon substrate has first doping atoms of a first conductivity type; S20: Form a first tunneling oxide layer and an intrinsic polysilicon layer on the back surface, and diffuse second doping atoms of a second conductivity type into the silicon substrate at a first temperature, forming a first doped layer of the second conductivity type on the side of the silicon substrate close to the back surface, converting the intrinsic polysilicon layer into a first doped polysilicon layer of the second conductivity type, and forming pinhole channels in the first tunneling oxide layer; The first conductivity type and the second conductivity type have opposite electrical properties; S30: Remove the first doped polysilicon layer; S40: Grow an intrinsic amorphous silicon layer on the side of the first tunneling oxide layer facing away from the silicon substrate, and diffuse second doping atoms of a second conductivity type into the silicon substrate at a second temperature, converting the first doped layer into a second doped layer of the second conductivity type, and converting the intrinsic amorphous silicon layer into a second doped polysilicon layer of the second conductivity type; The doping concentration of the second doped layer is greater than that of the first doped layer; The first temperature is greater than the second temperature.

2. The manufacturing method of the solar cell according to claim 1, characterized in that, In the step S10: Obtain the silicon substrate by texturing and double-sided polishing a single-crystalline silicon wafer, and both the light-receiving surface and the back surface are polished surfaces; Preferably, in the step S20, the first tunneling oxide layer and the intrinsic polysilicon layer are grown on the two polished surfaces; In the step S30, remove the first doped polysilicon layer on the light-receiving surface and the back surface of the silicon substrate; In the step S40, grow the intrinsic amorphous silicon layer on the side of the first tunneling oxide layer on the light-receiving surface and the back surface of the silicon substrate facing away from the silicon substrate; Preferably, the single-crystalline silicon wafer is an N-type single-crystalline silicon wafer doped with phosphorus atoms, the resistivity of the single-crystalline silicon wafer is 0.5 - 2 Ω·cm, and the thickness is 50 - 300 μm.

3. The manufacturing method of the solar cell according to claim 1, characterized in that, The difference ΔT between the first temperature and the second temperature is 30 °C - 50 °C.

4. The manufacturing method of the solar cell according to claim 1, characterized in that, In the step S20: Grow the first tunneling oxide layer and the intrinsic polysilicon layer by low-pressure chemical vapor deposition, the thickness of the first tunneling oxide layer is 1.2 nm - 1.8 nm, and the thickness of the intrinsic polysilicon layer is 100 nm - 250 nm; Preferably, the first temperature is 900 °C - 970 °C; Preferably, the second doping atom is a boron atom, and the active doping concentration of boron atoms in the first doping layer is 5×10 17 ~3×10 18 atoms / cm 3 , and the junction depth is 0.1 μm to 0.3 μm.

5. The manufacturing method of the solar cell according to claim 1, characterized in that, In the step S40: Grow the intrinsic amorphous silicon layer by low-pressure chemical vapor deposition, and the thickness of the intrinsic amorphous silicon layer is 150 nm - 300 nm; Preferably, in the step S40: the second temperature is 860 °C - 910 °C; Preferably, the second doping atom is a boron atom, and the active doping concentration of boron atoms in the second doping layer is 3×10 18 ~1×10 20 atoms / cm 3 , and the junction depth is 0.2 μm to 0.4 μm; Preferably, the active doping concentration of boron atoms in the second doped polysilicon layer is 3×10 19 ~1×10 20 atoms / cm 3 .

6. The method for preparing a solar cell according to claim 1, wherein, The back surface of the silicon substrate includes alternately distributed first conductivity type regions and second conductivity type regions, and an isolation region is also provided between adjacent first conductivity type regions and second conductivity type regions; After the step S40, it further includes: S50: Remove the second doped layer, the first tunneling oxide layer, and the second doped polysilicon layer corresponding to the first conductivity type region on the back surface of the silicon substrate; S60: A third doped layer of the first conductivity type, a second tunneling oxide layer, and a third doped polysilicon layer of the first conductivity type are sequentially formed on the first conductivity type region on the back surface of the silicon substrate; Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

7. The method for preparing a solar cell according to claim 6, wherein It further includes: S70: A textured structure is formed on the light-receiving surface and the surface of the back isolation region of the silicon substrate; Preferably, after step S70, it further includes: Step S80: A front surface passivation and antireflection layer and a back surface passivation and antireflection layer are respectively formed on the light-receiving surface and the back surface. A first electrode is formed at a position corresponding to the first conductivity type region on the back surface passivation and antireflection layer, and a second electrode is formed at a position corresponding to the second conductivity type region on the back surface passivation and antireflection layer; Preferably, the passivation and antireflection layer includes an alumina layer and a silicon nitride layer, wherein the alumina layer is located between the silicon substrate and the silicon nitride layer.

8. The manufacturing method of the solar cell according to claim 7, wherein, The thickness of the second tunneling oxide layer is 1.2 - 1.8 nm, and the thickness of the third doped polysilicon layer is 150 - 300 nm; Preferably, the surfaces of the first conductivity type region and the second conductivity type region on the back surface of the silicon substrate are polished surfaces with a tower base structure, and the size of the tower base structure is 5 - 30 μm.

9. A solar cell, characterized in that, The solar cell includes: A silicon substrate having opposite light-receiving surface and back surface, and the silicon substrate has first doped atoms of the first conductivity type; A doped layer of the second conductivity type provided on the back surface of the silicon substrate; A first tunneling oxide layer provided on the doped layer, and the first tunneling oxide layer has pinhole channels; A doped polysilicon layer of the second conductivity type provided on the first tunneling oxide layer; the first conductivity type and the second conductivity type have opposite electrical properties; The active doping concentration of doped atoms in the doping layer of the second conductivity type is 3×10 18 ~1×10 20 atoms / cm 3 , and the junction depth is 0.2 μm to 0.4 μm; the active doping concentration of doped atoms in the doped polysilicon layer of the second conductivity type is 3×10 19 ~1×10 20 atoms / cm 3 .

10. The solar cell according to claim 9, characterized in that, The back surface of the silicon substrate includes alternately distributed first conductivity type regions and second conductivity type regions, and an isolation region is further provided between adjacent first conductivity type regions and second conductivity type regions; the doped layer of the second conductivity type, the first tunneling oxide layer, and the doped polysilicon layer of the second conductivity type are provided in the second conductivity type region; The solar cell further includes: a doped layer of the first conductivity type, a second tunneling oxide layer, and a doped polysilicon layer of the first conductivity type provided in the first conductivity type region on the back surface of the silicon substrate; Preferably, the surface of the isolation region is textured, and the surfaces of the first conductivity type region and the second conductivity type region are polished surfaces with a tower base structure; Preferably, the size of the tower base structure is 5 - 30 μm; Preferably, the first tunneling oxide layer and the second tunneling oxide layer are silicon oxide; Preferably, the thickness of the first tunneling oxide layer is 1.2 nm - 1.8 nm, and the thickness of the doped polysilicon layer of the second conductivity type is 150 nm - 300 nm; Preferably, the thickness of the second tunneling oxide layer is 1.2 - 1.8 nm, and the thickness of the doped polysilicon layer of the first conductivity type is 150 - 300 nm; Preferably, the light-receiving surface of the silicon substrate is textured; Preferably, the solar cell further includes a passivation and antireflection layer disposed on the light-receiving surface and the back surface of the silicon substrate; Preferably, the passivation and antireflection layer includes an aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer is located between the silicon substrate and the silicon nitride layer.

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