Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention provides a solar cell and a preparation method thereof, and a photovoltaic module. In the embodiment of the invention, a first internal expansion layer with the same conduction type as a first doping layer and / or a second internal expansion layer with the same conduction type as a second doping layer are / is arranged in an interval region used for forming an isolation region on the back surface of a silicon substrate; and the first internal expansion layer and the second internal expansion layer are electrically connected, so that the field passivation effect can be realized, the recombination of minority carriers in the isolation region can be effectively reduced, reverse conduction can be realized when the battery piece is shielded, the breakdown can be avoided, and the hot spot prevention effect can be effectively realized.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and particularly to a solar cell based on an IBC cell structure, a preparation method thereof, and a photovoltaic module. Background Art

[0002] In recent years, back contact (BC) cells have received extensive attention due to their unique structural design. Different from traditional crystalline silicon cells, the positive and negative electrodes of BC cells are both located on the back of the cell, avoiding the light shielding of the front electrode, thereby improving the light utilization rate and the conversion efficiency of the cell.

[0003] During actual use, there may be obstacles such as bird droppings, leaves, sand and dust falling on the back contact cell. After the cell is blocked by the obstacle, the temperature will rise and the hot spot effect will occur. If the temperature generated by the hot spot exceeds a certain temperature value, it will cause problems such as delamination of the photovoltaic module, burning of the backplane, and bursting of the glass, resulting in the scrapping of the entire back contact cell and even a fire risk in severe cases. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a back contact cell, a preparation method thereof, and a photovoltaic module to solve the problem that when there is an external object blocking in the existing BC cell module, a significant hot spot effect will occur, seriously affecting the efficiency and reliability of the module.

[0005] To solve the above problems, the present invention is realized by the following technical solutions:

[0006] The present invention provides a back contact cell, which includes a silicon substrate, a first inner diffusion layer, a second inner diffusion layer, a first tunneling layer, a second tunneling layer, a first doping layer, and a second doping layer;

[0007] The back surface of the silicon substrate includes a first region, a second region, and a spacer region. The first region and the second region are arranged alternately, and a spacer region is provided between the first region and the second region. The first tunneling layer and the first doping layer are sequentially arranged on the first region, and the second tunneling layer and the second doping layer are sequentially arranged on the second region. Among them, the conduction types of the first doping layer and the second doping layer are opposite;

[0008] The first inner diffusion layer is arranged in the silicon substrate corresponding to the first region, the second inner diffusion layer is arranged in the silicon substrate corresponding to the second region, the first inner diffusion layer and / or the second inner diffusion layer are arranged in the silicon substrate corresponding to the spacer region, and the first inner diffusion layer and the second inner diffusion layer are electrically connected. Among them, the conduction types of the first inner diffusion layer and the first doping layer are the same, and the conduction types of the second inner diffusion layer and the second doping layer are the same.

[0009] Optionally, in the back-contact battery, a co-diffusion layer is further disposed in the silicon substrate, the co-diffusion layer is disposed between the first inner diffusion layer and the second inner diffusion layer, and the co-diffusion layer is used to conduct the electrical connection between the first inner diffusion layer and the second inner diffusion layer.

[0010] Optionally, in the back-contact battery, the co-diffusion layer is disposed in the silicon substrate corresponding to the first region.

[0011] Optionally, in the back-contact battery, the co-diffusion layer is disposed in the silicon substrate corresponding to the second region.

[0012] Optionally, in the back-contact battery, the co-diffusion layer is disposed in the silicon substrate corresponding to the spacer region.

[0013] Optionally, in the back-contact battery, when the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the second inner diffusion layer is disposed in the silicon substrate corresponding to the second region, the silicon substrate corresponding to the spacer region, and the side wall of the silicon substrate at the junction of the first region and the spacer region.

[0014] Optionally, in the back-contact battery, when the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the first inner diffusion layer is disposed in the silicon substrate corresponding to the first region, the side wall of the silicon substrate at the junction of the first region and the spacer region, and the silicon substrate corresponding to the spacer region.

[0015] Optionally, in the back-contact battery, when the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the first inner diffusion layer is disposed in the silicon substrate corresponding to the first region, the side wall of the silicon substrate at the junction of the first region and the spacer region, and the silicon substrate corresponding to the spacer region, and the second inner diffusion layer is disposed in the silicon substrate corresponding to the spacer region and the silicon substrate corresponding to the second region.

[0016] Optionally, in the back-contact battery, the doping elements of the co-diffusion layer include at least one P-type doping element and at least one N-type doping element.

[0017] Optionally, in the back-contact battery, the concentration of N-type doping elements in the co-diffusion layer is greater than the concentration of P-type doping elements, and the majority carriers in the PN co-diffusion layer are electrons.

[0018] Optionally, in the back-contact battery, the concentration of P-type doping elements on the back surface of the co-diffusion layer is greater than 2×10 19 cm -3 and the concentration of N-type doping elements on the back surface is greater than 1×10 20 cm-3 。

[0019] Optionally, in the back contact cell, the width of the co - diffusion layer is 2 - 80 nm.

[0020] Optionally, in the back contact cell, the thickness of the second inner diffusion layer in the spacer region is less than or equal to the thickness of the second inner diffusion layer in the second region.

[0021] Optionally, in the back contact cell, the thickness of the P - type inner diffusion layer in the first inner diffusion layer and the second inner diffusion layer is 5 - 100 nm, and the thickness of the N - type inner diffusion layer in the first inner diffusion layer and the second inner diffusion layer is 3 - 90 nm.

[0022] Optionally, in the back contact cell, one side of the first doping layer facing the spacer region protrudes and has a brim structure.

[0023] Optionally, the back contact cell further includes a passivation layer, a first electrode and a second electrode. The passivation layer is disposed on the surfaces of the first doping layer, the spacer region and the second doping layer, and the first electrode and the second electrode are disposed on the surface of the passivation layer and are respectively electrically connected to the first doping layer and the second doping layer.

[0024] The present invention provides a method for manufacturing a back contact cell, which includes:

[0025] Providing a silicon substrate, the back surface of the silicon substrate includes a first region, a second region and a spacer region. The first region and the second region are alternately arranged, and a spacer region is arranged between the first region and the second region;

[0026] Sequentially forming a first tunneling layer and a first doping layer on the back surface of the silicon substrate, and simultaneously forming a first inner diffusion layer in the silicon substrate;

[0027] Removing the first doping layer, the first tunneling layer on the spacer region and the second region, and removing the first inner diffusion layer in the silicon substrate corresponding to the second region or removing the first inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region;

[0028] Forming a second tunneling layer and a second doping layer on the back surface of the silicon substrate, and simultaneously forming a second inner diffusion layer in the silicon substrate corresponding to the second region, or forming a second inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region. Wherein, the first inner diffusion layer and the second inner diffusion layer are electrically connected, the conduction types of the first doping layer and the second doping layer are opposite, the conduction types of the first inner diffusion layer and the first doping layer are the same, and the conduction types of the second inner diffusion layer and the second doping layer are the same;

[0029] Remove the second doping layer and the second tunneling layer on the first region and the spacer region.

[0030] Optionally, after removing the first doping layer and the first tunneling layer on the spacer region and the second region, the method further includes:

[0031] Form a second tunneling layer and a second doping layer on the back surface of the silicon substrate, and at the same time form a second inner diffusion layer in the silicon substrate corresponding to the second region, or form a second inner diffusion layer in the silicon substrates corresponding to the second region and the spacer region, and form a co-diffusion layer by inner diffusion on the side of the second inner diffusion layer close to the first inner diffusion layer.

[0032] The present invention also provides a photovoltaic module, which includes a cover plate, a back plate, and a back contact cell disposed between the cover plate and the back plate. The back contact cell is the above-mentioned back contact cell, or the back contact cell is a back contact cell prepared by the above-mentioned preparation method.

[0033] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0034] In the embodiments of the present invention, a first inner diffusion layer having the same conductivity type as the first doping layer and / or a second inner diffusion layer having the same conductivity type as the second doping layer are disposed in the spacer region for forming an isolation region on the back surface of the silicon substrate, and the first inner diffusion layer and the second inner diffusion layer are electrically connected. This can not only achieve the field passivation effect and effectively reduce the recombination of minority carriers in the isolation region, but also reverse-conduct when the cell is shaded, avoid being broken down, and effectively achieve the anti-thermal spot effect.

[0035] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present invention;

[0037] Figure 2 is a schematic structural diagram of a solar cell provided by an embodiment of the present invention;

[0038] Figure 3 is a schematic structural diagram of a solar cell provided by another embodiment of the present invention;

[0039] Figure 4 is a schematic structural diagram of a solar cell provided by yet another embodiment of the present invention;

[0040] Figure 5 is a schematic structural diagram of a solar cell provided by still another embodiment of the present invention;

[0041] Figure 6 It is a flowchart of a method for manufacturing a solar cell provided by an embodiment of the present invention;

[0042] Figure 7 It is a schematic diagram of a silicon substrate structure provided by an embodiment of the present invention;

[0043] Figure 8 It is a schematic diagram of a first manufacturing state of a solar cell in an embodiment of the present invention;

[0044] Figure 9 It is a schematic diagram of a second manufacturing state of a solar cell in an embodiment of the present invention;

[0045] Figure 10 It is a schematic diagram of a third manufacturing state of a solar cell in an embodiment of the present invention;

[0046] Figure 11 It is a schematic diagram of a fourth manufacturing state of a solar cell in an embodiment of the present invention;

[0047] Figure 12 It is a schematic diagram of a fifth manufacturing state of a solar cell in an embodiment of the present invention;

[0048] Figure 13 It is a schematic diagram of a sixth manufacturing state of a solar cell in an embodiment of the present invention;

[0049] Figure 14 It is a schematic diagram of the structure of a solar cell prepared according to an embodiment of the present invention. Detailed implementation manners

[0050] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0051] Currently, there is a serious hot spot risk when a BC cell is shaded. And in the prior art, using an external diode to reduce the hot spot risk will increase the production cost.

[0052] An embodiment of the present invention provides a solar cell to solve the above problems. Among them, as Figures 1 - 3 shown, it includes a silicon substrate 101, a first inner diffusion layer 102, a first tunneling layer 103, a first doping layer 104, a second inner diffusion layer 108, a second tunneling layer 109, and a second doping layer 110.

[0053] Among them, the back surface of the silicon substrate 101 includes a first region 112, a second region 114, and a spacer region 113. The first region 112 and the second region 114 are alternately arranged (as Figure 2As shown, there is a spaced area 113 between the first area 112 and the second area 114. A first tunneling layer 103 and a first doping layer 104 are sequentially disposed on the first area 112, and a second tunneling layer 109 and a second doping layer 110 are sequentially disposed on the second area 114. Among them, the conduction types of the first doping layer 104 and the second doping layer 110 are different.

[0054] Among them, a first inner diffusion layer 102 is disposed in the silicon substrate 101 corresponding to the first area 112, a second inner diffusion layer 108 is disposed in the silicon substrate 101 corresponding to the second area 114, and a first inner diffusion layer 102 and / or a second inner diffusion layer 108 are disposed in the silicon substrate 101 corresponding to the spaced area 113. The first inner diffusion layer 102 and the second inner diffusion layer 108 are electrically connected. Among them, the conduction types of the first inner diffusion layer 102 and the first doping layer 104 are the same, and the conduction types of the second inner diffusion layer 108 and the second doping layer 110 are the same. That is, if the first doping layer 104 is one of a P-type doping layer and an N-type doping layer, then the first inner diffusion layer 102 is one of a P-type inner diffusion layer and an N-type inner diffusion layer, the second doping layer 110 is the other of a P-type doping layer and an N-type doping layer, and the second inner diffusion layer 108 is the other of a P-type inner diffusion layer and an N-type inner diffusion layer.

[0055] It can be understood that the overlap of the first inner diffusion layer 102 and the second inner diffusion layer 108 means that there is a contact area between the first inner diffusion layer 102 and the second inner diffusion layer 108, realizing electrical connection.

[0056] Optionally, in an embodiment, a common diffusion layer 107 is further disposed in the silicon substrate 101. The common diffusion layer 107 is disposed between the first inner diffusion layer 102 and the second inner diffusion layer 108, and the common diffusion layer 107 is used to conduct the electrical connection between the first inner diffusion layer 102 and the second inner diffusion layer 108. In this embodiment, the common diffusion layer 107 is disposed between the first inner diffusion layer 102 and the second inner diffusion layer 108 and contacts both of them, which can form a graded tunnel junction or a quasi-tunnel junction structure. It can not only achieve the effect of improving hot spots, but also effectively extract minority carriers in the graded tunnel junction or the quasi-tunnel junction, thereby reducing the recombination in this area.

[0057] For example, the first inner diffusion layer 102 is disposed within the silicon substrate 101 corresponding to the first region 112, the second inner diffusion layer 108 is disposed within the silicon substrate 101 corresponding to the spacer region 113 and the second region 114, and the common diffusion layer 107 is disposed within the silicon substrate 101 corresponding to the first region 112. The common diffusion layer 107 overlaps with the first inner diffusion layer 102 and the second inner diffusion layer 108, that is, the common diffusion layer 107 is disposed on the side of the first region 112 close to the spacer region 113, specifically disposed between the first inner diffusion layer 102 and the second inner diffusion layer 108 and in contact with both of them, which can form a graded tunnel junction or a tunnel-like junction structure, not only achieving the effect of improving hot spots, but also effectively extracting minority carriers in the graded tunnel junction or the tunnel-like junction, thereby reducing the recombination in this region.

[0058] It can be understood that there is a partially overlapping region between the first inner diffusion layer 102 and the second inner diffusion layer 108, and this overlapping region is the common diffusion layer 107.

[0059] In the embodiment of the present invention, the above-mentioned first region 112 and the second region 114 are arranged at intervals, and the spacer region 113 is the region between the first region 112 and the second region 114. The first region 112 is used to form a first functional region, the spacer region 113 is used to form an isolation region, the second region 114 is used to form a second functional region, the first functional region is one of a P-type functional region and an N-type functional region, and the second functional region is the other of the P-type functional region and the N-type functional region. Exemplarily, if the first region 112 is used to form a P-type functional region, then the second region is used to form an N-type functional region.

[0060] Optionally, in one implementation, the first region 112 and the second region 114 are arranged at intervals in a finger-like manner, such that the solar cell provided by the embodiment of the present invention is an Interdigitated Back Contact (IBC) cell.

[0061] In the embodiment of the present invention, the above-mentioned first tunneling layer 103 and the first doping layer 104 are sequentially stacked on the surfaces of the first inner diffusion layer 102 and the common diffusion layer 107, thereby forming the above-mentioned first functional region; the above-mentioned second tunneling layer 109 and the second doping layer 110 are sequentially stacked on the surface of the second inner diffusion layer 108 in the second region 114, thereby forming the above-mentioned second functional region.

[0062] Among them, the first inner diffusion layer 102 is a gradient doping region formed by diffusion on the silicon substrate surface when doping to form the first doping layer 104 through the first tunneling layer 103; the second inner diffusion layer 108 is a gradient doping region formed by diffusion on the silicon substrate surface when doping to form the second doping layer 110 through the second tunneling layer 109.

[0063] In an embodiment of the present invention, a first inner diffusion layer 102 having the same conductivity type as the first doping layer 104 and / or a second inner diffusion layer 108 having the same conductivity type as the second doping layer 110 are provided in the spacer region 113 on the back surface of the silicon substrate 101 for forming the isolation region, and the first inner diffusion layer 102 and the second inner diffusion layer 108 are electrically connected. This can not only achieve a field passivation effect via the first inner diffusion layer 102 and the second inner diffusion layer 108, effectively reducing the recombination of minority carriers in the isolation region, but also achieve reverse conduction when the solar cell is shaded, avoiding breakdown and effectively realizing the anti-thermal spot effect.

[0064] Among them, the above-mentioned co-diffusion layer 107 can be formed by diffusion on the first inner diffusion layer 102 when doping to form the second doping layer 110, or formed by diffusion on the second inner diffusion layer 108 when doping to form the first doping layer 104.

[0065] In the manufacturing process of the Tunnel Back Contact (TBC) solar cell, by precisely controlling the in-situ diffusion of doping elements, a graded tunnel junction or a tunnel-like junction structure is formed between the first inner diffusion layer 102 and the second inner diffusion layer 108 to directly generate an electrical contact. Through band engineering, the tunneling transport of carriers is induced, significantly reducing the barrier height under reverse bias, thereby reducing the reverse breakdown voltage of the solar cell to a safe threshold (such as below 15V), achieving reverse conduction similar to that of a diode, that is, avoiding breakdown of the solar cell, and the spacer region 113 retains the field passivation effect of the first inner diffusion layer 102 and / or the second inner diffusion layer 108, effectively reducing the recombination of minority carriers in the isolation region. Therefore, the solar cell in the embodiment of the present invention can retain the advantages of high conversion efficiency and low recombination loss while avoiding the thermal spot risk caused by high reverse voltage, providing double guarantees for the reliability and economy of photovoltaic modules.

[0066] Therefore, the solar cell provided by the embodiment of the present invention can be compatible with the existing Tunnel Back Contact (TBC) solar cell process flow, without adding new mask, deposition or etching steps, realizing the optimization of the reverse characteristics with zero process increment.

[0067] In an embodiment of the present invention, the silicon substrate 101 is provided with a first inner diffusion layer 102 in the first region 112, the silicon substrate 101 is provided with a second inner diffusion layer 108 in the second region 114, the silicon substrate 101 is provided with a first inner diffusion layer 102 and / or a second inner diffusion layer 108 in the spacer region 113, and the co-diffusion layer 107 is disposed between the first inner diffusion layer 102 and the second inner diffusion layer 108. Therefore, the co-diffusion layer can exist in the silicon substrate 101 corresponding to the first region 112, in the silicon substrate 101 corresponding to the spacer region 113, or in the silicon substrate 101 corresponding to the second region 114.

[0068] It can be understood that the side lap of the first inner expansion layer 102 and the second inner expansion layer 108 can be similar to the position of the co-expansion layer, that is, the side lap position can be within the silicon substrate 101 corresponding to the first region 112, or within the silicon substrate 101 corresponding to the spacer region 113, or within the silicon substrate 101 corresponding to the second region 114.

[0069] Optionally, in a specific embodiment, the second inner expansion layer 108 is disposed within the silicon substrate 101 corresponding to the spacer region 113 and the second region 114, and the first inner expansion layer 102 is disposed within the silicon substrate 101 corresponding to the first region 112. Then, the co-expansion layer 107 is disposed within the first region 112, and the co-expansion layer 107 overlaps with the first inner expansion layer 102 and the second inner expansion layer 108. Optionally, the co-expansion layer 107 can specifically be located on the side of the first inner expansion layer 102 close to the spacer region 113.

[0070] Optionally, in a more specific embodiment, as Figure 1 shown, when the silicon substrate corresponding to the first region is higher than the silicon substrate corresponding to the second region along the thickness direction of the silicon substrate (that is, the thickness of the silicon substrate corresponding to the second region is less than the thickness of the silicon substrate corresponding to the first region), a side wall of the silicon substrate 101 can be formed at the junction of the first region 112 and the spacer region 113. The second inner expansion layer 108 is also located within the silicon substrate 101 corresponding to the spacer region 113 and on the side wall of the silicon substrate at the junction of the first region 112 and the spacer region 113, such that the co-expansion layer 107 can be located on this side wall. Since the first tunneling layer 103 and the first doping layer 104 are sequentially stacked on the surfaces of the first inner expansion layer 102 and the co-expansion layer 107, an electrical contact can be formed between the back surface of the co-expansion layer 107 and the first doping layer 104 through the first tunneling layer 103, which can effectively separate the minority carriers (holes) in the graded tunnel junction or quasi-tunnel junction. The carriers collected by the first inner expansion layer 102 will be quickly collected by the strong electric field generated by the first doping layer 104, thereby separating electrons and holes and reducing the recombination loss of carriers. At the same time, since the second inner expansion layer 108 covers this side wall and overlaps with the co-expansion layer 107 at this side wall, a diode-like effect is formed at the side wall, which can conduct in the reverse direction when the solar cell is shaded, avoiding breakdown and effectively achieving the anti-thermal spot effect.

[0071] It can be understood that the position of the co-expansion layer 107 can be at the position as Figure 1 shown (that is, below the first tunneling layer 103). Or the co-expansion layer 107 can also be at other positions on the side wall of the silicon substrate at the junction of the silicon substrate corresponding to the first region 112 and the spacer region 113 in Figure 1 . In this case, the position of the first inner expansion layer 102 can be along the side wall downward and overlap with the second inner expansion layer 108 through this co-expansion layer 107.

[0072] In this embodiment, the passivation layer 105 not only covers the front surfaces of the first doped layer 104, the second inner diffusion layer 108 of the spacer region 113, and the second doped layer 110, but also covers the side surfaces of the first doped layer 104, the first dielectric layer (e.g., the first tunneling layer 103), the co-diffusion layer 107, the second doped layer 110, and the second dielectric layer (e.g., the second tunneling layer 109) facing the spacer region 113, which can achieve a better passivation effect.

[0073] In some embodiments, as Figure 3 shown, one side of the above-mentioned first doped layer 104 facing the spacer region 113 protrudes and has a brim structure. Among them, since wet etching is required after the doped silicon glass layer generated during the laser treatment doping process in the preparation process, the edge of the doped polysilicon after laser treatment will be further heavily doped under the influence of the high temperature of the laser. The heavily doped polysilicon is more resistant to etching by the alkaline solution, making it difficult to etch away this part of the doped polysilicon, so that one side of the above-mentioned first doped layer 104 facing the spacer region 113 protrudes and has a brim structure in the final product. Optionally, during the preparation process, the brim structure is affected by factors such as the laser treatment power and wet etching conditions, and the state of the brim structure can be adjusted by adjusting the laser power, wet etching time, concentration, etc.

[0074] Optionally, in another specific embodiment, a first inner diffusion layer 102 is provided in the silicon substrate corresponding to the spacer region 113 and the silicon substrate corresponding to the first region 112, and a second inner diffusion layer 108 is provided in the silicon substrate corresponding to the second region 114. Then, the co-diffusion layer 107 is provided in the silicon substrate corresponding to the second region 112, and the co-diffusion layer 107 is used for the overlap of the first inner diffusion layer 102 and the second inner diffusion layer 108. Optionally, the co-diffusion layer 107 may specifically be located on the side of the second inner diffusion layer 102 close to the spacer region 113.

[0075] Optionally, in a more specific embodiment, when the silicon substrate corresponding to the first region is higher than the silicon substrate corresponding to the second region along the thickness direction of the silicon substrate (i.e., the thickness of the silicon substrate corresponding to the second region is less than the thickness of the silicon substrate corresponding to the first region), as Figure 4As shown, a sidewall of the silicon substrate 101 can be formed at the junction of the first region 112 and the spacer region 113. The first inner expansion layer 102 is also located inside the silicon substrate 101 corresponding to the spacer region 113 and on the sidewall of the silicon substrate at the junction of the first region 112 and the spacer region 113, such that the co-expansion layer 107 can be located on the side of the second inner expansion layer 102 close to the spacer region 113. Since the second tunneling layer 109 and the second doping layer 110 are sequentially stacked on the surfaces of the second inner expansion layer 108 and the co-expansion layer 107, an electrical contact can be formed between the back surface of the co-expansion layer 107 and the second doping layer 110 through the second dielectric layer, which can effectively separate the minority carriers (holes) in the graded tunnel junction or quasi-tunnel junction, such that the carriers collected by the second inner expansion layer 108 will be quickly collected by the strong electric field generated by the second doping layer 110, thereby separating electrons and holes and reducing the recombination loss of carriers. At the same time, since the first inner expansion layer 102 covers the spacer region 113 and the above-mentioned sidewall and is overlapped with the second inner expansion layer 108 through the co-expansion layer 107, a function similar to that of a diode is formed, which can conduct in the reverse direction when the cell is shaded, avoiding breakdown and effectively achieving the anti-thermal spot effect.

[0076] Optionally, in another specific embodiment, when the silicon substrate corresponding to the first region is higher than the silicon substrate corresponding to the second region along the thickness direction of the silicon substrate (i.e., the thickness of the silicon substrate corresponding to the second region is less than the thickness of the silicon substrate corresponding to the first region), as Figure 5 shown, both the first inner expansion layer 102 and the second inner expansion layer 108 are provided in the spacer region 113 of the silicon substrate 101, and the first inner expansion layer 102 is provided both inside the silicon substrate corresponding to the first region 112 and on the sidewall of the silicon substrate at the junction of the first region 112 and the spacer region 113, and the second inner expansion layer 108 is also provided inside the silicon substrate corresponding to the second region 114. Then, the co-expansion layer 107 is provided in the spacer region 113, which can not only achieve a passivation effect by using the first inner expansion layer 102 and the second inner expansion layer 108 in the spacer region 113, thereby reducing the recombination loss of carriers; at the same time, since the first inner expansion layer 102 and the second inner expansion layer 108 in the spacer region 113 are overlapped through the co-expansion layer 107, a function similar to that of a diode is formed, which can conduct in the reverse direction when the cell is shaded, avoiding breakdown and effectively achieving the anti-thermal spot effect.

[0077] In the embodiments of the present invention, both the first tunneling layer 103 and the second tunneling layer 109 are tunneling dielectric layers, and the materials thereof can specifically be oxides, nitrides, oxynitrides, halides, carbides, silicon, etc. Optionally, in one embodiment, the first tunneling layer 103 and the second tunneling layer 109 include one or more of silicon oxide, aluminum oxide, titanium oxide, niobium oxide, boron oxide, gallium oxide, tin oxide, hafnium oxide, tantalum oxide, silicon nitride, silicon oxynitride, silicon carbide, lithium fluoride, magnesium fluoride, amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0078] Optionally, in one embodiment, the thicknesses of the first tunneling layer 103 and the second tunneling layer 109 are each 0.1 - 5 nm, which can effectively reduce interface recombination, inhibit chemical passivation or field-effect passivation of carriers on the battery surface, reduce the carrier transport barrier, and improve the selective contact efficiency. For example, the thicknesses of the first tunneling layer 103 and the second tunneling layer 109 can each be one of 0.1 nm, 0.2 nm, 0.5 nm, 0.8 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm or a range value between any two of them.

[0079] In the embodiments of the present invention, the first doping layer 104 can be one or more of single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, nanocrystalline silicon, and silicon oxide having a P-type doping element, and the doping elements specifically include one or more of boron, aluminum, gallium, indium, thallium, etc. The second doping layer 110 can be one or more of single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, nanocrystalline silicon, and silicon oxide having an N-type doping element, and the doping elements specifically include one or more of carbon, nitrogen, phosphorus, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium.

[0080] Optionally, in one embodiment, the carrier concentration of the first doping layer 104 is 2×10 19 ~1.5×10 20 cm -3 , and its thickness is 10 - 1500 nm, which can ensure that the carrier concentration of the first inner diffusion layer 102 can meet the anti-thermal spot requirement while ensuring the photoelectric conversion efficiency of the battery. For example, the carrier concentration of the first doping layer 104 is 2×10 19 cm -3 , 3×10 19 cm -3 , 5×10 19 cm -3 , 8×10 19 cm -3 , 1×10 20 cm -3 , 1.5×10 20 cm -3 or a range value between any two of them, and the thickness can be one of 10 nm, 15 nm, 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, 1000 nm, 1500 nm or a range value between any two of them.

[0081] In the embodiments of the present invention, the first inner diffusion layer 102 is an inner diffusion layer generated when doping the first doping layer 104, and the carrier concentration is greater than 10 19 cm -3region. Optionally, in one embodiment, the carrier concentration on the back surface of the first inner diffusion layer 102 is 2×10 19 ~1.5×10 20 cm -3 , which can effectively meet the characteristics of forming a similar tunnel junction.

[0082] Optionally, in one embodiment, since the first inner diffusion layer 102 is the inner diffusion layer generated during the deposition of the first doped layer 104, the doping element of the first inner diffusion layer 102 is the same as that of the first doped layer 104, and can also be one or more of single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, nanocrystalline silicon, and silicon oxide with P-type doping elements. The doping elements also include one or more of boron, aluminum, gallium, indium, thallium, etc.

[0083] Optionally, in one embodiment, the thickness d5 of the first inner diffusion layer 102 is 5 to 100 nm, which can effectively achieve the field passivation effect, ensure the hot spot improvement effect, and avoid serious Auger recombination caused by too thick inner diffusion layer, thus ensuring the battery efficiency.

[0084] Optionally, in one embodiment, the carrier concentration of the second doped layer 110 is 1×10 20 ~1.4×10 21 cm -3 , which can ensure that the carrier concentration of the second inner diffusion layer 108 can meet the hot spot prevention requirements on the premise of ensuring the photoelectric conversion efficiency of the battery.

[0085] In the embodiment of the present invention, the thickness of the second doped layer 110 is 10 to 1500 nm, and can be, for example, one of 10 nm, 15 nm, 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, 1000 nm, 1500 nm or a range value between any two of them.

[0086] Optionally, in one embodiment, since the second inner diffusion layer 108 is the inner diffusion layer generated during the doping of the second doped layer 110, the doping element of the second inner diffusion layer 108 is the same as that of the second doped layer 110, and can also be one or more of single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, nanocrystalline silicon, and silicon oxide with P-type doping elements. The doping elements also include one or more of carbon, nitrogen, phosphorus, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium, etc.

[0087] In the embodiment of the present invention, the second inner diffusion layer 108 is the inner diffusion layer generated during the deposition of the second doped layer 110, and the carrier concentration is greater than 10 19 cm -3 region. Optionally, in one embodiment, the carrier concentration on the back surface of the second inner diffusion layer 108 is 1×10 20 ~1.4×1021 cm -3 , which can effectively meet the characteristics of forming a similar tunnel junction and ensure the anti-thermal spot effect.

[0088] Optionally, in an embodiment, the thickness d3 of the second inner diffusion layer 108 is 3-90 nm; if the inner diffusion layer is too shallow, the field passivation effect is poor, and at the same time, the improvement effect of the thermal spot cannot be guaranteed; if the inner diffusion layer is too thick, it will cause serious Auger recombination and also affect the battery efficiency.

[0089] In the solar cell provided by the embodiment of the present invention, the doping elements of the co-diffusion layer 107 include at least one P-type doping element and at least one N-type doping element, that is, the co-diffusion layer 107 is formed by the common diffusion of P-type doping elements and N-type doping elements on the surface of the silicon substrate 101.

[0090] Optionally, in an embodiment, the above P-type doping elements include one or more of boron, aluminum, gallium, indium, thallium, etc., and the above N-type doping elements include one or more of carbon, nitrogen, phosphorus, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium.

[0091] In the solar cell provided by the embodiment of the present invention, the carrier concentrations of the P-type doping element and the N-type doping element in the co-diffusion layer 107 both reach 10 19 cm -3 or more regions.

[0092] Optionally, in an embodiment, the concentration of the N-type doping element in the co-diffusion layer 107 is greater than the concentration of the P-type doping element, and the majority carriers in the co-diffusion layer 107 are electrons.

[0093] Optionally, in an embodiment, the concentration of the P-type doping element on the back surface of the co-diffusion layer 107 is greater than 2×10 19 cm -3 , and the concentration of the N-type doping element on the back surface is greater than 1×10 20 cm -3 , that is, the minority carriers in the graded tunnel junction or quasi-tunnel junction can be effectively separated.

[0094] Optionally, in an embodiment, the width d4 of the co-diffusion layer 107 is 2-80 nm, for example, it can be 2 nm, 3 nm, 5 nm, 10 nm, 20 nm, 40 nm, 80 nm or a range value between any two of them. For example, electrical contact can be effectively formed with the first tunneling layer and the first doping layer 104.

[0095] Optionally, in one embodiment, the thickness of the co - diffusion layer 107 is the same as that of the first inner - diffusion layer 102, so that after the co - diffusion layer 107 diffuses to form the first inner - diffusion layer 102 during the deposition of the first doped layer 104, it can diffuse and form on the first inner - diffusion layer 102 during the deposition of the second doped layer 110.

[0096] It can be understood that the thickness of the co - diffusion layer 107 can also be the same as that of the second inner - diffusion layer 108, and the embodiments of the present application do not limit this.

[0097] Optionally, in another embodiment, the thickness of the second inner - diffusion layer 108 in the spacer region 113 is less than or equal to the thickness of the second inner - diffusion layer 108 in the second region 114, so as to avoid the electrical connection between the first doped layer and the second doped layer, and ensure that the spacer region formed by the spacer region 113 can effectively isolate the first functional region formed by the first region 112 and the second functional region formed by the second region 114.

[0098] Optionally, in one embodiment, the co - diffusion layer 107 can be one or more of single - crystal silicon, poly - silicon, micro - crystal silicon, nano - crystal silicon, and silicon oxide.

[0099] Optionally, in one embodiment, the second inner - diffusion layer 108 located in the spacer region 113 can be used as field passivation, which can effectively suppress the recombination of minority carriers (holes) on the back surface of the isolation region. Its width d1 is 20 - 500 μm. If its width is less than 20 μm, it will cause insufficient chemical passivation of the inner - diffusion layer field passivation and the passivation layer 105. If its width is greater than 500 μm, it will cause too large a lateral transfer resistance of the second inner - diffusion layer 108, and the resistance characteristics exceed the characteristics of the graded tunnel junction or quasi - tunnel junction, so that it cannot play the role of preventing hot spots. For example, the width d1 of the second inner - diffusion layer 108 in the spacer region 113 can be one of 20 μm, 30 μm, 50 μm, 100 μm, 200 μm, 300 μm, 500 μm or a range value between any two of them.

[0100] Optionally, in one embodiment, the length d2 of the second inner - diffusion layer 108 located in the first region 112 is 0 - 10 μm, which can avoid masking the characteristics of the graded tunnel junction or quasi - tunnel junction due to strong resistance characteristics.

[0101] In addition, the back - contact battery provided by the embodiments of the present invention further includes a passivation layer 105, a first electrode 106, and a second electrode 111; wherein, the passivation layer 105 is disposed on the surfaces of the first doped layer 104, the spacer region 113, and the second doped layer 110 to achieve the surface passivation effect; the first electrode 106 and the second electrode 111 are disposed on the surface of the passivation layer 105 and are respectively electrically connected to the first doped layer 104 and the second doped layer 110 to achieve metallization.

[0102] In an embodiment of the present invention, the material of the passivation layer 105 includes one or more of oxides, nitrides, oxynitrides, halides, carbides, and silicon, and its thickness is 5 to 1000 nm, which can effectively inhibit surface recombination, optimize carrier selective contact, and reduce the reverse saturation current, thereby improving the photoelectric conversion efficiency of the battery. Optionally, the passivation layer 105 is one or more of silicon oxide, aluminum oxide, titanium oxide, niobium oxide, boron oxide, phosphorus oxide, gallium oxide, tin oxide, hafnium oxide, tantalum oxide, indium oxide, tungsten oxide, zinc oxide, silicon nitride, silicon oxynitride, silicon carbide, lithium fluoride, magnesium fluoride, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, etc., and its thickness can be one of 5 nm, 6 nm, 10 nm, 20 nm, 50 nm, 100 nm, 200 nm, 500 nm, 1000 nm or a range value between any two of them.

[0103] In an embodiment of the present invention, the first electrode 106 is a positive metal grid line, and the second electrode is a negative metal grid line, and their materials can both be one or more of various metal elements such as silver, aluminum, chromium, copper, gold, nickel, and lead.

[0104] In an embodiment of the present invention, the above-mentioned silicon substrate 101 can be N-type or P-type, and the back surface of the silicon substrate 101 is a matte surface or a polished surface. Among them, setting the back surface of the silicon substrate 101 as a matte surface structure can increase the path length of incident light in the silicon substrate through the micron-scale pyramid or inverted pyramid morphology, and improve the light absorption efficiency; at the same time, the matte surface increases the surface area of the back, disperses the carrier transmission path, reduces the risk of local recombination, and improves the minority carrier lifetime. Among them, setting the back surface of the silicon substrate 101 as a polished surface structure has few surface defects, and the flat surface is more likely to achieve uniform coverage of the ultra-thin passivation layer 105, thereby reducing local leakage.

[0105] In an embodiment of the present invention, the above structure accounts for 5 to 50% of the back area of the battery cell, that is, the total area of the above-mentioned first region 112, the spacer region 113, and the second region 114 accounts for 5 to 50% of the back area of the silicon substrate 101. For example, it can be one of 5%, 10%, 20%, 30%, 40%, 50% or a range value between any two of them.

[0106] An embodiment of the present invention also provides a method for manufacturing a solar cell, as Figure 6 shown, including steps 201 to 205:

[0107] Step 201, provide a silicon substrate, the back surface of the silicon substrate includes a first region, a second region, and a spacer region, the first region and the second region are alternately arranged, and a spacer region is provided between the first region and the second region.

[0108] In this step, the above-mentioned silicon substrate can be N-type or P-type.

[0109] Step 202: Form a first tunneling layer and a first doping layer on the back surface of the silicon substrate in sequence, and simultaneously form a first inner diffusion layer in the silicon substrate.

[0110] In this step, as Figures 7 - 8 shown, first use methods such as Low Pressure Chemical Vapor Deposition (LPCVD) to deposit a first tunneling layer 103 and a first doping layer 104 on the back surface of the silicon substrate 101 in sequence. During the doping process of the first doping layer 104, due to the diffusion of the first doping element, a first inner diffusion layer 102 will be formed between the first tunneling layer 103 and the silicon substrate 101 at the same time.

[0111] In this first doping process, the first doping element includes one or more of boron, aluminum, gallium, indium, thallium, etc.; among them, if the first doping element includes boron, a borosilicate glass layer 115 will be formed on the surface at the same time.

[0112] Step 203: Remove the first doping layer and the first tunneling layer on the spacer region and the second region, and remove the first inner diffusion layer in the silicon substrate corresponding to the second region or remove the first inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region.

[0113] In this step, as Figure 9 shown, by means of laser patterning or photoresist patterning, remove the first doping layer 104 and the first tunneling layer 103 on the spacer region 113 and the second region 114, and remove the first inner diffusion layer 102 in the silicon substrate 101 corresponding to the second region 114 or remove the first inner diffusion layer 102 in the silicon substrate 101 corresponding to the second region 114 and the spacer region 113.

[0114] Among them, when removing the first inner diffusion layer 102 at the corresponding region, remove the adjacent part of the silicon substrate 101 to ensure that there is no residue of the first inner diffusion layer 102 at this region.

[0115] In this step, it can be to only remove the first inner diffusion layer 102 at part of the second region 114 while retaining the first inner diffusion layer 102 at the first region 112 and the spacer region 113; it can also be to remove the first inner diffusion layer 102 at all of the second region 114 while retaining the first inner diffusion layer 102 at the first region 112 and the spacer region 113; it can also be to remove the first inner diffusion layer 102 at all of the second region 114 and the spacer region 113 while only retaining the first inner diffusion layer 102 at the first region 112.

[0116] Wherein, if the first doping element is boron, it is also necessary to remove the borosilicate glass layer 115 at the back spacer region 113 and the second region 114 of the silicon substrate 101.

[0117] Step 204: Form a second tunneling layer and a second doping layer on the back of the silicon substrate, and at the same time form a second inner diffusion layer in the silicon substrate corresponding to the second region, or form a second inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region, wherein the first inner diffusion layer and the second inner diffusion layer are electrically connected, the conduction types of the first doping layer and the second doping layer are opposite, the conduction types of the first inner diffusion layer and the first doping layer are the same, and the conduction types of the second inner diffusion layer and the second doping layer are the same.

[0118] In this step, as Figure 10 shown, after removing the first inner diffusion layer 102 in the silicon substrate 101 corresponding to the second region 114 or removing the first inner diffusion layer 102 in the silicon substrate 101 corresponding to the second region 114 and the spacer region 113, by means of low-pressure chemical vapor deposition (LPCVD) or the like, a second tunneling layer 109 and a second doping layer 110 are sequentially deposited on the back of the silicon substrate 101. During the doping process of the second doping layer 110, due to the diffusion of the second doping element, a second inner diffusion layer 108 will be formed between the second tunneling layer 109 and the silicon substrate 101 at the same time.

[0119] Step 205: Remove the second doping layer and the second tunneling layer on the first region and the spacer region.

[0120] In this step, as Figure 11 shown, by means of laser patterning or photoresist patterning, the second doping layer 110 and the second tunneling layer 109 in the first region 112 and the spacer region 113 (the regions other than those for forming the second functional region, that is, the isolation region and the first functional region) are removed, so as to isolate the first doping layer 104 and the second doping layer 110, and at least retain the second inner diffusion layer 108 at the region where the first inner diffusion layer has been removed.

[0121] Among them, additives can be used to protect the inner expansion layer from being completely etched away, and the second inner expansion layer 108 at the area where the first inner expansion layer 102 has been removed in the first region 112, the spacer region 113 (isolation region), and the second region 114 is retained; specifically, a highly protective organic molecule such as a surfactant with an ammonium group can be used to protect the tunneling oxygen in the isolation region, so as to completely protect the second inner expansion layer 108 at the area where the first inner expansion layer 102 has been removed in the first region 112, the spacer region 113 (isolation region), and the second region 114; in addition, a modified additive can be used to further modify the isolation region on the basis of strong protection, and the etching depth of the isolation region can be adjusted according to parameters such as etching time and concentration, and the etching depth can be adjusted within the range of 0 to 2 μm, so as to achieve the purpose of retaining the second inner expansion layer 108 at the area where the first inner expansion layer 102 has been removed in the first region 112, the spacer region 113 (isolation region), and the second region 114.

[0122] Among them, if the first doping element is boron and the second doping element is phosphorus, it is also necessary to first remove the phosphosilicate glass layer 116 at the first region 112 and the spacer region 113 by means of laser patterning or photoresist patterning, and then sequentially remove the second doping layer 110 and the second tunneling layer 109 at the first region 112 and the spacer region 113, specifically as Figure 12 shown.

[0123] It can be understood that, as Figure 10 and Figure 11 shown, step 205 further includes removing the second doping layer on the first region, the second tunneling layer, and the second doping layer and the second tunneling layer on the side of the first inner expansion layer.

[0124] Optionally, for the method provided by the embodiments of the present invention, after the above step 204, the method further includes the steps of:

[0125] forming a second tunneling layer and a second doping layer on the back surface of the silicon substrate, and simultaneously forming a second inner expansion layer in the silicon substrate corresponding to the second region, or forming a second inner expansion layer in the silicon substrate corresponding to the second region and the spacer region, and the second inner expansion layer and the first inner expansion layer overlap to form a co-expansion layer.

[0126] In this step, a first inner expansion layer 102 is first formed in the silicon substrate 101 corresponding to the first region 112, or a first inner expansion layer 102 is formed in the silicon substrate 101 corresponding to the first region 112 and the spacer region 113, and then a second doping layer 110 is formed by up-diffusion on the back surface of the silicon substrate 101. During the doping process of the second doping layer 110, due to the diffusion of the second doping element, not only a second inner expansion layer 108 is formed, but also a co-expansion layer 107 is formed by inner expansion on the side of the first inner expansion layer 102 close to the second inner expansion layer 108.

[0127] Optionally, when the first inner diffusion layer 102 also exists in the spacer region 113 and the second region, during the doping process of the second doping layer 110, due to the diffusion of the second doping element, a co-diffusion layer 107 will also be formed by inner diffusion on the side of the first inner diffusion layer 102 close to the second inner diffusion layer 108.

[0128] Based on the different ranges of the first inner diffusion layer 102 retained in step 202, the position of the co-diffusion layer 107 is also different.

[0129] Among them, when removing all the first inner diffusion layer 10 in the second region 114 and the spacer region 113, the first inner diffusion layer 102 only exists at the silicon substrate in the first region, and the co-diffusion layer 107 is formed in the silicon substrate of the first region 112; when only removing part of the first inner diffusion layer 102 in the second region 114, then the first inner diffusion layer 102 exists at the silicon substrates in the first region and the spacer region, and the co-diffusion layer 107 can be formed in the silicon substrate of the second region 112; when removing all the first inner diffusion layer 102 in the second region 114 and the spacer region 113, and only retaining the first inner diffusion layer 102 in the first region 112, the co-diffusion layer 107 is formed in the silicon substrate of the spacer region 113.

[0130] Among them, during the formation process of the second doping layer 110, the second doping element includes one or more of carbon, nitrogen, phosphorus, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium, etc.; among them, if the second element includes phosphorus, a phosphosilicate glass layer 116 will be formed on the surface at the same time.

[0131] Optionally, the method provided by the embodiment of the present invention, after the above step 204, further includes the steps:

[0132] After removing the second doping layer and the second tunneling layer on the first region and the spacer region, a passivation layer, a first electrode conducting with the first doping layer, and a second electrode conducting with the second doping layer are deposited on the back surface of the silicon substrate.

[0133] In this step, as Figure 13 shown, after removing the second doping layer 110 and the second tunneling layer 109 in the first region 112 and the spacer region 113, a passivation layer 105 is deposited on the back surface of the battery. The atomic layer deposition (ALD) process is used to coat the entire back surface of the product as the passivation layer 105 to form field passivation.

[0134] Optionally, the above passivation layer 105 is an alumina film layer, that is, by coating an alumina film layer on the entire back surface as the above passivation layer 105; optionally, an alumina film layer is coated on the entire front surface as the above passivation layer 105, and the thickness of the above passivation layer 105 can be 1-10 nm.

[0135] Wherein, if the first doping element is boron and the second doping element is phosphorus, after removing the second doping layer 110 and the second tunneling layer 109 in the first region 112 and the spacer region 113, it is also necessary to first remove the borosilicate glass layer 115 in the first region 112 and the phosphosilicate glass layer 116 in the second region 114 by means of laser patterning or photoresist patterning, so as to expose the first doping layer 104 in the first region 112 and the second doping layer in the second region 114.

[0136] Optionally, after forming the passivation layer 105, a plasma enhanced chemical vapor deposition (PECVD) process can also be used to deposit an antireflection film layer on the back of the battery, and then deposit an antireflection film layer on the front, further improving the passivation effect of the battery cell.

[0137] Optionally, the above-mentioned back antireflection film layer can be a silicon nitride layer with a thickness of 50 - 120 nm, that is, a silicon nitride layer is deposited on the entire back as the above-mentioned back antireflection film;

[0138] Optionally, the above-mentioned front antireflection film layer can be a silicon nitride film, or a stack of silicon nitride and silicon oxide, or a silicon oxynitride layer, with a thickness of 50 - 120 nm, which can further improve the antireflection effect.

[0139] In this step 207, as Figure 14 shown, the first electrode 106 (positive grid line) electrically connected to the first doping layer 104 and the second electrode 111 (negative grid line) electrically connected to the second doping layer 110 are deposited by means of screen printing, evaporation, copper electroplating, zero busbar (0BB), etc., and then high-temperature sintering is carried out, thus a solar cell can be fabricated.

[0140] In the preparation method provided by the embodiments of the present invention, by precisely controlling the in-situ diffusion of doping elements, a graded tunnel junction or a tunnel-like junction structure is formed between the first inner diffusion layer 102 and the second inner diffusion layer 108, directly generating an electrical contact. Through band engineering, the tunneling transport of carriers is induced, significantly reducing the barrier height under reverse bias, thereby reducing the reverse breakdown voltage of the battery to a safe threshold (such as below 15V), achieving reverse conduction similar to that of a diode, that is, avoiding the breakdown of the battery. Moreover, the spacer region 113 retains the second inner diffusion layer 108 with a field passivation effect, effectively reducing the recombination of minority carriers in the isolation region. Therefore, the preparation method provided by the embodiments of the present invention can be compatible with the existing Tunnel Back Contact (TBC) battery process flow, without adding new mask, deposition, or etching steps. The prepared solar cell can retain the advantages of high conversion efficiency and low recombination loss while avoiding the hot spot risk caused by high reverse voltage, achieving the optimization of the reverse characteristics with zero process increment, providing double guarantees for the reliability and economy of photovoltaic modules.

[0141] Optionally, in the embodiments of the present invention, the boron silicate glass layer 115 or the phosphosilicate glass layer 116 can be directionally removed by means of photolithography of photoresist in combination with chain pickling. Optionally, the boron silicate glass layer 115 and the phosphosilicate glass layer 116 are directionally removed by chain pickling of the boron-doped silicon wafer with hydrofluoric acid having a mass percentage of 5-30%. Optionally, the boron silicate glass layer 115 and the phosphosilicate glass layer 116 are directionally removed by cleaning with hydrofluoric acid having a mass percentage of 5-30% and O3.

[0142] Optionally, in one implementation manner, before the above step 201, the preparation method provided by the embodiments of the present invention further includes the step of:

[0143] Texturing or polishing the back surface of the silicon substrate 101.

[0144] In this implementation manner, before forming the first tunneling oxide layer and doping to form the first doped layer 104, the silicon wafer is textured or polished; among them, texturing can remove the mechanical damage layer and metal ions on the surface of the original silicon wafer, form a "pyramid" appearance on the battery surface, improve the light trapping effect of the battery, and at the same time, the textured surface increases the surface area of the back surface, disperses the carrier transport path, reduces the local recombination risk, and improves the minority carrier lifetime; while polishing can eliminate the organic contamination and metal impurities on the surface of the silicon wafer.

[0145] Optionally, texturing treatment is achieved by treating the back surface of the grooved alkali-treated silicon substrate 101; wherein, the texturing solution in the texturing tank mainly includes an acid and an alkali solution, and the texturing treatment specifically includes: first performing alkali texturing with the alkali solution, and then performing pickling treatment with the acid solution; wherein, the alkali solution includes NaOH or KOH, and the solution mass ratio is 0.5-1.2%; the acid solution is HCL or HF, and the solution mass ratio is 0.5-1.2%; the above texturing duration is between 550-650 s.

[0146] Optionally, double-sided polishing of the silicon substrate 101 is performed by trough-type alkali polishing. The alkali polishing solution includes water, an alkali polishing additive, and 1%-10% NaOH or KOH by mass percentage, and the treatment time is 50 s-250 s.

[0147] The present invention also provides a photovoltaic module, which includes a cover plate, a back plate, and a back contact battery disposed between the cover plate and the back plate. The back contact battery is the above-mentioned back contact battery, or the back contact battery is the back contact battery prepared by the above-mentioned preparation method.

[0148] The present invention will be described in detail below through examples.

[0149] Test method

[0150] (1) Battery efficiency test:

[0151] The battery efficiency test is a conventional IV test method. One example is: using a transient light source, the scanning voltage range is -50 mV to 800 mV, the test time is 150 ms, and the number of test voltage points is 500.

[0152] (2) Battery hot spot test:

[0153] When performing the hot spot test, a steady-state light source (AM 1.5G) is used to apply a reverse bias voltage to the battery so that the reverse current of the battery reaches the current value corresponding to the maximum power point of the battery, and the temperature of the battery cell is detected when the bias voltage is continuously applied for 10 minutes. The detection method is not limited to infrared detection.

[0154] It should be noted that the same terms in the following examples are the same as those in the previous embodiments. To avoid repetition, the following embodiments will not be described repeatedly.

[0155] Example 1

[0156] A solar cell is fabricated using an N-type silicon substrate with a resistivity of 12 Ω·m.

[0157] Among them, 20% of the area of the back surface of the silicon substrate has a battery cell structure as Figure 1 shown;

[0158] The thickness d5 of the first inner diffusion layer is 50 nm, the doping element is boron, and the back surface carrier concentration is 5×10 19 cm -3 ; the thickness d3 of the second inner diffusion layer is 30 nm, the doping element is phosphorus, and the back surface carrier concentration is 5×10 20 cm -3 ; the width d4 of the PN co-diffusion layer is 25 nm;

[0159] The width d1 of the second inner diffusion layer in the spacer region is 100 μm, and the length d2 of the second inner diffusion layer in the first region is 2 μm;

[0160] Both the first tunneling layer and the second tunneling layer are silicon oxide, and the thickness of both is 1.5 nm;

[0161] The first doping layer is boron-doped polysilicon, and the carrier concentration is 5×10 19 cm -3 ;

[0162] The second doping layer is phosphorus-doped polysilicon, and the carrier concentration is 6×10 20 cm -3 ;

[0163] The passivation layer is a stack of silicon nitride and aluminum oxide, the thickness of aluminum oxide is 5 nm, and the thickness of silicon nitride is 80 nm;

[0164] Both the first electrode and the second electrode are metal silver electrodes.

[0165] Example 2: The difference from Example 1 is that the thickness d5 of the first inner diffusion layer is adjusted to 30 nm.

[0166] Example 3: The difference from Example 1 is that the thickness d5 of the first inner diffusion layer is adjusted to 70 nm.

[0167] Example 4: The difference from Example 1 is that the back surface carrier concentration of the first inner diffusion layer is adjusted to 2×10 19 cm -3 , and the carrier concentration of the first doping layer is 2×10 19 cm -3 .

[0168] Example 5: The difference from Example 1 is that the back surface carrier concentration of the first inner diffusion layer is adjusted to 8×10 19 cm -3 , and the carrier concentration of the first doping layer is 8×10 19 cm -3 .

[0169] Example 6: The difference from Example 1 is that the width d1 of the second inner diffusion layer in the spacer region is adjusted to 50 μm.

[0170] Example 7: The difference from Example 1 is that the width d1 of the second inner expansion layer in the spacer region is adjusted to 200 μm.

[0171] Example 8: The difference from Example 1 is that 5% of the area on the back of the silicon substrate is adjusted to have the cell structure as Figure 1 shown.

[0172] Example 9: The difference from Example 1 is that 50% of the area on the back of the silicon substrate is adjusted to have the cell structure as Figure 1 shown.

[0173] Comparative Example 1: The difference from Example 1 is that the back of the silicon substrate is adjusted to have no cell structure as Figure 1 shown.

[0174] The efficiency and hot spot tests were carried out on the solar cells prepared in the above examples and comparative examples, and the results are shown in Table 1:

[0175] Table 1

[0176] Battery efficiency (%) Actual bias voltage applied to the battery cell (V) Average temperature of the battery cell (°C) Comparative example 26.65 15 181 Example 1 26.59 4.3 72 Example 2 26.63 12.1 131 Example 3 26.49 3.1 68 Example 4 26.64 13.5 155 Example 5 26.51 3.8 70 Example 6 26.54 3.7 69 Example 7 26.62 6.2 123 Example 8 26.61 6.5 122 Example 9 26.55 3.6 67

[0177] In summary, in this embodiment, by providing a first inner expansion layer having the same conductivity type as the first doping layer and / or a second inner expansion layer having the same conductivity type as the second doping layer in the spacer region on the back of the silicon substrate for forming the isolation region, and electrically connecting the first inner expansion layer and the second inner expansion layer, not only can the field passivation effect be achieved, effectively reducing the recombination of minority carriers in the isolation region, but also the reverse conduction can be achieved when the cell is shaded, avoiding breakdown, and effectively realizing the anti-hot spot effect; therefore, the solar cell in the embodiment of the present invention can retain the advantages of high conversion efficiency and low recombination loss while avoiding the hot spot risk caused by high reverse voltage, providing double guarantees for the reliability and economy of the photovoltaic module.

[0178] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0179] The above provides a detailed introduction to a solar cell, its manufacturing method, and a photovoltaic module provided by the present invention. Specific examples are used herein to illustrate the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A back-contact battery, characterized in that, It includes a silicon substrate, a first inner diffusion layer, a second inner diffusion layer, a first tunneling layer, a second tunneling layer, a first doping layer, and a second doping layer; The back surface of the silicon substrate includes a first region, a second region, and a spacer region. The first region and the second region are arranged alternately, and a spacer region is provided between the first region and the second region. A first tunneling layer and a first doping layer are sequentially provided on the first region, and a second tunneling layer and a second doping layer are sequentially provided on the second region. Among them, the conduction types of the first doping layer and the second doping layer are opposite; The first inner diffusion layer is provided in the silicon substrate corresponding to the first region, the second inner diffusion layer is provided in the silicon substrate corresponding to the second region, the first inner diffusion layer and / or the second inner diffusion layer is provided in the silicon substrate corresponding to the spacer region, and the first inner diffusion layer and the second inner diffusion layer are electrically connected. Among them, the conduction types of the first inner diffusion layer and the first doping layer are the same, and the conduction types of the second inner diffusion layer and the second doping layer are the same.

2. The back contact battery according to claim 1, characterized in that, A common diffusion layer is further provided in the silicon substrate, and the common diffusion layer is provided between the first inner diffusion layer and the second inner diffusion layer, and the common diffusion layer is used to conduct the electrical connection between the first inner diffusion layer and the second inner diffusion layer.

3. The back-contact battery according to claim 2, wherein The common diffusion layer is provided in the silicon substrate corresponding to the first region.

4. The back-contact battery according to claim 2, characterized in that, The common diffusion layer is provided in the silicon substrate corresponding to the second region.

5. The back-contact battery according to claim 2, wherein, The common diffusion layer is provided in the silicon substrate corresponding to the spacer region.

6. The back-contact battery according to claim 3, characterized in that, When the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the second inner diffusion layer is provided in the silicon substrate corresponding to the second region, the silicon substrate corresponding to the spacer region, and the side wall of the silicon substrate at the junction of the first region and the spacer region.

7. The back-contact battery according to claim 4, characterized in that, When the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the first inner diffusion layer is provided in the silicon substrate corresponding to the first region, the side wall of the silicon substrate at the junction of the first region and the spacer region, and the silicon substrate corresponding to the spacer region.

8. The back-contact battery according to claim 5, wherein, When the first inner diffusion layer is higher than the second inner diffusion layer in the thickness direction of the silicon substrate, the first inner diffusion layer is provided in the silicon substrate corresponding to the first region, the side wall of the silicon substrate at the junction of the first region and the spacer region, and the silicon substrate corresponding to the spacer region, and the second inner diffusion layer is provided in the silicon substrate corresponding to the spacer region and the silicon substrate corresponding to the second region.

9. The back-contact battery according to claim 2, characterized in that, The doping elements of the common diffusion layer include at least one P-type doping element and at least one N-type doping element.

10. The back contact battery according to claim 2, characterized in that, The concentration of N-type doping elements in the common diffusion layer is greater than the concentration of P-type doping elements, and the majority carriers in the common diffusion layer are electrons.

11. The back contact battery according to claim 10, characterized in that, The P-type doping element concentration on the back surface of the co-diffusion layer is greater than 2×10 19 cm -3 , and the N-type doping element concentration on the back surface is greater than 1×10 20 cm -3 .

12. The back-contact battery according to claim 2, characterized in that, The width of the common diffusion layer is 2 - 80 nm.

13. The back contact battery according to claim 1, wherein, The thickness of the P-type inner diffusion layer in the first inner diffusion layer and the second inner diffusion layer is 5 - 100 nm, and the thickness of the N-type inner diffusion layer in the first inner diffusion layer and the second inner diffusion layer is 3 - 90 nm.

14. The back-contact battery according to claim 1, characterized in that, One side of the first doping layer facing the spacing region protrudes and has a brim structure.

15. The back-contact battery according to any one of claims 1 to 14, characterized in that, Further included are a passivation layer, a first electrode and a second electrode. The passivation layer is disposed on the surfaces of the first doped layer, the spacer region and the second doped layer, and the first electrode and the second electrode are disposed on the surface of the passivation layer and are respectively electrically connected to the first doped layer and the second doped layer.

16. A method for preparing a back-contact battery, characterized in that, Comprising: Providing a silicon substrate, the back surface of the silicon substrate including a first region, a second region and a spacer region, the first region and the second region being alternately arranged, and a spacer region being provided between the first region and the second region; Successively forming a first tunneling layer and a first doped layer on the back surface of the silicon substrate, and simultaneously forming a first inner diffusion layer in the silicon substrate; Removing the first doped layer and the first tunneling layer on the spacer region and the second region, and removing the first inner diffusion layer in the silicon substrate corresponding to the second region or removing the first inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region; Forming a second tunneling layer and a second doped layer on the back surface of the silicon substrate, and simultaneously forming a second inner diffusion layer in the silicon substrate corresponding to the second region, or forming a second inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region, wherein the first inner diffusion layer and the second inner diffusion layer are electrically connected, the conduction types of the first doped layer and the second doped layer are opposite, the conduction types of the first inner diffusion layer and the first doped layer are the same, and the conduction types of the second inner diffusion layer and the second doped layer are the same; Removing the second doped layer and the second tunneling layer on the first region and the spacer region.

17. The preparation method according to claim 16, wherein After removing the first doped layer and the first tunneling layer on the spacer region and the second region, the method further includes: Forming a second tunneling layer and a second doped layer on the back surface of the silicon substrate, and simultaneously forming a second inner diffusion layer in the silicon substrate corresponding to the second region, or forming a second inner diffusion layer in the silicon substrate corresponding to the second region and the spacer region, and the second inner diffusion layer and the first inner diffusion layer overlap to form a common diffusion layer.

18. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, a back plate, and a back contact cell disposed between the cover plate and the back plate. The back contact cell is the back contact cell according to any one of claims 1-15, or the back contact cell is the back contact cell prepared by the preparation method according to claim 16 or claim 17.

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