High density static random access memory

Abstract

A semiconductor memory cell includes six vertical transport field effect transistors (VTFETs) on a wafer. The six VTFETs are in the first layer. The six VTFETs are in a first row.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to the field of semiconductor device manufacturing, and more particularly to high-density static random access memories using vertical transfer field effect transistors (VTFETs).

[0002] Semiconductor devices are fabricated by sequentially depositing insulating (dielectric), conductive, and semiconductor layers of materials on a semiconductor substrate and using lithography to pattern the layers to form circuit components and elements thereon. Typically, these semiconductor devices include multiple circuits that form an integrated circuit (IC) fabricated on the semiconductor substrate.

[0003] A static random access memory (SRAM) can be formed as a semiconductor device. SRAM is a random access memory that uses latch circuits (flip-flops) to store each bit. Conventional SRAM is formed by six transistors. Two sets of two transistors out of the six transistors form two cross-coupled inverters that store the bit in the cell. The storage cell has two stable states that are used to represent "0" or VSS and "1" or VDD. The fifth and sixth transistors are access transistors for read / write operations. Alternative SRAM configurations that use 4, 8, or 10 transistors have been implemented.

[0004] Current SRAM circuits can occupy a large amount of space on an integrated circuit. There is a need for a high-density SRAM cell that reduces size requirements and thus increases the density of SRAM circuits on an integrated circuit. The VTFET has a smaller width and height compared to conventional planar field effect transistors due to the vertical flow of current. SUMMARY OF THE INVENTION

[0005] In the first embodiment, a semiconductor memory cell including six vertical transfer field effect transistors (VTFETs) is on a wafer. In the first embodiment, the six VTFETs are in a first layer. In the first embodiment, the six VTFETs are in a first row. In the first embodiment, the power supplies of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the first embodiment, the grounds of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the first embodiment, the bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the back surface of the wafer, and the word lines of two of the six VTFETs are connected to a power supply network on the front surface of the wafer. In the first embodiment, the bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the front surface of the wafer, and the word lines of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the first embodiment, a first metal wire electrically connects the source / drain regions of the first VTFET, the source / drain regions of the second VTFET, the source / drain regions of the third VTFET, the gate region of the fourth VTFET, and the gate region of the fifth VTFET. In the first embodiment, a second metal wire electrically connects the gate region of the second VTFET, the gate region of the third VTFET, the source / drain regions of the fourth VTFET, the source / drain regions of the fifth VTFET, and the source / drain regions of the sixth VTFET. In the first embodiment, the first metal wire is within the semiconductor memory cell. In the first embodiment, the second metal wire is within the semiconductor memory cell. In the first embodiment, the fin ends and gate ends of one or more of the plurality of VTFETs are aligned with the RX edge.

[0006] In the second embodiment, multiple vertical transmission field effect transistors (VTFETs) are on a wafer. In the second embodiment, each of the multiple VTFETs is in a first layer. In the second embodiment, six of the multiple VTFETs form a memory cell. In the second embodiment, at least one memory cell is in a row adjacent to at least one other memory cell. In the second embodiment, the power supplies of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the second embodiment, the grounds of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the second embodiment, the bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the back surface of the wafer, and the word lines of two of the six VTFETs are connected to a power supply network on the front surface of the wafer. In the second embodiment, the bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the front surface of the wafer, and the word lines of two of the six VTFETs are connected to a power supply network on the back surface of the wafer. In the second embodiment, a first metal wire electrically connects the source / drain regions of a first VTFET, a second VTFET, and a third VTFET, the gate region of a fourth VTFET, and the gate region of a fifth VTFET. In the second embodiment, a second metal wire electrically connects the gate region of the second VTFET, the gate region of the third VTFET, the source / drain region of the fourth VTFET, the source / drain region of the fifth VTFET, and the source / drain region of the sixth VTFET. In the second embodiment, the first metal wire is within the semiconductor memory cell. In the second embodiment, the second metal wire is within the semiconductor memory cell.

[0007] In the third embodiment, a semiconductor SRAM includes six vertical transmission field effect transistors (VTFETs) on a wafer. In the third embodiment, the six VTFETs are in a first layer. In the third embodiment, the six VTFETs are in a first row.

[0008] In a fourth embodiment, a semiconductor memory array includes a plurality of vertical transfer field effect transistors (VTFETs) on a wafer. In the fourth embodiment, six of the plurality of VTFETs are disposed on a memory cell in one or more memory cells in a first layer on the wafer. In the fourth embodiment, each of the one or more memory cells is disposed in a single row. In the fourth embodiment, each of the one or more memory cells shares a first continuous bottom source / drain region for a first VTFET and a second VTFET in each memory cell. In the fourth embodiment, the first continuous bottom source / drain region is connected to a power supply network on the back side of the wafer. In the fourth embodiment, each of the one or more memory cells shares a second continuous bottom source / drain region for a third VTFET and a fourth VTFET in each memory cell. In the fourth embodiment, the second continuous bottom source / drain region is connected to a power supply network on the back side of the wafer. In the fourth embodiment, each of the one or more memory cells shares a third continuous bottom source / drain region for a fifth VTFET and a fourth continuous bottom source / drain region for a sixth VTFET in each memory cell. In the fourth embodiment, the third continuous bottom source / drain region is connected to a power supply network on the back side of the wafer. In the fourth embodiment, the fourth continuous bottom source / drain region is connected to a power supply network on the back side of the wafer.

[0009] In a fifth embodiment, a semiconductor memory array includes one or more vertical transistors on a wafer. In the fifth embodiment, the one or more vertical transistors are disposed in one or more memory cells in a first layer. In the fifth embodiment, each of the one or more memory cells is in a single row.

[0010] Embodiments of the present invention provide a high-density cell layout for SRAM technology using VTFETs. Embodiments of the present invention provide an SRAM including six VTFETs in a single row. Embodiments of the present invention provide bit line connections on a first side of the SRAM and word line connections on a second side of the SRAM. Embodiments of the present invention provide a single line connecting a pull-down, a transmission gate, a pull-up, and cross-coupling. Embodiments of the present invention provide fin tip and gate tip alignment. Embodiments of the present invention provide distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to source / drain / gate regions of VTFETs through a back-side power supply network. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

[0012] Figure 1A cross-sectional view of a VTFET semiconductor structure with front contacts for a top source / drain region, a bottom source / drain region, and a gate region according to a first embodiment of the present invention is shown.

[0013] Figure 2 A cross-sectional view of a VTFET semiconductor structure with front contacts for a top source / drain region and a gate region and a back contact for a bottom source / drain region according to a first embodiment of the present invention is shown.

[0014] Figure 3 A cross-sectional view of a VTFET semiconductor structure with front contacts for a top source / drain and back contacts for a bottom source / drain region and a gate region according to a first embodiment of the present invention is shown.

[0015] Figure 4 A circuit schematic diagram of an SRAM according to an embodiment of the present invention is shown.

[0016] Figure 5 A top view of two adjacent SRAMs according to an embodiment of the present invention is shown.

[0017] Figure 6 A top view of an SRAM cell according to a first embodiment of the present invention is shown.

[0018] Figure 7 A cross-sectional view of cross-section X of an SRAM cell according to an embodiment of the present invention is shown.

[0019] Figure 8 A cross-sectional view of cross-section Y of an SRAM cell according to an embodiment of the present invention is shown. Detailed Description

[0020] Embodiments of the present invention recognize that a vertical transmission field effect transistor (VTFET) has a vertical current. Embodiments of the present invention recognize that a VTFET includes a bottom source / drain region and a top source / drain region. Embodiments of the present invention recognize that the bottom source / drain region is closer to the back of the VTFET (closer to the wafer), and the top source / drain region is closer to the front of the VTFET (closer to the conventional interconnect wiring). Embodiments of the present invention recognize that the input will be to one source / drain region and the output will be to one source / drain region, so one of the input or output will be on the back of the device and one of the input or output will be on the front of the device. Thus, embodiments of the present invention recognize that VTFET transistors are suitable for use in SRAM technology.

[0021] Embodiments of the present invention provide a high-density cell layout for SRAM technology using VTFETs. Embodiments of the present invention provide an SRAM including six VTFETs in a single row. Embodiments of the present invention provide bit line connections on a first side of the SRAM and word line connections on a second side of the SRAM. Embodiments of the present invention provide a single line connecting the pull-down, transmission gate, pull-up, and cross-coupling. Embodiments of the present invention provide fin tip and gate end alignment. Embodiments of the present invention provide distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate regions of the VTFETs through a backside power supply network.

[0022] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure have been shown. However, the present disclosure may be implemented in various ways and should not, therefore, be construed as limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals always refer to like elements.

[0023] The following presents an overview to provide a basic understanding of one or more embodiments of the present disclosure. This overview is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. It should be understood that aspects of the present invention will be described in accordance with a given illustrative architecture; however, other architectures, structures, substrate materials, process features, and steps may be varied within the scope of aspects of the present invention.

[0024] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. Embodiments of the present invention may be practiced in conjunction with integrated circuit manufacturing techniques currently used in the art for advanced semiconductor devices and include only as many of the common practice process steps as are necessary to understand the described embodiments. The drawings represent a cross-sectional portion of a part of an advanced semiconductor device after fabrication and are not drawn to scale but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting but only as a representative basis for teaching one skilled in the art to employ the methods and structures of the present disclosure in various ways. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0025] It should also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0026] For the purposes of the description hereinafter, the terms "up", "down", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods as oriented in the accompanying drawings. The terms "overlying", "on top", "above", "on", "lying on", or "lying on top" mean that a first element is present on a second element, where intervening elements, such as an interface structure, can be present between the first and second elements. The term "direct contact" means that a first element and a second element are joined without any intervening conductive, insulating, or semiconductor layers at the interface of the two elements.

[0027] To avoid obscuring the presentation of the embodiments of the present invention, in the following detailed description, some processing steps, materials, or operations known in the art may be combined for purposes of presentation and illustration and may not be described in detail in some cases. Additionally, for the sake of brevity and to maintain focus on the distinguishing features of the elements of the present invention, the descriptions of the previously discussed materials, processes, and structures may not be repeated for subsequent figures. In other cases, some processing steps or operations that are known may not be described. It should be understood that the following description is more focused on the distinguishing features or elements of the various embodiments of the present invention.

[0028] This embodiment may include the design of an integrated circuit chip, which can be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard disk drive, or virtual hard disk drive in a storage access network). If the designer does not fabricate the chip or the lithography mask for fabricating the chip, the designer can transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for fabricating the lithography mask, which typically includes multiple copies of the chip design under discussion to be formed on a wafer. The lithography mask is used to define the areas of the wafer (and / or the layers thereon) to be etched or otherwise processed.

[0029] The methods described herein can be used in the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in the form of a raw wafer (i.e., as a single wafer having a plurality of unpackaged chips), as bare chips, or in a packaged form. In the latter case, the chips are mounted in a single chip package (e.g., a plastic carrier having leads that are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both surface interconnects or buried interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processing unit.

[0030] It should also be understood that material compounds will be described in terms of listed elements, such as SiGe. These compounds include elements in different proportions within the compound, e.g., SiGe includes SixGe1-x, where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the principles herein. Compounds having additional elements will be referred to herein as alloys.

[0031] References in the specification to "one embodiment" or "an embodiment" and other variations thereof mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations thereof appearing throughout the specification are not necessarily all referring to the same embodiment.

[0032] References in the specification to "one embodiment", "other embodiments", "another embodiment", "an embodiment", etc. indicate that the described embodiments can include particular features, structures, or characteristics, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Moreover, these phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that implementing this feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly described.

[0033] It should be understood that, for example, in the cases of "A / B", "A and / or B", and "at least one of A and B", the use of any one of the following, namely, " / ", "and / or", and "at least one of", is intended to cover the selection of only the first-listed option (A), or only the second-listed option (B), or the selection of both options (A and B). As a further example, in the cases of "A, B, and / or C" and "at least one of A, B, and C", such wording is intended to cover the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or the selection of only the first and second-listed options (A and B), or the selection of only the first and third-listed options (A and C), or the selection of only the second and third-listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of items listed, which is apparent to those of ordinary skill in the art and related fields.

[0034] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] For ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "beneath" can include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein may be interpreted accordingly. Additionally, it should be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intermediate layers.

[0036] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the scope of this concept, the first element discussed below could be termed the second element.

[0037] Generally, the various processes used to form semiconductor chips are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process by which materials are grown, coated, or otherwise transferred onto a wafer. Available techniques include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently atomic layer deposition ("ALD"), among others. Another deposition technique is plasma-enhanced chemical vapor deposition ("PECVD"), which is a process that uses the energy in a plasma to initiate reactions on the wafer surface that would otherwise require higher temperatures associated with conventional CVD. The high-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0038] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can subsequently be transferred onto the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. Patterns generated by lithography or photolithography are typically used to define or protect selected surfaces and portions of semiconductor structures during subsequent etching processes.

[0039] Removal is any process by which materials are removed from the wafer, such as etching or chemical mechanical planarization ("CMP"). Examples of etching processes include wet (e.g., chemical) or dry etching processes. An example of a removal process or a dry etching process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that uses a remote broad-beam ion / plasma source to remove substrate material by means of physical inert gas and / or chemical reaction gas. Similar to other dry plasma etching techniques, IBE has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etching process is reactive ion etching ("RIE"). Generally, RIE uses a chemical reaction plasma to remove materials deposited on the wafer. The high-energy ions from the RIE plasma attack the wafer surface and react with the surface material to remove the surface material.

[0040] The deposition processes for the metal gasket and sacrificial material include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which the deposited material is formed due to a chemical reaction between gaseous reactants at a temperature above room temperature (e.g., from about 25 °C to about 900 °C). The solid product of the reaction is deposited on a surface on which a film, coating, or layer of the solid product will be formed. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be employed. In an alternative embodiment using PVD, the sputtering device may include a direct current diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In an alternative embodiment using ALD, the chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In an alternative embodiment using GCIB deposition, a high-pressure gas is allowed to expand in a vacuum and then condenses into clusters. The clusters can be ionized and directed onto the surface, thereby providing highly anisotropic deposition.

[0041] Vertical transport field effect transistors (VTFETs) have emerged as a viable device option for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to the 5 nanometer (nm) node and below. The VTFET device includes one or more fin channels on the top and bottom sides of the fin, with source / drain regions at the ends of the fin channels. Current flows through the fin channels in a vertical direction (e.g., perpendicular to the substrate), e.g., from the bottom source / drain region to the top source / drain region. The vertical transport structure device is designed to address the limitations of horizontal device structures in terms of, for example, density, performance, power consumption, and integration by, for example, decoupling the gate length from the contact gate pitch, providing FiN-FET equivalent density at a larger contact poly pitch (CPP), and providing lower mid-section of line (MOL) resistance.

[0042] In a first embodiment, Figure 1 VTFET 100 is shown, where contacts 114, 124, and 134 are directly connected to the interconnect wiring and / or power supply network (not shown) on the front side of VTFET 100. In a second embodiment, Figure 2 VTFET 200 is shown, where contacts 214 and 234 are directly connected to the interconnect wiring and / or power supply network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to the interconnect wiring and / or power supply network (not shown) on the back side of VTFET 200. In a third embodiment, Figure 3Shows a VTFET 300, where contact 314 is directly connected to the interconnect wiring and / or power supply network (not shown) on the front side of the VTFET 300, and contact 324 and contact 334 are directly connected to the interconnect wiring and / or power supply network (not shown) on the back side of the VTFET 300.

[0043] Figure 1 Is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 can be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and their multilayers. Although silicon is the main semiconductor material used in wafer manufacturing, alternative semiconductor materials can be used as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. In an illustrative embodiment, the substrate 102 is silicon.

[0044] The VTFET 100 includes a STI region 104 composed of a dielectric material such as silicon oxide or silicon oxynitride, which is formed by methods well known in the art. For example, in an illustrative embodiment, the STI region 104 is a shallow trench isolation oxide layer.

[0045] The VTFET 100 includes a top source / drain region 110 and a bottom source / drain region 120 at either end of the fin 130. In an embodiment, the top source / drain region 110 is formed between dielectric layers 170. In an embodiment, the bottom source / drain region 120 is formed in the substrate 102 between the shallow trench isolation regions 104. The top source / drain region 110 and the bottom source / drain region 120 are formed by, for example, an epitaxial growth process. The epitaxially grown top source / drain region 110 and bottom source / drain region 120 can be in-situ doped, which means that dopants are incorporated into the epitaxial film during the epitaxial process. Other alternative doping techniques can be used, including but not limited to, for example, ion implantation, vapor doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, etc., and the dopants can include, for example, n-type dopants selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb) at various concentrations, and p-type dopants selected from the group consisting of boron (B), gallium (Ga), indium (In), and thallium (Tl) at various concentrations. For example, in a non-limiting example, the dopant concentration range can be 1×10 18 / cm 3 to 1×10 21 / cm 3According to an embodiment, the bottom source / drain region 120 can be boron-doped SiGe for a p-type field effect transistor (P-FET), or phosphorus-doped silicon for an n-type field effect transistor (N-FET). It should be understood that the term "source / drain region" as used herein means that a given source / drain region can be a source region or a drain region, depending on the application.

[0046] Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which the epitaxial semiconductor material is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on a semiconductor surface and does not deposit material on a dielectric surface, such as a silicon dioxide or silicon nitride surface.

[0047] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of the epitaxial deposition process can be in the range of 500°C to 900°C. Although higher temperatures generally result in faster deposition, faster deposition may lead to crystal defects and film cracking.

[0048] Many different sources can be used for the epitaxial growth of a compressive strain layer. In some embodiments, the gas sources for depositing the epitaxial semiconductor material include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source that includes, but is not limited to, silane, disilane, trisilane, tetrasilane, hexachloroethylsilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that includes, but is not limited to, germane, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. A combination of these gas sources can be utilized to form an epitaxial silicon-germanium alloy layer. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. After the epitaxial growth is formed, a drive-in anneal can be applied to move the dopants closer to the bottom of the fin channel.

[0049] In an embodiment, as used herein, a "semiconductor fin" or fin 130 refers to a semiconductor material including a pair of vertical sidewalls parallel to each other. As used herein, a surface is "vertical" if there is a vertical plane in which the surface deviation does not exceed three times the root mean square roughness of the surface. In an embodiment, each fin 130 has a height ranging from about 20 nm to about 200 nm and a width ranging from about 5 nm to about 30 nm. Other heights and / or widths less than or greater than the ranges mentioned herein may also be used in this application. Each fin 130 is spaced from its nearest adjacent fin 130 by a pitch of about 20 nm to about 100 nm; the pitch is measured from a point or reference surface on one semiconductor fin to the exact same point or reference surface on an adjacent semiconductor fin. Moreover, the fins 130 are generally oriented parallel to each other. Although this application describes and illustrates a single fin 108, any number of fins may be used, where the gate region surrounds the fins, and the fins may be of any shape.

[0050] The fin 130 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multi-layers thereof. Although silicon is the semiconductor material mainly used in wafer manufacturing, alternative semiconductor materials may be employed as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. In one exemplary embodiment, the fin 130 is silicon.

[0051] In an embodiment, a bottom spacer layer 140 is formed on the STI region 104 and the bottom source / drain region 120. In an embodiment, the bottom spacer layer 140 is formed around the fin 130. Suitable materials for the bottom spacer layer 140 include, for example, silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), silicon carbon nitrogen oxide (SiOCN), SiN, and SiO x . The bottom spacer layer 140 may be deposited using, for example, directed deposition techniques such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directed deposition preferably deposits spacer material on exposed horizontal surfaces rather than on lateral sidewalls. Alternatively, the bottom spacer layer 140 may be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0052] In an embodiment, a top spacer layer 160 is formed on the gate region between the fin 130 and the dielectric layer 170. In an embodiment, the top spacer layer 160 is formed around the fin 130. Suitable materials for the top spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), silicon carbon nitrogen oxide (SiOCN), SiN, and SiOx The bottom spacer layer 140 can be deposited using, for example, directed deposition techniques such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directed deposition preferably deposits spacer material on exposed horizontal surfaces rather than on lateral sidewalls. Alternatively, the top spacer layer 160 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0053] A gate region is formed on the bottom spacer layer 140 and around the fin 130. In an illustrative embodiment, the gate region is deposited on the bottom spacer layer 140 and around the fin 130 using, for example, ALD, CVD, RFCVD, plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region can include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 can be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanate, barium titanate, strontium titanate, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 can include a metal gate or a work function metal (WFM). The WFM for the gate conductor layer can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack including a barrier layer (e.g., a barrier layer of TiN, TaN, etc.) and one or more of the above WFM materials subsequently, etc.

[0054] In an embodiment, the dielectric layer 170 can be composed of, for example, silicon oxide (SiO x )), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As described above, the term "low-k" as used herein refers to a material having a relative dielectric constant k lower than that of silicon dioxide. In an embodiment, the dielectric layer 170 can be formed using deposition techniques including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin coating, or sputtering.

[0055] In an embodiment, the top source / drain region 110, the bottom source / drain region 120, and the gate region are connected to an interconnect wiring and / or a power supply network (not shown) through contacts 114, 124, and 134, respectively. In an embodiment, as Figure 1 shown, the contacts 114, 124, and 134 are formed to directly connect to an interconnect wiring and / or a power supply network (not shown) on the front side of the VTFET 100. In an embodiment, the contacts 114, 124, and 134 may include any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or an alloy thereof. Examples of deposition techniques that can be used include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques can be used to form the contacts 114, 124, and 134.

[0056] In a second embodiment, Figure 2 a VTFET 200 is shown, where the contacts 214 and 234 are directly connected to an interconnect wiring and / or a power supply network (not shown) on the front side of the VTFET 200, and the contact 224 is directly connected to an interconnect wiring and / or a power supply network (not shown) on the back side of the VTFET 200. In the second embodiment, the VTFET 200 has features that are substantially similar to the features described above with reference to the VTFET 100. For example, the top source / drain region 210 is substantially similar to the top source / drain region 110. It should be noted that although Figure 2 a substrate similar to the Figure 1 substrate 102 shown is not shown, those skilled in the art should know that the VTFET 200 will be formed on a substrate similar to the Figure 1 substrate 102 shown.

[0057] In the second embodiment, the main difference in the VTFET 200 compared to the VTFET 100 is the orientation of the contacts. In the second embodiment, the contacts 214 and 234 are directly connected to an interconnect wiring and / or a power supply network (not shown) on the front side of the VTFET 200, and the contact 224 is directly connected to an interconnect wiring and / or a power supply network (not shown) on the back side of the VTFET 200.

[0058] In a third embodiment, Figure 3Shows a VTFET 300, where the contact 314 is directly connected to the interconnect wiring and / or power supply network (not shown) on the front side of the VTFET 300, and the contacts 324 and 334 are directly connected to the interconnect wiring and / or power supply network (not shown) on the back side of the VTFET 300. In the third embodiment, the VTFET 300 has features that are substantially similar to those described above with reference to the VTFET 100 and the VTFET 200. For example, the top source / drain region 310 is substantially similar to the top source / drain region 110 and the top source / drain region 210. It should be noted that although a substrate similar to the substrate 102 shown in Figure 3 is not shown in Figure 1 , those skilled in the art should know that the VTFET 300 will be formed on a substrate similar to the substrate 102 shown in Figure 1 .

[0059] In the third embodiment, compared with the VTFET100 and the VTFET200, the orientation of the contacts in the VTFET 300 is the main difference. In the third embodiment, the contact 314 is directly connected to the interconnect wiring and / or power supply network (not shown) on the front side of the VTFET 300, and the contacts 324 and 334 are directly connected to the interconnect wiring and / or power supply network (not shown) on the back side of the VTFET 300.

[0060] Figure 4 Shows a circuit schematic of an SRAM 400 according to an embodiment of the present invention. In the embodiment, the SRAM 400 is composed of six transistors, a first transistor 410, a second transistor 412, a third transistor 420, a fourth transistor 422, a fifth transistor 430, and a sixth transistor 432. As is known in the art, this is also called a 6T SRAM cell. As described herein, each of the six transistors is a VTFET structure. However, embodiments of the present invention recognize that some or all of these six transistors can be other types of transistors.

[0061] In an embodiment, each bit in the SRAM 400 cell is stored on a third transistor 420, a fourth transistor 422, a fifth transistor 430, and a sixth transistor 432. In an embodiment, the third transistor 420 and the fourth transistor 422 form a first inverter. In an embodiment, the fifth transistor 430 and the sixth transistor 432 form a second inverter. In an embodiment, the first inverter and the second inverter are cross-coupled. In other words, the output 440 of the first inverter is connected to the gate 446 of the second inverter, and the output 442 of the second inverter is connected to the gate 444 of the second inverter. In an embodiment, the output 440 of the first inverter is also connected to the source / drain region of the first transistor 410. In an embodiment, the output 442 of the second inverter is connected to the source / drain region of the second transistor 412. In an embodiment, the source / drain regions of both the third transistor 420 and the fifth transistor 430 are connected to a power supply or VDD power supplies 426 and 436, respectively. In an embodiment, the source / drain regions of the fourth transistor 422 and the sixth transistor 432 are connected to a ground or GND power supplies 428 and 438, respectively. In an embodiment, the gate regions of the first transistor 410 and the second transistor 412 are connected to a word line 450. In an embodiment, the word line 450 controls read and write operations in the SRAM 400 cell. In an embodiment, the source / drain region of the first transistor 410 is connected to a bit line 460, and the source / drain region of the second transistor 412 is connected to a bitline_bar 462. In an embodiment, the bit line 460 and the bitline_bar 462 are used to transfer data for both read and write operations. It should be noted that the SRAM may include only the bit line 460 or the bitline_bar 462, but typically two signals are provided to improve the noise margin when reading and writing SRAM cells. As Figure 4 shown, the first transistor 410, the second transistor 412, the fourth transistor 422, and the sixth transistor 432 are "n-type" transistors, while the third transistor 420 and the fifth transistor 430 are "p-type", but other doping configurations can be implemented.

[0062] Figure 5 A top view of two adjacent SRAMs 500 according to an embodiment of the present invention is shown. As Figure 5 shown, the first SRAM 502 cell is adjacent to the second SRAM 504 cell. For simplicity, only two cells are shown. However, those skilled in the art will recognize that any number of SRAM cells can be found adjacent to each other. It should be noted that in Figure 5The internal transistors of each SRAM cell are not shown, but as described above and below, each SRAM cell includes multiple transistors. In an embodiment, the first SRAM 502 cell is connected to a word line (not shown) through a word line contact 530. In an embodiment, the second SRAM 504 cell is connected to a word line (not shown) through a word line contact 532. In an embodiment, the SRAM 500 includes bit lines 510, bit line strips 512, grounds 520, 522 or GND, and a power supply 525 or VDD. In an embodiment, the bit lines 510, bit line strips 512, grounds 520, ground 522, and power supply 525 are found on the back surface of the SRAM cell. In other words, the SRAM cell is on top of a wafer (not shown), and the bit lines 510, bit line strips 512, grounds 520, ground 522, and power supply 525 are between the SRAM cell and the wafer. In an embodiment, the word line (not shown) is on the front surface of the SRAM cell or on top of the SRAM cell. It should be noted, and is discussed below, that in an alternative configuration, the word line and the bit line / bit line strip can be swapped. It should be noted, and is discussed below, that in an alternative configuration, VDD and GND can be swapped.

[0063] Figure 6 A top view of an SRAM 600 cell according to a first embodiment of the present invention is shown. In an embodiment, the SRAM 600 cell includes a first transistor 630, a second transistor 640, a third transistor 650, a fourth transistor 670, a fifth transistor 660, and a sixth transistor 680. It should be noted that, as described by the functions in Figure 4 the first transistor 630 is similar to the first transistor 410, the second transistor 640 is similar to the second transistor 412, the third transistor 650 is similar to the third transistor 420, the fourth transistor 670 is similar to the fourth transistor 422, the fifth transistor 660 is similar to the fifth transistor 430, and the sixth transistor 680 is similar to the sixth transistor 432.

[0064] As Figure 6 shown, the SRAM 600 cell includes a backside power supply network, which includes a power supply (i.e., VDD) 625, grounds (i.e., GND) 620, 622, bit lines 610, and bit line strips 612. As described above, the backside power supply network is located on the back surface, or between the device layer (i.e., the transistor) and the wafer on which the device layer is formed. As Figure 6As shown, the SRAM 600 cell includes word lines 628, 629 at either end of the SRAM 600 cell, which are respectively connected to the gate regions 632, 642 of the first transistor 630 and the second transistor 640. In an embodiment, the word lines 628, 629 are formed on the front side of the device layer or on the top of the device layer, and on the opposite side of the wafer on which the device layer is formed. In an embodiment, the word lines 628, 629 are within the conventional back end of the wire interconnect routing. As Figure 6 shown, the word lines 628, 629 are on the first metal layer directly above the transistors of the SRAM 600 cell. In an alternative embodiment, the word lines 628, 629 are on any metal layer above the transistors of the SRAM 600 cell, as long as the contacts from the word lines 628, 629 respectively extend to the gate regions 632, 642 of the first transistor 630 and the second transistor 640.

[0065] In an alternative embodiment, as described above, the power supply 625 can actually provide ground, and the grounds 620, 622 can provide the power supply. In other words, the power supply and the ground are exchanged or flipped. In this alternative embodiment, those skilled in the art will recognize that the layout of the third transistor 650, the fourth transistor 670, the fifth transistor 660, and the sixth transistor 680 can be different. In an alternative embodiment, as described above, the word lines 628, 629 can provide the bit line 610 and bit line strip 612 functions, and the bit lines 610, bit line strips 612 can provide the word line function. In other words, in this alternative embodiment, the routing of the word lines is exchanged or flipped with the routing of the bit lines and bit line strips. In this alternative embodiment, those skilled in the art will recognize that the layout of the first transistor 630, the second transistor 640, the third transistor 650, the fourth transistor 670, the fifth transistor 660, and the sixth transistor 680 can be different.

[0066] In an embodiment, as Figure 6 shown, the first transistor 630 includes a bottom source / drain region (not shown), a fin 634, a gate region 632, and a top source / drain region 636. In an embodiment, the bottom source / drain region (not shown) is connected to the bit line 610 through a back contact (not shown). In an embodiment, the gate region 632 is connected to the word line 628 through a front contact (not shown). In an embodiment, the top source / drain region 636 is connected to the cross-coupling 690 through a front contact 638. In an embodiment, the bottom source / drain region (not shown) can be used for the first transistor 630. In an alternative embodiment, the bottom source / drain region (not shown) can be a shared bottom source / drain region, which is also the shared bottom source / drain region of any number of first transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6As shown, the ends of fin 634 and the ends of gate region 632 both extend and align on the RX edge of first transistor 630 that is closest to third transistor 650. In an alternative embodiment, the ends of fin 634 and the ends of gate region 632 may not be aligned with each other and / or may not be aligned on the RX edge of first transistor 630. For example, the edges of fin 634 and gate region 632 may align on the left edge of first transistor 630 that is farthest from third transistor 650. In an embodiment, fin 634 has a first length and a second length, the first length being in the same direction as the longer length of SRAM 600 cell, and the second length being shorter than the first length.

[0067] In an embodiment, as Figure 6 As shown, second transistor 640 includes a bottom source / drain region (not shown), fin 644, gate region 642, and top source / drain region 646. In an embodiment, the bottom source / drain region (not shown) is connected to bit line 612 through a back contact (not shown). In an embodiment, gate region 642 is connected to word line 629 through a front contact (not shown). In an embodiment, top source / drain region 646 is connected to cross-coupling 694 through front contact 648. In an embodiment, the bottom source / drain region (not shown) may be used for first transistor 640. In an alternative embodiment, the bottom source / drain region (not shown) may be a shared bottom source / drain region that is also the shared bottom source / drain region of any number of second transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6 As shown, the ends of fin 644 and the ends of gate region 642 both extend and align on the RX edge of second transistor 640 that is closest to fifth transistor 660. In an alternative embodiment, the ends of fin 644 and the ends of gate region 642 may not be aligned with each other and / or may not be aligned on the RX edge of second transistor 640. For example, the edges of fin 644 and gate region 642 may align on the right edge of second transistor 640 that is farthest from fifth transistor 660. In an embodiment, fin 644 has a first length and a second length, the first length being in the same direction as the longer length of SRAM 600 cell, and the second length being shorter than the first length.

[0068] In an embodiment, as Figure 6As shown, the third transistor 650 includes a bottom source / drain region (not shown), a fin 654, a shared gate region 652 / 672, and a top source / drain region 656. In an embodiment, the bottom source / drain region (not shown) is connected to ground 620 through a back contact (not shown). In an embodiment, the shared gate region 652 / 672 is connected to cross-coupling 694 through a front contact 696 and a fourth transistor 670, as described below. In an embodiment, the shared gate region 652 / 672 is a gate region for both the third transistor 650 and the fourth transistor 670. In an embodiment, the top source / drain region 656 is connected to cross-coupling 690 through a front contact 658. In an embodiment, the bottom source / drain region (not shown) can be used for the third transistor 650. In an alternative embodiment, the bottom source / drain region (not shown) can be a shared bottom source / drain region, which is also a shared bottom source / drain region for any number of third transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6 shown, both the end of the fin 654 and the end of the gate region 652 / 672 extend and align on the RX edge of the third transistor 650 closest to the first transistor 630. In an alternative embodiment, the end of the fin 654 and the end of the gate region 652 / 672 may not be aligned with each other and / or may not be aligned on the RX edge of the third transistor 650. For example, the edge of the fin 654 may be aligned with the right edge of the second transistor 640 that is farthest from the first transistor 630. In an embodiment, the fin 645 has a first length and a second length, the first length being in the same direction as the longer length of the SRAM 600 cell, and the second length being shorter than the first length.

[0069] In an embodiment, as Figure 6 shown, the fifth transistor 660 includes a bottom source / drain region (not shown), a fin 664, a shared gate region 662 / 682, and a top source / drain region 666. In an embodiment, the bottom source / drain region (not shown) is connected to ground 622 through a back contact (not shown). In an embodiment, the shared gate region 662 / 682 is connected to cross-coupling 690 through a front contact 692 and a sixth transistor 680, as described below. In an embodiment, the shared gate region 652 / 672 is a gate region for both the third transistor 650 and the fourth transistor 670. In an embodiment, the top source / drain region 666 is connected to cross-coupling 694 through a front contact 668. In an embodiment, the bottom source / drain region (not shown) can be used for the fifth transistor 660. In an alternative embodiment, the bottom source / drain region (not shown) can be a shared bottom source / drain region, which is also a shared bottom source / drain region for any number of fifth transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6As shown, the ends of fin 664 and the ends of gate regions 662 / 682 both extend and align on the RX edge of the fifth transistor 660 that is closest to the second transistor 640. In an alternative embodiment, the ends of fin 664 and the ends of gate regions 662 / 682 may not be aligned with each other and / or may not be aligned on the RX edge of the fifth transistor 660. For example, the edge of fin 664 may align with the left edge of the fifth transistor 660 that is farthest from the second transistor 640. In an embodiment, fin 664 has a first length and a second length, the first length being in the same direction as the longer length of the SRAM 600 cell, and the second length being shorter than the first length.

[0070] In an embodiment, as Figure 6 shown, the fourth transistor 670 includes a bottom source / drain region (not shown), a fin 674, a shared gate region 652 / 672, and a top source / drain region 676. In an embodiment, the bottom source / drain region (not shown) is connected to power supply 625 through a back contact (not shown). In an embodiment, as described above, the shared gate region 652 / 672 is connected to cross-coupling 694 through a front contact 696 and the third transistor 650. In an embodiment, as described above, the shared gate region 652 / 672 is the gate region of both the third transistor 650 and the fourth transistor 670. In an embodiment, the top source / drain region 676 is connected to cross-coupling 690 through a front contact 678. In an embodiment, the bottom source / drain region (not shown) may be used for the fourth transistor 670. In an alternative embodiment, the bottom source / drain region (not shown) may be a shared bottom source / drain region that is also the shared bottom source / drain region of any number of fourth transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6 shown, the ends of fin 674 and the ends of gate region 652 / 672 both extend and align on the RX edge of the fourth transistor 670 that is closest to the sixth transistor 680. In an alternative embodiment, the ends of fin 674 and the ends of gate region 652 / 672 may not be aligned with each other and / or may not be aligned on the RX edge of the fourth transistor 670. For example, the edge of fin 674 and the gate region 652 / 672 may align on the left edge of the fourth transistor 670 that is closest to the third transistor 650. In an embodiment, fin 674 has a first length and a second length, the first length being in the same direction as the longer length of the SRAM 600 cell, and the second length being shorter than the first length.

[0071] In an embodiment, as Figure 6As shown, the sixth transistor 680 includes a bottom source / drain region (not shown), a fin 684, a shared gate region 662 / 682, and a top source / drain region 686. In an embodiment, the bottom source / drain region (not shown) is connected to a power supply 625 through a back contact (not shown). In an embodiment, as described above, the shared gate region 662 / 682 is connected to a cross-coupling 690 through a front contact 692 and a fifth transistor 660. In an embodiment, as described above, the shared gate region 662 / 682 is a gate region for both the fifth transistor 660 and the sixth transistor 680. In an embodiment, the top source / drain region 686 is connected to a cross-coupling 694 through a front contact 688. In an embodiment, the bottom source / drain region (not shown) can be used for the sixth transistor 680. In an alternative embodiment, the bottom source / drain region (not shown) can be a shared bottom source / drain region, which is also a shared bottom source / drain region for any number of sixth transistors in adjacent SRAM cells (not shown). In an embodiment, as Figure 6 shown, both the end of the fin 684 and the end of the gate region 662 / 682 extend and align on the RX edge of the sixth transistor 680 that is closest to the fourth transistor 670. In an alternative embodiment, the end of the fin 684 and the end of the gate region 662 / 682 may not be aligned with each other and / or may not be aligned on the RX edge of the sixth transistor 680. For example, the edge of the fin 684 and the gate region 662 / 682 may be aligned on the right edge of the sixth transistor 680 that is closest to the fifth transistor 660. In an embodiment, the fin 684 has a first length and a second length, the first length is in the same direction as the longer length of the SRAM 600 cell, and the second length is shorter than the first length.

[0072] In an embodiment, as described above, the SRAM 600 cell includes a cross-coupling 690 and a cross-coupling 694. In an embodiment, the cross-coupling 690 and the cross-coupling 694 are on any metal layer above the transistors of the SRAM 600 cell. In an embodiment, the cross-coupling 690 and the cross-coupling 694 can be metal wire tracks. In an embodiment, the cross-coupling 690 is connected to the first transistor 630 through a front contact 638, to the third transistor 650 through a front contact 658, to the fourth transistor 670 through a front contact 678, and to the shared gate region 662 / 682 through a front contact 692. In an embodiment, the cross-coupling 694 is connected to the second transistor 640 through a front contact 648, to the fifth transistor 660 through a front contact 668, to the sixth transistor 680 through a front contact 688, and to the shared gate region 652 / 672 through a front contact 696.

[0073] Figure 7FIG. shows a cross-sectional view of cross-section X of an SRAM 700 cell according to an embodiment of the present invention. In an embodiment, as Figure 7 shown, the SRAM 700 cell includes a backside power supply network, which includes a power supply (i.e., VDD) 725, a ground (i.e., GND) 720, 722, bit lines 710, and bit line strips 712. As described above, the backside power supply network is located on the backside, or between the device layer (i.e., transistors) and the wafer on which the device layer is formed. In an embodiment, the power supply 725 can be connected to the backside power supply network through a backside power supply contact 725A. In an embodiment, the grounds 720, 722 can be respectively connected to the backside power supply network through backside power supply contacts 720A, 722A. In an embodiment, the bit lines 710 can be connected to the backside power supply network through a backside power supply contact 710A. In an embodiment, the bit line strips 712 can be connected to the backside power supply network through a backside power supply contact 712A.

[0074] In an embodiment, the bit line 710 is connected to a bottom source / drain region 711. In an embodiment, the bit line strip 712 is connected to a bottom source / drain region 713. In an embodiment, the ground 720 is connected to a bottom source / drain region 721. In an embodiment, the ground 722 is connected to a bottom source / drain region 723. In an embodiment, the power supply 725 is connected to a shared bottom source / drain region 726. In an alternative embodiment, the shared bottom source / drain region 726 can be two separate and distinct bottom source / drain regions for each VTFET.

[0075] As Figure 7 shown, the SRAM 700 cell includes word lines 728, 729 at either end of the SRAM 700 cell, and are respectively connected to gate regions 732, 742 of a first transistor 630 and a second transistor 640. In an embodiment, the word lines 728, 729 are formed on the front or top of the device layer, and on the opposite side of the wafer on which the device layer is formed. In an embodiment, the word lines 728, 729 are within a conventional back end of line interconnect wiring. As Figure 7 shown, the word lines 728, 729 are on a first metal layer directly above the transistors of the SRAM 600 cell. In an alternative embodiment, the word lines 728, 729 are on any metal layer above the transistors of the SRAM 600 cell, as long as the contacts from the word lines 728, 729 respectively extend to the gate regions 732, 742 of the first transistor 630 and the second transistor 640. In an embodiment, the word lines 728, 729 are respectively connected to the gate regions 732, 742 through front side contacts.

[0076] In an embodiment, the gate region 732 surrounds at least a portion of the fin 734, and the fin 734 is connected to the top source / drain region 736. In an embodiment, the top source / drain region 736 is connected to the front contact 738, and the front contact 738 is connected to the cross-coupling 690 (not shown). In an embodiment, the gate region 742 surrounds at least a portion of the fin 744, and the fin 744 is connected to the top source / drain region 746. In an embodiment, as described above, the top source / drain region 746 is connected to the front contact 748, and the front contact 748 is connected to the cross-coupling 694 (not shown).

[0077] In an embodiment, the shared gate region 752 / 772 surrounds at least a portion of the fins 754 and 774. In an embodiment, the fin 754 is connected to the top source / drain region 756. In an embodiment, as described above, the top source / drain region 756 is connected to the front contact 758, and the front contact 758 is connected to the cross-coupling 690 (not shown). In an embodiment, the fin 774 is connected to the top source / drain region 776. In an embodiment, as described above, the top source / drain region 776 is connected to the front contact 778, and the front contact 778 is connected to the cross-coupling 690 (not shown). In an embodiment, as described above, the shared gate region 752 / 772 is connected to the front contact 796, and the front contact 796 is connected to the cross-coupling 694 (not shown).

[0078] In an embodiment, the shared gate region 762 / 782 surrounds at least a portion of the fins 764 and 784. In an embodiment, the fin 764 is connected to the top source / drain region 766. In an embodiment, as described above, the top source / drain region 766 is connected to the front contact 768, and the front contact 768 is connected to the cross-coupling 694 (not shown). In an embodiment, the fin 784 is connected to the top source / drain region 786. In an embodiment, as described above, the top source / drain region 786 is connected to the front contact 788, and the front contact 788 is connected to the cross-coupling 694 (not shown). In an embodiment, as described above, the shared gate region 762 / 782 is connected to the front contact 792, and the front contact 792 is connected to the cross-coupling 690 (not shown).

[0079] Figure 8 A cross-sectional view of cross-section Y of the SRAM 800 cell according to an embodiment of the present invention is shown. In an embodiment, as Figure 8As shown, the SRAM 800 cell includes a backside power supply network, which includes a power supply (i.e., VDD) 825, a ground (i.e., GND) 820, 822, bit lines 810, and bit line strips 812. As described above, the backside power supply network is located on the backside, or between the device layer (i.e., transistors) and the wafer on which the device layer is formed. In an embodiment, the power supply 825 can be connected to the backside power supply network through a backside power supply network contact 824. In an embodiment, the grounds 820, 822 can be connected to the backside power supply network through backside power supply network contacts 819, 821 respectively. In an embodiment, the bit line 810 can be connected to the backside power supply network through a backside power supply network contact 809. In an embodiment, the bit line strip 812 can be connected to the backside power supply network through a backside power supply network contact 812A. In an embodiment, the power supply 825 can be connected to the backside power supply network through a backside power supply network contact 825A. In an embodiment, the grounds 820, 822 can be connected to the backside power supply network through backside power supply network contacts 820A, 822A respectively. In an embodiment, the bit line 810 can be connected to the backside power supply network through a backside power supply network contact 810A. In an embodiment, the bit line strip 812 can be connected to the backside power supply network through a backside power supply network contact 812A.

[0080] In an embodiment, the bit line 810 is connected to a bottom source / drain region 811. In an embodiment, the bit line strip 812 is connected to a bottom source / drain region 813. In an embodiment, the ground 820 is connected to a bottom source / drain region 821. In an embodiment, the ground 822 is connected to a bottom source / drain region 823. In an embodiment, the power supply 825 is connected to a shared bottom source / drain region 826. In an alternative embodiment, the shared bottom source / drain region 826 can be two separate and distinct bottom source / drain regions for each VTFET.

[0081] In an embodiment, as Figure 8 shown, the SRAM 800 cell includes cross-coupling 890. In an embodiment, the cross-coupling 890 is connected to front contacts 838, 858, 878, and front contact 892. In an embodiment, as described above, the front contact 838 is connected to a top source / drain region (not shown). In an embodiment, as described above, the front contact 858 is connected to a top source / drain region (not shown). In an embodiment, as described above, the front contact 878 is connected to a top source / drain region (not shown). In an embodiment, as described above, the front contact 892 is connected to a shared gate region (not shown).

[0082] The description of various embodiments of the present invention has been given for illustrative purposes, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology existing in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

[0083] In a preferred embodiment of the present invention described herein, there is provided a semiconductor memory cell, comprising: a plurality of vertical transfer field effect transistors (VTFETs) on a wafer, wherein each of the plurality of VTFETs is in a first layer, and wherein six of the plurality of VTFETs form the memory cell; and wherein at least one memory cell is in a row adjacent to at least one other memory cell.

[0084] In a preferred embodiment of the present invention described herein, there is provided a semiconductor SRAM, comprising: six vertical transfer field effect transistors (VTFETs) on a wafer, wherein the six VTFETs are in a first layer, and wherein the six VTFETs are in a first row.

[0085] In a preferred embodiment of the present invention described herein, there is provided a semiconductor memory array, comprising: a plurality of vertical transfer field effect transistors (VTFETs) on a wafer, wherein six of the plurality of VTFETs are arranged in a memory cell in one or more memory cells in a first layer on the wafer, and wherein each of the one or more memory cells is arranged in a single row. Each of the one or more memory cells may share a first continuous bottom source / drain region for a first VTFET and a second VTFET in each memory cell, wherein the first continuous bottom source / drain region is connected to a power supply network on the back surface of the wafer. Each of the one or more memory cells may share a second continuous bottom source / drain region for a third VTFET and a fourth VTFET in each memory cell, wherein the second continuous bottom source / drain region is connected to a power supply network on the back surface of the wafer. Each of the one or more memory cells may share a third continuous bottom source / drain region for a fifth VTFET and a fourth continuous bottom source / drain region for a sixth VTFET in each memory cell, wherein the third continuous bottom source / drain region is connected to a power supply network on the back surface of the wafer, and wherein the fourth continuous bottom source / drain region is connected to a power supply network on the back surface of the wafer.

[0086] In a preferred embodiment of the invention described herein, a semiconductor memory array is provided, comprising: one or more vertical transistors on a wafer, wherein the one or more vertical transistors are arranged in one or more memory cells in a first layer, and wherein each of the one or more memory cells is in a single row.

Claims

1. A semiconductor memory cell, comprising: Six vertical transmission field effect transistors (VTFETs) on a wafer, wherein the six VTFETs are in a first layer, and wherein the six VTFETs are in a first row.

2. The semiconductor memory cell according to claim 1, wherein, The power supply for two of the six VTFETs is connected to a power supply network on the back surface of the wafer.

3. The semiconductor memory cell according to claim 1, wherein, The ground connection for two of the six VTFETs is connected to a power supply network on the back surface of the wafer.

4. The semiconductor memory cell according to claim 1, wherein, The bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the back surface of the wafer, and wherein the word lines of two of the six VTFETs are connected to a power supply network on the front surface of the wafer.

5. The semiconductor memory cell according to claim 1, wherein, The bit lines and bit line strips of two of the six VTFETs are connected to a power supply network on the front surface of the wafer, and wherein the word lines of two of the six VTFETs are connected to a power supply network on the back surface of the wafer.

6. The semiconductor memory cell according to claim 1, wherein, A first metal wire is electrically connected to the source / drain regions of a first VTFET, a second VTFET, a third VTFET, the gate region of a fourth VTFET, and the gate region of a fifth VTFET.

7. The semiconductor memory cell according to claim 6, wherein A second metal wire is electrically connected to the gate region of the second VTFET, the gate region of the third VTFET, the source / drain region of the fourth VTFET, the source / drain region of the fifth VTFET, and the source / drain region of a sixth VTFET.

8. The semiconductor memory cell according to claim 6, wherein, The first metal wire is within the semiconductor memory cell.

9. The semiconductor memory cell according to claim 7, wherein, The second metal wire is within the semiconductor memory cell.

10. The semiconductor memory cell according to claim 1, wherein, The fin ends and gate ends of one or more of the six VTFETs are aligned with the RX edge.

Images