Co-packaged optical engine module and networking

Abstract

The invention discloses a co-packaging type optical engine module and networking. The co-packaged optical engine module comprises a photonic integrated chip and a processor bare core, and the photonic integrated chip is stacked above the processor bare core and electrically connected with the processor bare core; the photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the processor bare core; the processor die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of optical modules, and in particular to a co-packaged optical engine module and a network architecture. Background Art

[0002] Optical communication is a communication method that uses light waves as carriers and optical fibers or the atmosphere as transmission media to achieve information transmission. The basic principle of optical communication is to convert electrical signals into optical signals, transmit them through the transmission medium, and then convert the optical signals back into electrical signals at the receiving end. Therefore, optical communication has an extremely high transmission bandwidth and can meet the transmission requirements of a large amount of data. However, there is still a large room for improvement in the volume and transmission rate of existing optical modules used to support optical communication. Summary of the Invention

[0003] The main object of the present invention is to provide a co-packaged optical engine module, which includes a photonic integrated chip and a processor die. The photonic integrated chip is stacked above the processor die and electrically connected to the processor die. The photonic integrated chip is configured to receive and transmit data in the form of optical signals, and the optical signal transceiver of the photonic integrated chip is located on a side away from the processor die. The processor die is configured to process the data.

[0004] In one embodiment, the photonic integrated chip includes a flip-chip optical receiving array and a flip-chip optical transmitting array. The optical receiving array includes a first metal bonding end and an optical receiving end arranged opposite to each other, and the optical transmitting array includes a second metal bonding end and an optical transmitting end arranged opposite to each other. The first metal bonding end and the second metal bonding end are respectively bonded to the processor die through a solder ball array.

[0005] In one embodiment, the co-packaged optical engine module further includes: electrical chips, including a first electrical chip and a second electrical chip. The first electrical chip is disposed between the optical receiving array and the processor die; the second electrical chip is disposed between the optical transmitting array and the processor die.

[0006] In one embodiment, the electrical chips are selected from at least any one of a transimpedance amplifier, a clock recovery circuit, a high-speed memory, an electrical driver chip, a modulator driver chip, and a digital signal processing chip.

[0007] In one embodiment, the optical transmitting array includes a plurality of VCSEL units distributed in an array, and the optical receiving array includes a plurality of photodetector units distributed in an array.

[0008] In one embodiment, the co-packaged optical engine module further includes: a coupled optical fiber array, including a first coupled optical fiber array and a second coupled optical fiber array, where the first coupled optical fiber array is coupled to the light receiving ends of the light receiving array, and the second coupled optical fiber array is coupled to the light emitting ends of the light emitting array; and / or The coupled optical fiber array is a multi-core optical fiber array.

[0009] In one embodiment, at least one of an electric drive unit, an optical drive unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit is integrated in the processor die; and / or At least one of an electric drive unit, an optical drive unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit is integrated in the photonic integrated chip; The devices integrated in the processor die are different from or complementary to the devices integrated in the photonic integrated chip.

[0010] In one embodiment, the processor die is selected from any one of a graphics processing unit (GPU), a customized AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip.

[0011] In one embodiment, when the processor die is an application-specific integrated circuit (ASIC) chip, the application-specific integrated circuit (ASIC) chip includes an integrated modulator driver and a microcontroller, and the integrated modulator driver is configured to drive optical signal modulation using pulse amplitude modulation (PAM)-4 format or pulse amplitude modulation (PAM)-6 format or pulse amplitude modulation (PAM)-8 format.

[0012] In a second aspect, the present application further provides a co-packaged optical engine network, including a plurality of the co-packaged optical engine modules as described above, and the co-packaged optical engine modules are optically coupled to each other.

[0013] In one embodiment, the co-packaged optical engine modules are optically coupled to each other's photonic integrated chips by using an optical fiber array.

[0014] In one embodiment, the co-packaged optical engine network further includes a plurality of switching chips, and one switching chip is optically coupled between any two co-packaged optical engine modules.

[0015] The present invention has at least the following beneficial effects: In the co-packaged optical engine module and networking provided by the present invention, by directly packaging a photonic integrated chip above the bare processor die, the optical signal transceiver end of the photonic integrated chip is perpendicular to the upper surface of the bare processor die, and is used to transmit and receive high-speed communication data in the form of optical signals. The bare processor die is responsible for processing the high-speed communication data transmitted and received by the photonic integrated chip. Since the intermediate substrate between the traditional bare processor die and the photonic integrated chip is eliminated, the transmission path between data processing and data transmission and reception is further shortened, and the data transmission efficiency is further improved. In addition, this tight coupling can also significantly reduce signal loss and improve the integrity of high-speed signals. Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of a co-packaged optical engine module in an embodiment of the present application; Figure 2 It is a schematic structural diagram of a co-packaged optical engine module according to another embodiment provided by the present application; Figure 3 It is a schematic structural diagram of a co-packaged optical engine module according to another embodiment provided by the present invention; Figure 4 It is a schematic structural diagram of a co-packaged optical engine networking in an embodiment provided by the present invention; Figure 5 It is a schematic structural diagram of a co-packaged optical engine networking according to another embodiment provided by the present invention.

[0017] The implementation, functional features, and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the drawings. Detailed Embodiments

[0018] In order to make the object, technical solution, and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first client can be called the second client, and similarly, the second client can be called the first client.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. The meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. The meaning of "several" is at least one, such as one, two, etc., unless otherwise specifically defined.

[0021] With the development of the AI industry, "cloud data" companies represented by supercomputer companies and data centers have put forward higher requirements for the bandwidth, rate, and lower energy efficiency of the optical transmission relay module. Inside the traditional pluggable optical module used in data centers, it is gradually developing towards optical transmitters with higher modulation rates and modulation chips with advanced processes. Inside the traditional pluggable optical module used in data centers, it is gradually developing towards optical transmitters with higher modulation rates and modulation chips with advanced processes. For short-distance transmission scenarios, optical engine architectures of LPO (Linear-drive Pluggable Optics) and CPO (Co-Packaged Optics) are introduced. Both of them eliminate the DSP or CDR devices traditionally used for long-distance signal recovery, saving about 50% of the module power consumption. The CPO optoelectronic co-packaging solution eliminates the pluggable connection method between the PCB gold fingers and the switch side, and co-packages the optical engine and the ASIC chip onto the same substrate to achieve the purpose of increasing the bandwidth on the electrical I / O and optical I / O sides and reducing losses.

[0022] However, taking the relatively mainstream CPO packaging as an example, in its main packaging method, multiple dielectric substrates are required for data signal transfer between the electro-optical chips EIC, PIC, and GPU (such as Organic package, TSMC interposer, PCB). Although this has significantly reduced the signal transmission loss compared to the traditional solution, the signal transmission path will still be increased due to the existence of multiple dielectric substrates, resulting in a certain signal transmission loss.

[0023] Based on this, as Figures 1 - 5 shown, the present application provides a co-packaged optical engine module, aiming to solve the above technical problems, with a view to further reducing signal transmission loss and improving data transmission efficiency. As Figure 1As shown, the co-packaged optical engine module may include a photonic integrated chip 10 and a processor die 20. The photonic integrated chip 10 is stacked above the processor die 20 and electrically connected to the processor die 20. The photonic integrated chip 10 is configured to transmit and receive data in the form of optical signals, and the optical signal transceiver end of the photonic integrated chip 10 is located on the side away from the processor die 20. The processor die 20 is configured to process the data. Specifically, the data transmitted and received by the photonic integrated chip 10 is high-speed communication data, which is modulated and transmitted in the form of optical signals. Compared with the traditional copper wire transmission method, optical signals have a larger transmission bandwidth and transmission speed, and are gradually becoming the future mainstream communication method. Optical communication is a technology in which light waves are used as signal carriers and transmitted between two nodes via optical fibers. An optical communication system mainly includes an optical transmitter and an optical receiver. Through an optical transceiver, the received optical signal can be converted into an electrical signal that can be processed by an integrated circuit (IC), or the processed electrical signal can be converted into an optical signal to be transmitted via an optical fiber. Therefore, the purpose of communication can be achieved.

[0024] In one example, the photonic integrated chip 10 of the present application can be stacked above the processor die 20 by means of flip-chip bonding. At this time, the processor die 20 is electrically connected to the photonic integrated chip 10. Specifically, reference can be continued to Figure 1 The photonic integrated chip 10 may include a flip-chip optical receiving array 110 and a flip-chip optical transmitting array 120. The optical receiving array 110 may include a first metal bonding end (not shown in the figure) and an optical receiving end (not shown in the figure) arranged opposite to each other. The optical transmitting array 120 may include a second metal bonding end (not shown in the figure) and an optical transmitting end (not shown in the figure) arranged opposite to each other. The first metal bonding end and the second metal bonding end are respectively bonded to the processor die 20 through a solder ball array (132, 134). That is to say, auxiliary reference can be made to Figure 2, the upper surface of the processor die 20 is provided with an area bonded to the photonics integrated chip 10. Compared with the traditional photonics integrated chip that needs to be electrically connected to the processor die through a silicon dielectric substrate and a TMSC interposer, this application can not only shorten the signal transmission loss but also save the material costs of the silicon dielectric substrate, TMSC interposer, etc. Depending on the size of the photonics integrated chip 10, the ball grid arrays 132, 134 can be selected as a ball grid array (BGA Ball), a bump array, or a micro-bump (μbump) array. It can be understood that both the ball grid arrays 132, 134 are used to achieve electrical connection and mechanical fixation, and are key components to ensure that the optical interconnection structure can work properly, realize signal transmission, and provide physical support. Among them, the diameter range of the metal solder balls is usually between 0.25 mm and 0.76 mm, the diameter of the bumps is usually between 100 μm and 150 μm, the micro-bumps have the smallest size, and the diameter is usually between a few microns and dozens of microns. At the smallest, it can be less than 2 μm. Based on different sizes, the difficulty of the preparation processes for the solder balls, bumps, and micro-bumps gradually increases. In this specific embodiment, the ball grid arrays 132, 134 are selected as micro-bump arrays.

[0025] Further, to enable the optical signal transceiver ends of the photon integrated chip 10 to be perpendicular to the upper surface of the processor die 10. The optical receiving array 110 of the present application may adopt photodiodes (PDs), and the number of photodiodes is multiple. The multiple photodiodes are arranged in an array. Exemplarily, the multiple photodiodes may be arranged in a regular hexagon, or a regular quadrilateral, or a regular pentagon. The present application does not limit this. The photosensitive surface of the photodiode is flush with the upper surface of the processor die 20. The optical transmitting array 120 may adopt vertical-cavity surface-emitting lasers (VCSELs), and the number of vertical-cavity surface-emitting lasers is multiple. The multiple vertical-cavity surface-emitting lasers are arranged in an array. Each laser includes multiple light-emitting channels. The multiple light-emitting channels may be arranged in a regular hexagon, or a regular quadrilateral, or a regular pentagon. The present application does not limit this. Further, the present application may adopt 4 vertical-cavity surface-emitting lasers, and the four vertical-cavity surface-emitting lasers may be configured to emit lasers with at least four wavelengths. These lasers are modulated to convert N electrical data into optical signals in N optical channels. Optionally, the four wavelengths may be selected from the group of 1270 nm, 1280 nm, 1290 nm, and 1300 nm or the group of 1300 nm, 1310 nm, 1320 nm, and 1330 nm with a smaller channel spacing. Optionally, each wavelength is selected from the range of 1270 nm to 1330 nm to serve as a CWDM channel to support optical signal transmission in high-speed (e.g., 100 Gbps or higher) data communication. In other embodiments, the photon integrated chip 10 with a similar configuration may be formed with more than 4 wavelengths. Optionally, 4 or more wavelengths may be selected to have half the spacing compared to the nominal CWDM channels.

[0026] Vertical-cavity surface-emitting lasers have advantages such as low power consumption, easy integration, low cost, and high reliability, and are widely used in fields such as optical communication, optical interconnection, and optical sensing. Compared with edge-emitting lasers (EELs), they have more unique advantages in the field of optical communication or optical interconnection. For example, more vertical-cavity surface-emitting lasers can be placed under the same area, thereby increasing the signal transmission density.

[0027] In one example, reference may be made to Figures 1 - 3, the co-packaged optical engine module may further include a coupling fiber array (not shown in the figure). The coupling fiber array may include a first coupling fiber array 510 and a second coupling fiber array 520. The first coupling fiber array 510 is coupled to the light receiving ends of the light receiving array 110, and the second coupling fiber array 520 is coupled to the light emitting ends of the light emitting array 120. Further, in order to match the aforementioned light receiving array 110 and light emitting array 120, the first coupling fiber array 110 and the second coupling fiber array 120 may be selected as multi-core fiber arrays. The number of optical fibers in each fiber array matches the number of devices in the light emitting array 120 or the light receiving array 110. For example, one photodiode is correspondingly coupled to one optical fiber, and one vertical cavity surface emitting laser is correspondingly coupled to one optical fiber. Using a multi-core fiber array can increase the data transmission density.

[0028] In one example, in addition to including the above modules, the co-packaged optical engine module may further include an electrical host interface (not shown in the figure), configured to receive electrical host data input via an N 25G (NRZ) or 56G (PAM4) or 100G (PAM4) channel; and a digital processor (not shown in the figure), which processes data signals through a clock recovery chip with N to N channels. Optionally, the digital processor processes data signals via a Gearbox N to M channel, where N is a multiple of M. Optionally, the electrical host interface is configured in one or more chips, and the electrical host interface includes forward error correction (FEC) channel coding, which is used to control errors in data transmission over unreliable or noisy communication channels.

[0029] In one example, reference may be made to Figure 3, the co-packaged optical engine module may further include an electrical chip (not shown in the figure), and the electrical chip may include a first electrical chip 310 and a second electrical chip 320; the first electrical chip 310 is disposed between the optical receiving array 110 and the processor die 20; the second electrical chip 320 is disposed between the optical transmitting array 120 and the processor die 20. Taking the first electrical chip 310 and the optical receiving array 110 as an example, the first electrical chip 310 is arranged below the optical receiving array 110, so that it will not block the detection light path of the optical transmitting array 110, thereby improving the light utilization rate of the optical transmitting array 110, reducing losses, and improving the heat dissipation capacity. Specifically, TSV vias may be formed in the first electrical chip 310, and on the side of the first electrical chip 310 welded to the processor die 20, the size of the ball grid array used is larger than the size of the ball grid array used between the first electrical chip 310 and the optical receiving array 110; for example, a bump array is used for welding between the first electrical chip 310 and the processor die 20, and a micro-bump array is used for welding between the first electrical chip 310 and the optical receiving array 110. The first electrical chip 310 is used to provide a modulation drive signal. Further, the first electrical chip 310 may be selected from at least any one of a transimpedance amplifier TIA, a clock recovery unit, a high-speed memory HBM, an electrical drive chip, a modulator drive chip, and a digital signal processing chip DSP. For example, the first electrical chip 310 is a traditional EIC chip, or some additional components such as a high-speed memory HBM may be integrated on the basis of the traditional EIC chip. Taking the traditional EIC chip as an example, a photodiode in the optical receiving array 110 individually detects each optical signal and converts it into a current signal that is transmitted to the transimpedance amplifier (TIA) and processed by the transimpedance amplifier module to generate a voltage signal. The digital signal processing DSP chip is configured to provide the module control and power supply required for operating the co-packaged optical engine module. Optionally, the DSP chip includes a gearbox or retimer chip for converting analog signals into digital signals through N-to-N channel electrical data transmission, a digital processor for processing digital signals, one or more interface devices for communicating with an external electrical host, and a current driver for driving four laser chips.

[0030] Optionally, the modulator drive chip may adopt a PAM-N (N is an integer) modulation protocol or an NRZ modulation protocol to modulate the optical signal.

[0031] In one embodiment, reference may be made to Figure 2 , in order to implement signal control between the processor die 20 and the photon integration chip 10, at least any one of an electrical drive unit, an optical drive unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator drive unit, and a digital signal processing unit is integrated in the processor die 20. In Figure 2As shown, unit 1, unit 2, unit 3, unit 4... unit N are integrated in the processor die 20. Unit 1 can be selected as a transimpedance amplification unit, and unit 4 can be selected as a modulator driver unit or an electrical driver unit or an optical driver unit; unit 1 can be selected as a modulator driver unit PHY, unit 3 can be selected as a clock recovery unit CDR, and unit N can be selected and adjusted from the remaining units. For example, a digital signal processing unit DSP can be selected, or a memory unit can be selected, or a microcontroller can be selected. The main purpose is to integrate the main functional devices of the original EIC chip in the processor die 20, thus eliminating the intermediate EIC chip link. The microcontroller is connected to a corresponding unit or device and is configured to control the operations of the digital signal processing DSP chip, the modulator driver unit, the transimpedance amplifier TIA, and the interfaces therein.

[0032] In one embodiment, in addition to integrating the main functions of the original EIC chip in the processor die 20, the main functional devices of the EIC chip can also be integrated in the photon integration chip 10, making the photon integration chip 10 different from the traditional PIC chip and becoming an EPIC chip. The EPIC chip can be fabricated based on the CMOS process. Similar to the previous embodiment, at least any one of an electrical driver unit, an optical driver unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driver unit, and a digital signal processing unit can be integrated in the photon integration chip 10.

[0033] Furthermore, in order to better allocate the devices and achieve the best transmission efficiency, the devices integrated in the processor die 20 and the devices integrated in the photon integration chip 10 can be set to be different or complementary. For example, the electrical driver unit, the optical driver unit, the transimpedance amplification unit, the clock recovery unit, and the modulator driver unit are integrated in the photon integration chip 10, and the remaining memory unit, microcontroller, and digital signal processing unit are integrated in the processor die 20, and the corresponding electrical connections are achieved. Another example is that the electrical driver unit, the optical driver unit, and the modulator driver unit are integrated in the photon integration chip 10, and the remaining transimpedance amplification unit, clock recovery unit, modulator driver unit, memory unit, microcontroller, and digital signal processing unit are integrated in the processor die 20.

[0034] In one example, the processor die 20 can be selected from any one of a graphics processing unit (GPU), a customized AI accelerator (XPU), or an application-specific integrated circuit (ASIC) chip. Among them, the customized AI accelerator XPU is not a single chip, but a strategic concept of heterogeneous computing, aiming to address complex computing requirements through a diverse combination of hardware. Its essence is "Right Tool for the Right Job", that is, using the most suitable hardware to process specific tasks, thereby improving the overall system efficiency. The customized AI accelerator XPU can be, for example, at least any one of a CPU, an NPU, an FPGA, or an AI accelerator. Exemplarily, the XPU can be a CPU + GPU + NPU to accelerate the training of large-scale models. The ASIC chip includes a SerDes chip for encoding and decoding data through a DSP interface. Further, when the processor die 20 is an application-specific integrated circuit (ASIC) chip, the application-specific integrated circuit (ASIC) chip can include an integrated modulation driver and a microcontroller. The integrated modulation driver is configured to drive optical signal modulation using pulse amplitude modulation (PAM)-4 format, or pulse amplitude modulation (PAM)-6 format, or pulse amplitude modulation (PAM)-8 format. The microcontroller is configured to control the operation of the integrated modulation driver.

[0035] Further, since the computing power of a single optical engine module is gradually approaching the physical limit, in order to meet the growing computing requirements, it has become an inevitable trend for multiple optical engine modules to work together collaboratively.

[0036] Based on this, as Figures 4 - 5 ... This application also provides a co-packaged optical engine network, which can include several co-packaged optical engine modules 20a, 20b... as described above. The co-packaged optical engine modules are optically coupled to each other. Further, as Figure 4As shown, an optical fiber array can be used to optically couple and connect the respective photonic integrated chips 10 between the co-packaged optical engine module 20a and the co-packaged optical engine module 20b. In this specific embodiment, when connecting the co-packaged optical engine module 20a and the co-packaged optical engine module 20b through an optical fiber array, specifically, the optical emission array 120 in the co-packaged optical engine module 20a is optically coupled and connected to the optical reception array 110 in the co-packaged optical engine module 20b, while the optical reception array 120 of the co-packaged optical engine module 20a is optically coupled to the optical emission array 110 of the previous co-packaged optical engine module, and the optical emission array 110 of the co-packaged optical engine module 20b is optically coupled to the optical reception array 120 of the next co-packaged optical engine module, thereby realizing the networking of the co-packaged optical module. It can be understood that in order to achieve optical interconnection between different optical engine modules, functional devices or protocol interfaces of the switching chip SWITCH can be further integrated in the co-packaged optical engine module 20, or the switching chip SWITCH can be directly removed, and the respective transceiver arrays of the optical engine modules are used to transmit and exchange optical signals.

[0037] Furthermore, as Figure 5 shown, if the switching chip SWITCH is not omitted, the co-packaged optical engine networking can further include several switching chips 40, and one of the switching chips 40 is optically coupled and connected between any two co-packaged optical engine modules 20a and 20b. As Figure 5 shown, the switching chip 40 is also provided with an optical emission array 120 and an optical reception array 110. The optical reception array 110 on the switching chip 40 is optically coupled to the optical emission array 120 of the co-packaged optical engine module 20a, and the optical emission array 120 on the switching chip 40 is optically coupled to the optical reception array 110 of the co-packaged optical engine module 20a. In this way, data access and interaction between different co-packaged optical engine modules can be realized.

[0038] In this specific embodiment, by connecting the transceiver arrays in different optical engine modules through an optical fiber array, direct data exchange between different optical engine modules and memory data access between the high-speed storage units HBM of different optical engine modules can be allowed. This design not only reduces the latency of data transmission but also can greatly improve the throughput of the entire system.

[0039] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations can be made in light of the above disclosure, or can be obtained from the practice of the embodiments. Additionally, any of the embodiments described herein can be combined, unless the foregoing disclosure specifically provides a reason why one or more of the embodiments cannot be combined.

[0040] Even if particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. As used herein, the phrase referring to a list of items “at least one of” refers to any combination of these items, including a single member. By way of example, “at least one of the following: a, b, or c” is intended to cover a, b, c, a - b, a - c, b - c, and a - b - c, as well as any combination having multiple identical items.

[0041] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) are described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise expressly required (e.g., by using “a first component” and “a second component” or other language that differentiates components in the claims), such language is intended to cover a single component that performs or is configured to perform all operations, a group of components that jointly perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform the operations. For example, when a claim is in the form “one or more components are configured to: perform X; perform Y; and perform Z,” the claim should be interpreted to mean “one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (also possibly different) components are configured to perform Z.”

[0042] The components, acts, or instructions used herein should not be construed as critical or essential unless expressly described as such. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Further, as used herein, the article "the" is intended to include one or more items referenced in conjunction with the article "the" and may be used interchangeably with "the one or more." Additionally, as used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with "one or more." In instances where only one item is intended, the phrase "only one" or similar language is used. Additionally, as used herein, the terms "having," "including," "carrying," etc. are intended to be open-ended terms. Further, unless expressly stated otherwise, the phrase "based on" is intended to mean "at least partially based on." Additionally, as used herein, unless expressly stated otherwise (e.g., if used in combination with "any" or "only one of"), the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or." Further, for ease of description, spatial relative terms such as "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (one or more) element or (one or more) feature illustrated in the figures. Except for the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device, apparatus, and / or element during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

Claims

1. A co-packaged optical engine module, characterized in that, It includes a photonic integrated chip and a processor die. The photonic integrated chip is stacked above the processor die and electrically connected to the processor die. The photonic integrated chip is configured to transmit and receive data in the form of optical signals, and the optical signal transceiver of the photonic integrated chip is located on the side far from the processor die. The processor die is configured to process the data.

2. The co-packaged optical engine module according to claim 1, characterized in that, The photonic integrated chip includes an inverted optical receiving array and an inverted optical transmitting array. The optical receiving array includes a first metal bonding end and an optical receiving end arranged opposite to each other. The optical transmitting array includes a second metal bonding end and an optical transmitting end arranged opposite to each other. The first metal bonding end and the second metal bonding end are respectively bonded to the processor die through a solder ball array.

3. The co-packaged optical engine module according to claim 2, wherein It further includes: electrical chips, including a first electrical chip and a second electrical chip; The first electrical chip is disposed between the optical receiving array and the processor die; the second electrical chip is disposed between the optical transmitting array and the processor die.

4. The co-packaged optical engine module according to claim 3, characterized in that, The electrical chip is selected from at least any one of a transimpedance amplifier, a clock recovery unit, a high-speed memory, an electrical driver chip, a modulator driver chip, and a digital signal processing chip.

5. The co-packaged optical engine module according to claim 2, wherein The optical transmitting array includes a plurality of VCSEL units distributed in an array, and the optical receiving array includes a plurality of photodetector units distributed in an array.

6. The co-packaged optical engine module according to claim 2, characterized in that, It further includes: a coupling fiber array, including a first coupling fiber array and a second coupling fiber array. The first coupling fiber array is coupled to the optical receiving end of the optical receiving array, and the second coupling fiber array is coupled to the optical transmitting end of the optical transmitting array; and / or The coupling fiber array is a multi-core fiber array.

7. The co-packaged optical engine module according to claim 1, wherein At least any one of an electrical driving unit, an optical driving unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the processor die; and / or At least any one of an electrical driving unit, an optical driving unit, a transimpedance amplification unit, a clock recovery unit, a memory unit, a microcontroller, a modulator driving unit, and a digital signal processing unit is integrated in the photonic integrated chip; Moreover, the devices integrated in the processor die are different from or complementary to the devices integrated in the photonic integrated chip.

8. The co-packaged optical engine module according to claim 1, characterized in that, The processor die is selected from any one of a graphics processing unit GPU, a customized AI accelerator XPU, or an application-specific integrated circuit ASIC chip.

9. The co-packaged optical engine module according to claim 8, wherein When the processor die is an application-specific integrated circuit ASIC chip, the application-specific integrated circuit ASIC chip includes an integrated modulator driver and a microcontroller. The integrated modulator driver is configured to drive optical signal modulation using pulse amplitude modulation PAM-4 format or pulse amplitude modulation PAM-6 format or pulse amplitude modulation PAM-8 format.

10. A co-packaged optical engine networking, characterized in that, It includes a plurality of co-packaged optical engine modules as described in any one of claims 1-9, and the co-packaged optical engine modules are optically coupled to each other.

11. The co-packaged optical engine networking according to claim 10, characterized in that, The photonic integrated chips of the co-packaged optical engine modules are optically coupled to each other by using a fiber array.

12. The co-packaged optical engine networking according to claim 10, characterized in that, It further includes a plurality of switching chips, and one of the switching chips is optically coupled between any two co-packaged optical engine modules.

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