Multi-source heterogeneous data processing method and system based on test chip

Abstract

The invention discloses a multi-source heterogeneous data processing method and system based on a test chip, and the method comprises the steps: employing a distributed message queue to access a multi-protocol data stream in real time, collecting the multi-source heterogeneous data related to a chip test, and carrying out the normalization preprocessing; performing cross-domain spatio-temporal feature alignment and mapping on the preprocessed multi-source heterogeneous data, constructing a hybrid incidence matrix based on linear correlation degree and nonlinear correlation degree, extracting three-dimensional joint features, and generating a dynamic metadata tag; generating nodes and edges by using the incidence matrix and the extracted three-dimensional joint features, constructing a parameter association graph structure, performing graph embedding training and generating an index structure, positioning Top-K candidates based on the index structure by using query features and labels, and sorting and returning a result according to a comprehensive distance; the problem that cross-domain association analysis is difficult to carry out due to the fact that the format difference of multi-source heterogeneous data generated by existing chip testing is large is solved, and the precision and efficiency of multi-source heterogeneous data processing are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-source heterogeneous data processing, and particularly relates to a multi-source heterogeneous data processing method and system based on a test chip. Background Art

[0002] The purpose of chip testing is to eliminate defective products with unqualified circuits or faults. At present, the chip market is highly competitive, and it is required that the product be launched quickly with low economic costs. The testing cost accounts for too high a proportion in the total production cost. If the product design is unreasonable but not found in the design verification, the product will enter the manufacturing stage according to the development process. However, the cost of detecting and eliminating problems during the manufacturing process is ten times higher than that of eliminating them in the design stage. It can be seen that the costs of detecting and eliminating product faults at different stages vary greatly. Especially when chips, circuit boards, and systems are more complex at present, the increase in costs has far exceeded ten times. Therefore, various tests are carried out on chips; For different test links including functional testing, aging testing, and electrical performance testing, independent terminals are used. Each terminal includes data formats such as CSV, binary logs, images, and XML. Moreover, the simulation data, test data, and production line yield data formed by the test chip belong to different systems, resulting in a large amount of test data that not only has large format differences but is also difficult to perform cross-domain correlation analysis. For example, the timing data of chip package testing and the electrical parameter structure data of wafer testing are difficult to synchronize and analyze. In addition, the existing data lake for chip testing has difficulties in retrieval due to the lack of metadata tags, that is, when the packaged chip fails, it is impossible to quickly associate with specific parameter anomalies in the previous wafer testing and trace the root cause. Summary of the Invention

[0003] The purpose of the present invention is to provide a multi-source heterogeneous data processing method and system based on a test chip to solve the problems raised in the above background art.

[0004] To solve the above technical problems, the present invention provides the following technical solutions: A multi-source heterogeneous data processing method based on a test chip, including the following steps: S1: Real-time access to multi-protocol data streams using a distributed message queue, collect multi-source heterogeneous data related to chip testing, and perform normalized preprocessing; Preferably, perform normalization processing on the obtained multi-modal data related to chip testing. Among them, for optical image data, use the dynamic binarization algorithm to calculate the gray-scale statistic of the image, determine the adaptive threshold, and perform binarization to extract the defect contour, that is, perform local correction by moving the window; Align the electrical performance data using cubic spline interpolation, and construct a piecewise cubic polynomial based on the original timing data of the aging test. That is, the formula of the cubic spline interpolation function is: , where, is the third - degree polynomial function of the j - th segment, describing the signal within the time interval . is the timestamp of the j - th data point, such as the sampling moment in the aging test., and and and are the polynomial coefficients, determined by three constraints of continuity, first - derivative continuity, and second - derivative continuity. Among them, the continuity constraint is: the function values at the connection point of adjacent segments are equal, that is . The first - derivative continuity constraint is: . The second - derivative continuity constraint is: . Then, output a uniformly sampled sequence aligned to the set frequency. The extraction of log key parameters is performed by automatically matching templates through the regular expression template library using the defined parameter capture rules. At the same time, by constructing an electrical parameter feature matrix, calculate the Euclidean distance between each missing sample and all complete samples, and select the k nearest neighbors for weighted filling.

[0005] S2: Align and map the cross - domain spatio - temporal features of the pre - processed multi - source heterogeneous data, and construct a hybrid correlation matrix based on the linear correlation degree and the non - linear correlation degree ; Preferably, construct a cross - domain correlation matrix, that is, calculate the linear correlation degree and the non - linear correlation degree , and then construct a hybrid correlation matrix based on the linear correlation degree . The specific calculation formula is: where . Among them, is the covariance measuring the linear correlation, are the wafer test parameters, are the test parameters after packaging, and are the standard deviations used to normalize the covariance value, is the total number of test samples, is the wafer parameter non - linear kernel function, is the package parameter non - linear kernel function, is the parameter of the n - th chip in the wafer test stage of the original measured value, is the parameter of the n - th chip in the package test stage of the original measured value, is the mean value of the wafer parameters, is the mean value of the package parameters, is a dynamic weight that can be automatically adjusted according to the parameter distribution characteristics.

[0006] S3: Extract three-dimensional joint features based on the multi-modal data and the parameter sequence after spatio-temporal alignment, and generate dynamic metadata labels; Preferably, extracting the multi-modal joint features includes: extracting the three-dimensional joint features of the time-domain features, frequency-domain features, and spatio-temporal alignment features, and the extraction formula is: where, is the three-dimensional joint feature of the th chip, with the dimension of d, , , are the modal weight coefficients, dynamically calculated through the cross-domain correlation matrix, specifically: , , , is the wavelet transform feature of the time series data, is the histogram of oriented gradients feature of the image, is the principal component analysis dimensionality reduction feature of the electrical performance parameters.

[0007] Preferably, based on the three-dimensional joint feature generate a candidate label set by k-nearest neighbor majority voting, screen the generated candidate label set according to the set process rule library, calculate the comprehensive score of the screened qualified dynamic labels, and select the label with the highest comprehensive score for output. Among them, the formula for generating the candidate label set is: where, is the dynamic label of the th chip generated, C is a preset label set defined by the process knowledge base, is the weight of the feature point, calculated through the Gini importance of the random forest, that is, , is the constraint strength coefficient, is the physical constraint function, used to verify the process rationality of the label c. At the same time, use the cross-domain correlation matrix to guide the generation of high-dimensional joint features.

[0008] S4: Use the correlation matrix and the extracted three-dimensional joint features to generate nodes and edges, construct a parameter correlation graph structure, and perform graph embedding training to generate an index structure; Preferably, generating the index structure specifically includes the following steps: S4-1: Generate nodes and edges based on the correlation matrix and three-dimensional joint features, calculate the weights of hybrid edges, filter the edges below the set threshold, and construct a parameter correlation graph; S4-2: Generate a node sequence, jointly optimize the topological loss and label alignment loss, and train an embedding model so that the embedding vectors can encode both the structure and semantics simultaneously; S4-3: Assign levels according to the norms of the embedding vectors, construct an index corresponding to the multi-layer graph structure, and optimize the number of node connections in each layer.

[0009] S5: The user utilizes the query features and labels to locate the Top-K candidates based on the generated index structure, and sort and return the results according to the comprehensive distance.

[0010] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: (1) By using a distributed message queue to access multi-protocol data streams in real time, collect multi-source heterogeneous data related to chip testing, and perform normalized preprocessing, the present invention solves the problem that the large differences in the formats of multi-source heterogeneous data generated by existing chip testing make it difficult to perform cross-domain correlation analysis, and improves the accuracy and efficiency of multi-source heterogeneous data processing. (2) By introducing a non-linear kernel function, the present invention further breaks through the limitations of traditional linear correlation analysis, can accurately capture the complex dependence relationships between chip parameters, and provides a more comprehensive analysis in combination with a hybrid correlation matrix with dynamic weights, especially suitable for the analysis of the increasingly significant non-linear effects in advanced process nodes. (3) The use of a graph structure index in the present invention not only improves the retrieval efficiency but also enhances the cross-domain correlation analysis ability, enabling the rapid tracing of package failures to abnormal wafer test parameters, and significantly improving the retrieval speed compared with traditional data lake solutions. Description of the Drawings

[0011] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention, and do not constitute a limitation to the present invention. In the drawings: Figure 1 is a flowchart of the steps of the multi-source heterogeneous data processing method provided by the embodiment of the present invention; Figure 2 is a schematic diagram of the functional unit composition of the multi-source heterogeneous data processing system provided by the embodiment of the present invention. Detailed Embodiments

[0012] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in conjunction with the drawings and preferred embodiments, details the specific implementation manners, structures, features, and effects according to the present invention as follows.

[0013] The present invention provides a technical solution: a multi-source heterogeneous data processing method based on a test chip, including the following steps: S1: Use a distributed message queue to access multi-protocol data streams in real time, collect multi-source heterogeneous data related to chip testing, and perform normalized preprocessing; In this embodiment, the original multi-source heterogeneous data related to chip testing is synchronously obtained from a functional test machine, an electrical performance tester, an aging test system, an optical detection device, and a yield management system. Specifically, the original multi-source heterogeneous data includes test log data in CSV format containing voltage, current, and frequency parameters output by the functional test machine through the GPIB interface, electrical characteristic data in XML format including I-V curves, leakage current, and on-resistance transmitted by the electrical performance tester through the LXI protocol, timing data containing power consumption change curves under temperature cycling output by the aging test system through Modbus TCP, defect detection image data transmitted by the optical detection device through the GigE Vision protocol, and structured data including wafer Map and Bin classification statistics obtained by the yield management system through the ODBC interface. A unified data bus is constructed using a 3-node Apache Kafka cluster, and each chip testing device is connected through an adapter plugin. Topics are divided according to the chip testing stage, and each Topic is set with independent partitions to ensure the timing of data in each testing stage; Exemplarily, perform normalization processing on the obtained multi-modal data related to chip testing. Among them, for optical image data, use the dynamic binarization algorithm to calculate the gray-scale statistic of the image, determine the adaptive threshold, and perform binarization to extract the defect contour, that is, perform local correction by moving the window; use cubic spline interpolation to align the electrical performance data, and construct a piecewise cubic polynomial based on the original timing data of the aging test. That is, the formula of the cubic spline interpolation function is: , where is the j-th piecewise cubic polynomial function, describing the signal in the time interval inside, is the timestamp of the j-th data point, such as the sampling moment in the aging test., , , , are polynomial coefficients, determined by three constraints of continuity, first derivative continuity, and second derivative continuity. Among them, the continuity constraint is: the function values of adjacent segments are equal at the connection point , that is , the first derivative continuity constraint is: , and the second derivative continuity constraint is: , and then output a uniform sampling sequence aligned to the set frequency. The extraction of log key parameters is automatically template-matched through a regular expression template library using defined parameter capture rules. At the same time, by constructing an electrical parameter feature matrix, the Euclidean distance between each missing sample and all complete samples is calculated, and the k nearest neighbors with the closest distance are selected for weighted filling.

[0014] S2: Align and map the cross-domain spatio-temporal features of the preprocessed multi-source heterogeneous data, and based on the linear correlation degree and the non-linear correlation degree construct a hybrid correlation matrix ; In this embodiment, the wafer data and packaging coordinates in the preprocessed structured data are mapped using the dynamic process parameter compensation formula. The specific dynamic process parameter compensation formula is: , where , are the coordinates of the chip coordinate system after packaging, used to locate physical defects during failure analysis, is the rotation matrix, representing the angular offset during wafer dicing, , are the coordinates of the wafer coordinate system, which are the defect positions located by the optical detection device in S1, is the scaling factor, and are the offset compensation amounts, determined by the reference point error of the packaging wire bonding process, and are measured in real time through an on-line calibration system and , and then introduce a thermo-mechanical coupling model to calculate , to solve the thermal deformation problem during the packaging process; Exemplarily, global alignment is performed on the timing data of multiple test links, and the alignment formula is: where is the cumulative distance matrix, representing the minimum path cost of aligning and , is the th timing data point of the functional test, is the th timing data point of the aging test, and dynamic time warping is performed on the timing data generated in the test chip by test link, that is, the dynamic time warping algorithm is applied separately to each segment. By defining the stage weight where is the total number of test stages, is the stage weight, and the longer the time proportion, the higher the weight. is the time length of the s-th segment, is the cumulative distance matrix of the s-th segment. By applying dynamic time warping in segments, the overfitting problem of global alignment is avoided. And by introducing a time weight factor, the alignment accuracy of key stages can be further improved; Furthermore, a cross-domain correlation matrix is constructed, that is, the linear correlation degree and the non-linear correlation degree are calculated, and then based on the linear correlation degree and the non-linear correlation degree a hybrid correlation matrix is constructed , and the specific calculation formula is: where, is the covariance for measuring linear correlation, are wafer test parameters, are test parameters after packaging, and are the standard deviations for normalizing the covariance values, is the total number of test samples, is the non-linear kernel function of wafer parameters, is the non-linear kernel function of packaging parameters, is the -th chip's parameters in the wafer test stage 's original measured value, is the -th chip's parameters in the package test stage 's original measured value, is the mean value of wafer parameters, is the mean value of packaging parameters, is a dynamic weight that can be automatically adjusted according to the parameter distribution characteristics.

[0015] S3: Extract three-dimensional joint features based on multi-modal data and the parameter sequence after spatio-temporal alignment, and generate dynamic metadata labels; In this embodiment, extracting multi-modal joint features includes: extracting three-dimensional joint features of time-domain features, frequency-domain features, and spatio-temporal alignment features. The extraction formula is: where, is the three-dimensional joint feature of the -th chip, with dimension d, , , are modal weight coefficients, dynamically calculated through the cross-domain correlation matrix. Specifically: , , , It is the wavelet transform feature of time series data, It is the histogram of oriented gradients feature of the image, It is the dimensionality reduction feature obtained by principal component analysis of electrical performance parameters.

[0016] Exemplarily, based on the three-dimensional joint feature a k-nearest neighbor majority vote is used to generate a candidate label set, the generated candidate label set is screened according to a set process rule library, a comprehensive score is calculated for the qualified dynamic labels, and the label with the highest comprehensive score is selected for output. Among them, the formula for generating the candidate label set is: Among them, is the dynamic label of the th chip generated, C is a preset label set defined by the process knowledge base, is the weight of the feature point, which is calculated through the Gini importance of the random forest, that is, , is the constraint strength coefficient, is the physical constraint function, which is used to verify the process rationality of the label c. At the same time, a cross-domain correlation matrix is used to guide the generation of high-dimensional joint features; S4: Use the correlation matrix and the extracted three-dimensional joint features to generate nodes and edges, construct a parameter correlation graph structure, perform graph embedding training, and generate an index structure; In this embodiment, it specifically includes the following steps: S4-1: Generate nodes and edges based on the correlation matrix and the three-dimensional joint features, calculate the mixed edge weights, filter the edges below the set threshold, and construct a parameter correlation graph; Exemplarily, the generated node features are: , is the feature vector of the node , which is spliced by the three-dimensional joint feature and the dynamic label encoding . The formula for calculating the mixed edge weights is: , among which, is the edge weight between the node and , is the correlation weight coefficient dynamically adjusted according to the parameter distribution, is the similarity weight, is the node feature similarity. By comprehensively considering cross-domain correlation and feature similarity, the semantic consistency of the constructed parameter correlation graph is improved.

[0017] S4-2: Generate a node sequence, jointly optimize the topology loss and the label alignment loss, and train an embedding model so that the embedding vectors encode both structure and semantics simultaneously; Exemplarily, generating a node sequence is suitable for preserving the structural characteristics of a graph, and the objective function used is: , where is a graph embedding function for mapping nodes into low-dimensional vectors, is the node 's neighbor sequence, generated by the biased random walk of Node2Vec, is the alignment weight, is the alignment loss between the embedding vector and the label, where , is the dynamic label encoding of node , is the Sigmoid function, is the label 's embedding vector. By introducing the label alignment loss, the embedding vectors encode both structure and semantics simultaneously, and the retrieval results can be reversely interpreted through the label vector .

[0018] S4-3: Assign levels according to the embedding vector norms, construct an index corresponding to the multi-layer graph structure, and optimize the number of node connections in each layer; Exemplarily, the formula for index construction is: , where is the level of node in the index, is the L2 norm of the embedding vector , is the minimum norm value. Dynamically assign levels according to the embedding vector norms, place important nodes at higher levels to accelerate retrieval, and comprehensively consider the embedding distance and the label distance to enhance the semantic relevance of the retrieval results.

[0019] S5: Locate the Top-K candidates based on the query feature and the label based on the generated index structure, and sort and return the results according to the comprehensive distance.

[0020] Exemplarily, the graph structure index not only improves the retrieval efficiency but also enhances the cross-domain correlation analysis ability, enabling the encapsulation failure to be quickly traced back to the wafer test parameter anomalies, and significantly improving the retrieval speed compared with the traditional data lake solution.

[0021] In this embodiment, in combination with Figure 2 , a multi-source heterogeneous data processing system based on a test chip is provided, including the following functional units: A multi-source heterogeneous data acquisition unit for real-time collecting heterogeneous data in each link of chip testing based on the accessed multiple protocols; An adaptive preprocessing unit for standardizing the format, filtering noise, and repairing missing values of the original data to construct a unified data space; A cross-domain spatio-temporal alignment unit for establishing a wafer-packaging coordinate mapping relationship and aligning the timing data of multiple test links; A multi-modal feature fusion unit for extracting three-dimensional joint features to enhance the data representation ability; A dynamic label generation unit for generating interpretable metadata labels through data-driven and physical rules; A graph structure index construction unit for constructing a parameter association graph and generating an efficient retrieval index.

[0022] The above is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or variations equivalent to the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A multi-source heterogeneous data processing method based on a test chip, characterized in that: It includes the following steps: S1: Use a distributed message queue to access multi - protocol data streams in real - time, collect multi - source heterogeneous data related to chip testing, and perform normalized pre - processing; S2: Align and map the cross - domain spatio - temporal features of the pre - processed multi - source heterogeneous data, and construct a hybrid correlation matrix based on the linear correlation degree and the non - linear correlation degree ; ; S3: Extract three - dimensional joint features based on multi - modal data and the parameter sequence after spatio - temporal alignment, and generate dynamic metadata labels; S4: Use the correlation matrix and the extracted three - dimensional joint features to generate nodes and edges, construct a parameter correlation graph structure, perform graph embedding training, and generate an index structure; S5: Locate the Top-K candidates based on the generated index structure by querying features and labels and sort the results according to the comprehensive distance and return the results 2. The multi-source heterogeneous data processing method based on a test chip according to claim 1, wherein: The above-mentioned preprocessing for normalization includes: performing normalization processing on the acquired multi-modal data related to chip testing. Among them, for the optical image data, the gray-scale statistics of the image are calculated using the dynamic binarization algorithm, the adaptive threshold is determined, and binarization is performed to extract the defect contour, that is, local correction is performed by moving the window; cubic spline interpolation is used to align the electrical performance data, and a piecewise cubic polynomial is constructed based on the original timing data of the aging test. The formula of the cubic spline interpolation function is: , where is the j-th piecewise cubic polynomial function, describing the signal in the time interval ; is the timestamp of the j-th data point; , , , are polynomial coefficients, determined by three constraints of continuity, first derivative continuity, and second derivative continuity. Among them, the continuity constraint is: the function values are equal at the connection point of adjacent segments, that is ; the first derivative continuity constraint is: ; the second derivative continuity constraint is: . Then, a uniformly sampled sequence aligned to the set frequency is output. The extraction of the key log parameters is automatically template-matched through the regular expression template library using the defined parameter capture rules. At the same time, by constructing an electrical parameter feature matrix, the Euclidean distance between each missing sample and all complete samples is calculated, and the k nearest neighbors are selected for weighted filling.

3. A multi-source heterogeneous data processing method based on a test chip according to claim 1, characterized in that: The mapping includes: mapping the wafer data and the package coordinates in the preprocessed structured data by using the dynamic process parameter compensation formula. The specific dynamic process parameter compensation formula is: , where 、 are the coordinates of the chip coordinate system after packaging, which are used to locate physical defects during failure analysis, is the rotation matrix, representing the angular offset during wafer dicing, 、 are the coordinates of the wafer coordinate system, which are the defect positions located by the optical detection device, is the scaling factor, and are the offset compensation amounts, which are determined by the reference point error of the package wire bonding process and are measured in real time by the on-line calibration system and , and a thermo-mechanical coupling model is introduced to calculate .

4. A method and system for processing multi-source heterogeneous data based on a test chip according to claim 1, characterized in that: The alignment formula for aligning cross - domain spatio - temporal features is: Among them, is the cumulative distance matrix, representing the minimum path cost of aligning and . is the th time-series data point of the functional test, is the jth time-series data point of the aging test, and the time-series data generated in the test chip is segmented by test session for dynamic time warping, that is, the dynamic time warping algorithm is applied separately to each segment, and by defining the stage weight , the calculation formula is: Among them, is the total number of test phases, is the phase weight, and the longer the time proportion, the higher the weight, is the time length of the s-th segment, is the cumulative distance matrix of the s-th segment.

5. A multi-source heterogeneous data processing method based on a test chip according to claim 1, characterized in that: The construction of the hybrid correlation matrix includes: calculating the linear correlation degree and the non-linear correlation degree , and then constructing the hybrid correlation matrix based on the linear correlation degree and the non-linear correlation degree . The specific calculation formula is as follows: Among them, is the covariance for measuring linear correlation, is the wafer test parameter, is the test parameter after packaging, and are the standard deviations for normalizing the covariance values, is the total number of test samples, is the wafer parameter non - linear kernel function, is the package parameter non - linear kernel function, is the th chip's parameter during the wafer test stage of the original measured value, is the th chip's parameter during the package test stage of the original measured value, is the mean of wafer parameters, is the mean of package parameters, is the dynamic weight that can be automatically adjusted according to the parameter distribution characteristics.

6. A multi-source heterogeneous data processing method based on a test chip according to claim 1, characterized in that: The extracted three-dimensional joint feature includes: extracting the three-dimensional joint feature of the time-domain feature, frequency-domain feature, and spatio-temporal alignment feature. The extraction formula is: , where is the three-dimensional joint feature of the th chip, with a dimension of d, , , are modal weight coefficients, dynamically calculated through the cross-domain correlation matrix, is the wavelet transform feature of the time-series data, is the histogram of oriented gradients feature of the image, is the principal component analysis dimensionality reduction feature of the electrical performance parameters.

7. A multi-source heterogeneous data processing method based on a test chip according to claim 6, characterized in that: The generation of dynamic metadata tags includes: based on the three-dimensional joint features to generate a candidate tag set by k-nearest neighbor majority voting, screen the generated candidate tag set according to the set process rule library, calculate the comprehensive scores of the qualified dynamic tags, and select and output the tag with the highest comprehensive score. Among them, the formula for generating the candidate tag set is: Among them, is the dynamic label of the th generated chip, C is a preset label set defined by the process knowledge base, is the weight of the feature point, calculated by the Gini importance of the random forest, that is, , is the constraint strength coefficient, is a physical constraint function, used to verify the process rationality of the label c, and at the same time use the cross-domain correlation matrix to guide the generation of high-dimensional joint features.

8. A method and system for processing multi-source heterogeneous data based on a test chip according to claim 7, characterized in that: The specific steps of S4 are as follows: S4 - 1: Generate nodes and edges based on the correlation matrix and three - dimensional joint features, calculate the mixed edge weights, filter the edges below the set threshold, and construct a parameter correlation graph; S4 - 2: Generate a node sequence, jointly optimize the topology loss and the label alignment loss, train the embedding model, so that the embedding vector encodes both the structure and the semantics; S4 - 3: Assign levels according to the embedding vector norm, construct an index corresponding to the multi - layer graph structure, and optimize the number of node connections in each layer.

9. A multi-source heterogeneous data processing method and system based on a test chip according to claim 8, characterized in that: The generated nodes and edges further include: The generated node features are as follows: , is the feature vector of the node , which is concatenated by the three-dimensional joint feature and the dynamic label encoding . The calculation formula of the mixed edge weight is: , where is the edge weight between the node and , is the correlation weight coefficient dynamically adjusted according to the parameter distribution, is the similarity weight, is the node feature similarity; The generated node sequence further includes: The objective function used is: , where is a graph embedding function for mapping nodes to low-dimensional vectors, is the neighbor sequence of node , generated by the biased random walk of Node2Vec, is the alignment weight, is the alignment loss between the embedding vector and the label, where , is the dynamic label encoding of node , is the Sigmoid function, is the embedding vector of label . By introducing the label alignment loss, the embedding vector encodes both structure and semantics at the same time, and the retrieval result can be reversely interpreted through the label vector ; The index corresponding to constructing the multi-layer graph structure includes: The formula for index construction is: , where is the level of node in the index, is the L2 norm of the embedding vector , is the minimum norm value, and the levels are dynamically assigned according to the embedding vector norms, so that important nodes are located at higher levels.

10. A multi-source heterogeneous data processing system based on a test chip, characterized in that: It includes the following functional units: multi - source heterogeneous data acquisition unit, adaptive pre - processing unit, cross - domain spatio - temporal alignment unit, multi - modal feature fusion unit, dynamic label generation unit, graph structure index construction unit; The multi - source heterogeneous data acquisition unit is used to collect heterogeneous data in each link of chip testing based on the accessed multi - protocols in real - time; The adaptive pre - processing unit is used to perform format standardization, noise filtering, and missing value repair on the original data, and construct a unified data space; The cross - domain spatio - temporal alignment unit is used to establish a wafer - package coordinate mapping relationship and align the time - series data of multiple testing links; The multi - modal feature fusion unit is used to extract three - dimensional joint features and enhance the data representation ability; the dynamic label generation unit is used to generate interpretable metadata labels through data - driven and physical rules; The graph structure index construction unit is used to construct a parameter correlation graph and generate an efficient retrieval index.

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