Distributed multi-screen synchronization method

Abstract

The invention discloses a distributed multi-screen synchronization method, and relates to the technical field of video synchronous display, and the method comprises the steps: forming an output node cluster by a plurality of devices, dynamically electing a main node in the output node cluster, and enabling the main node to serve as a global synchronization controller; the interrupt time sequence of the distributed nodes is synchronized, and alignment of frame taking moments of a video output module VO of the equipment is achieved; and a frame synchronization controller is selected from the distributed nodes, the frame synchronization controller collects the data of the distributed nodes and carries out frame synchronization control, so that multiple devices can synchronously display the same frame of data. Based on a dynamic main node election mechanism, decentralized distributed deployment is achieved, and distributed deployment can be achieved without intervention of an upper computer or input node equipment; by constructing a frame synchronization mechanism based on a global time reference, the tearing and dislocation phenomena of a moving picture are effectively eliminated; and realizing multi-screen synchronization in a sub-millisecond error range through an interrupt synchronization mechanism.

Description

Technical Field

[0001] The present invention relates to the technical field of distributed video synchronous display, and specifically, to a distributed multi-screen synchronization method. Background Art

[0002] In the technical architecture of existing media playback systems, the video output (VO) module usually adopts a frame buffer driving mechanism as the core process for terminal display. Specifically, the decoded video frame data is processed and written into the video memory frame buffer, and the VO module extracts frame data from the buffer through a fixed-frequency vertical synchronization signal (VSync) according to a preset frame rate for digital-to-analog conversion and signal output. However, when performing multi-screen synchronous playback, restricted by this mechanism, there are the following technical bottlenecks: First, the frame capture timing of the VO module is affected by factors such as the start time and the time-consuming of image frame rendering, and different terminal devices are not synchronized and cannot be configured; Second, the frame capture timing of the VO module is also restricted by the inherent frequency drift of the crystal oscillator clock source, resulting in deviations in the actual video memory reading moments of different terminal devices; Third, in a distributed multi-screen system, due to the lack of a global accurate frame synchronization mechanism, even if a control strategy of injecting a unified time stamp into the frame buffer is adopted, observable frame phase offsets will still occur when different terminal devices render moving pictures, typically manifested as dynamic image tearing or dislocation phenomena.

[0003] There is also a common technical limitation in the deployment of current mainstream multi-screen synchronization solutions: the degree of centralization of the system architecture is too high. Relying on the host computer (PC-side management and control software) or the input node device (video source input forwarding device) for global synchronization calculation and instruction distribution not only has the risk of single-point failure, but also is difficult to implement a distributed deployment mode of autonomous cooperation of edge nodes and lacks the ability of distributed deployment. Summary of the Invention

[0004] The purpose of the present invention is to provide a distributed multi-screen synchronization method, which is used to solve the problems in the prior art that there are dynamic image tearing or dislocation phenomena in multi-screen synchronization, and there are single-point failure risks and lack of distributed deployment capabilities when relying on the host computer or the input node device for global synchronization calculation and instruction distribution.

[0005] The present invention solves the above problems through the following technical solutions:

[0006] A distributed multi-screen synchronization method includes:

[0007] Step S1, a plurality of devices form an output node cluster, and a master node is dynamically elected in the output node cluster, and the master node serves as a global synchronization controller;

[0008] Step S2: Synchronize the interruption timings of distributed nodes to achieve alignment of the frame acquisition moments of the device video output module VO;

[0009] Step S3: Elect a frame synchronization controller in the distributed nodes. The frame synchronization controller collects data of the distributed nodes and performs frame synchronization control to achieve synchronized display of the same frame of data by multiple devices.

[0010] Through dynamic election of the master node, the present invention breakthroughly adopts a decentralized architecture, enabling distributed deployment without the intervention of a host computer (PC-side management and control software) or input node devices (video source input and forwarding devices), and overcoming the risk of single-point failures. By constructing a frame synchronization mechanism based on a global time reference, it can effectively eliminate the deviation in video memory reading between multiple terminals, achieve synchronized display of the same frame of data by multiple devices within the allowable error range, and effectively eliminate the tearing and misalignment phenomena of the moving pictures in the multi-screen synchronization solution.

[0011] Further, the method for dynamically electing the master node in step S1 is: a dynamic master node election mechanism based on node status perception, which elects the master node in the output node cluster through autonomous negotiation between devices and updates the master node in real time to cope with device addition, deletion, or offline anomalies.

[0012] Further, the method for electing the master node in the output node cluster through autonomous negotiation between devices and updating the master node in real time based on the dynamic master node election mechanism based on node status perception is specifically as follows:

[0013] Each node, based on the two-way active heartbeat detection mechanism, periodically sends a survival status detection packet through a unicast UDP message;

[0014] The node selects the node corresponding to the minimum / maximum value of the device identifier as the master node according to the sorting of the device identifiers in the real-time status table; for example, if the node performs a total order sorting based on the device identifiers in the real-time status table (preferably using the 32-bit integer value of the IPv4 address), it selects the node corresponding to the minimum value as the master control node, which undertakes the responsibility of interruption timing synchronization management;

[0015] Through a dynamic arbitration mechanism triggered by multiple events, it monitors changes in the network topology in real time. When it detects that the master node is offline or the device identifier of the newly connected node is the minimum / maximum value, it triggers a preemptive master node switching process, and the master node always remains in a globally unique state. The method for detecting that the master node is offline can be based on an adaptive heartbeat timeout determination. If the threshold = average round-trip delay RTT × 3, it is determined that the master node is offline; in the case where the master node is the node with the minimum value of the device identifier, if the IPv4 address of the newly connected node is smaller than that of the master node, or in the case where the master node is the node with the maximum value of the device identifier, if the IPv4 address of the newly connected node is larger than that of the master node, it triggers a preemptive master node switching process.

[0016] This mechanism has strong consistency guarantee. All nodes execute the election algorithm based on the same state data set, fundamentally avoiding the "split brain" (multiple master nodes) problem. At the same time, through the design of a decentralized architecture, it realizes plug-and-play of devices and dynamic adaptation of network topology.

[0017] Furthermore, in step S2, through the synergistic effect of hardware-level clock fine-tuning and software feedback control, the interruption timings of distributed nodes are synchronized.

[0018] Furthermore, the method of synchronizing the interruption timings of distributed nodes through the synergistic effect of hardware-level clock fine-tuning and software feedback control is specifically as follows:

[0019] Step A1: All nodes enable a VO interruption counter. For each VO interruption event that occurs, the counter increments by one (automatically resetting to zero after overflow), and the counter value is sent to the master node in real time.

[0020] Step A2: The time when the master node receives the interruption count is recorded as T0. The average round-trip delay RTT of each node is calculated using the sliding window algorithm, and the interruption trigger timestamp T1 = T0 - RTT / 2 is derived. When collecting its own information, the average round-trip delay RTT of the master node is 0. Therefore, the interruption trigger timestamp T1 of the master node is T1 = T0.

[0021] Step A3: The master node maintains an interruption clock deviation calibration table, which is used to record the IPv4 addresses of all nodes, the interruption count values, the interruption trigger timestamp T1, and the deviation amount ΔT of the interruption trigger timestamp T1 of the slave node relative to the interruption trigger timestamp T1 of the master node. ΔT = T1_slave - T1_master, where T1_slave is the T1 value of the slave node; T1_master is the T1 value of the master node. After the number of nodes stabilizes, the data in the interruption clock deviation calibration table is backed up, and the backup table is the initial calibration table.

[0022] Step A4: Phase-locked loop (PLL) frequency adjustment: When ΔT is greater than the set value N1, the slave node is relatively faster than the master node, and a clock down-frequency command CLK_DOWN is sent to the slave node to reduce the output frequency of its crystal oscillator by modifying the PLL division factor; when ΔT is less than the set value N2, the slave node is relatively slower than the master node, and a clock up-frequency command CLK_UP is sent to the slave node to increase the output frequency of its crystal oscillator by modifying the PLL division factor.

[0023] Step A5: When the difference between the node interruption count value and the master node interruption count value in the interrupted clock deviation calibration table is the same as the corresponding difference in the initial calibration table, it is considered that the next synchronization cycle has arrived; in each synchronization cycle, step A4 is iteratively executed; until the fluctuation range of ΔT of all nodes spirally converges until it spirally fluctuates within the set range and the trend is stable;

[0024] Step A6: Dynamic reference calibration: When nodes are added or deleted or the network topology changes, the master node generates a new interrupted clock deviation calibration table, and restarts steps A1 - A5 based on the new interrupted clock deviation calibration table.

[0025] Through the above steps, the deviation ΔT of the distributed slave node interruption timing gradually converges, achieving a synchronization effect that is indistinguishable to the human eye, and the whole process does not require the intervention of the host computer.

[0026] Further, N1 is +200 μs; N2 is -200 μs; the set range is ±1 ms.

[0027] Further, the method for the frame synchronization controller in step S3 to collect data of distributed nodes and perform frame synchronization control includes: based on the frame sequence synchronization algorithm of the presentation timestamp PTS, the frame synchronization controller performs PTS data collection, dynamically filters the intersection of PTS of each node, and issues a frame switching instruction. After each node receives the frame switching instruction, it performs video memory exchange and updates the frame to be displayed.

[0028] Further, step S3 specifically includes:

[0029] Step S31: Dynamically elect a frame synchronization controller in the output node cluster; the election mechanism of the frame synchronization controller is the same as that of the master node. Preferably, when the smallest numerical value of the device identifier is selected as the master node, the node corresponding to the largest numerical value of the device identifier is selected as the frame synchronization controller. When the largest numerical value of the device identifier is selected as the master node, the node corresponding to the smallest numerical value of the device identifier is selected as the frame synchronization controller. The purpose is to separate from the interrupt master node and achieve computational load sharing;

[0030] Step S32: Presentation timestamp PTS data collection: After each node receives the new frame data, it decodes and clips it and stores it in the double - buffer queue, and sends the PTS information of this frame to the frame synchronization controller;

[0031] Step S33, Frame Synchronization Decision: The frame synchronization controller dynamically filters the intersection of PTS information of each node, issues a frame switching instruction, and clears the expired PTS information; it cannot simply switch according to the video frame order to prevent frame misalignment caused by frame loss at a certain node; the sending time of the frame switching instruction is aligned with the midpoint of the vertical blanking interval (VBI) of the master node, VBI midpoint = trailing edge of the vertical synchronization (VSync) signal + vertical blanking interval (Blanking Interval) / 2, avoiding the critical area of frame fetching by the VO, and ensuring that each node completes the video memory frame buffer switching at the leading edge of the next VBI;

[0032] Step S34, Video Memory Exchange Mechanism: After each node receives the frame switching instruction, it performs an atomic video memory pointer switching operation in the hardware interrupt context, activates the frame to be displayed in the double buffer queue, and clears the expired frame buffer.

[0033] Furthermore, it also includes:

[0034] Step S35, Dynamic Fault Tolerance: When the number of failures in dynamically filtering the intersection of PTS of each node > the set number (such as 3 times), activate the fault tolerance mechanism, clear the double buffer queue of each node, and return to step S32.

[0035] The above steps, based on interrupt synchronization, achieve sub-millisecond (<1ms) multi-screen synchronization of 30 / 60fps video streams, and support flexible deployment of dynamic nodes, completely eliminating the dynamic blur and frame tearing phenomena of cross-screen videos.

[0036] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0037] Based on the dynamic master node election mechanism, the present invention realizes decentralized distributed deployment, and can achieve distributed deployment without the intervention of a host computer (PC-side management control software) or an input node device (video source input forwarding device); by constructing a frame synchronization mechanism based on a global time reference, it can effectively eliminate the deviation of video memory reading between multiple terminals, and effectively eliminate the tearing and misalignment phenomena of moving pictures; through the interrupt synchronization mechanism, it realizes multi-screen synchronization within a sub-millisecond (<1ms) error range. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the interrupt synchronization of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The present invention will be further described in detail below in conjunction with embodiments, but the embodiments of the present invention are not limited thereto.

[0040] Embodiment:

[0041] A distributed multi-screen synchronization method includes:

[0042] 1. A dynamic master node election mechanism based on node status awareness elects a global synchronization controller, i.e., the master node, among the output node clusters through autonomous negotiation between devices, and updates the master node in real time to cope with device addition, deletion, or offline anomalies.

[0043] 2. An interruption synchronization algorithm synchronizes the interruption timing through the algorithm to achieve sub-microsecond-level alignment at the VO frame acquisition moment.

[0044] 3. A frame sequence synchronization algorithm based on PTS (Presentation Time Stamp) ensures strict consistency of multi-terminal display frame data at the same interruption by collecting and managing frame PTS.

[0045] Among them:

[0046] Dynamic master node election mechanism:

[0047] 1) Topology awareness layer: Each node, based on the two-way active heartbeat detection mechanism, periodically sends survival status detection packets through unicast UDP packets (port numbers can be configured), supports NAT penetration and cross-router network segment communication, and finally realizes the consistent synchronization of the global node status table.

[0048] 2) Election decision layer: Adopting a deterministic election strategy, nodes perform a total order sorting based on the device identifiers (preferably 32-bit integer values of IPv4 addresses) in the real-time status table, and select the node corresponding to the smallest value as the master control node, which undertakes the responsibility of interruption timing synchronization management.

[0049] 3) Fault recovery layer: Through a dynamic arbitration mechanism triggered by multiple events, it monitors network topology changes in real time. When it detects that the master node is offline (judged based on adaptive heartbeat timeout, threshold = average round-trip delay RTT × 3 or a new access node meets the conditions (such as a device with a smaller IPv4 address goes online)), it triggers a preemptive master node switching process, and the master node always remains in a globally unique state.

[0050] The dynamic master node election mechanism has strong consistency guarantee. All nodes execute the election algorithm based on the same state data set, fundamentally avoiding the "split brain" (multiple master nodes) problem, and at the same time realizing plug-and-play of devices and dynamic adaptation of network topology through a decentralized architecture design.

[0051] Interruption synchronization algorithm:

[0052] 1) Interruption counter: All nodes enable a VO interruption counter. For each VO interruption event, the counter uses an int circular count to increment by one (automatically resetting to zero after overflow), and sends the counter value to the master node in real time.

[0053] 2) Counter Sampling: The time when the master node receives the interrupt count is recorded as T0. The sliding window algorithm is used to calculate the average round-trip time (RTT) of each node, and the interrupt trigger timestamp T1 of each node is derived as T1 = T0 - RTT / 2. Since the RTT of the master node is 0, the T1 of the master node is T0.

[0054] 3) Construction of Interrupt Clock Deviation Calibration Table: The master node maintains an interrupt clock deviation calibration table, which records the IPv4 address of each node, the interrupt count value, the interrupt trigger timestamp T1, and the deviation ΔT of the interrupt trigger timestamp T1 of the slave node relative to the interrupt trigger timestamp T1 of the master node. ΔT = T1_slave - T1_master, where T1_slave is the T1 value of the slave node and T1_master is the T1 value of the master node. After the number of nodes stabilizes, the table data is backed up, and the backup table is the initial calibration table. The interrupt clock deviation calibration table is continuously updated dynamically, while the initial calibration table remains unchanged after it is determined.

[0055] 4) Phase-Locked Loop (PLL) Frequency Adjustment:

[0056] When the ΔT of the slave node > +200 μs, the slave node is faster than the master node, and a clock down-frequency command (CLK_DOWN) is sent to the slave node to reduce the output frequency of its crystal oscillator by modifying the PLL frequency division coefficient.

[0057] When the ΔT of the slave node < -200 μs, the slave node is slower than the master node, and a clock up-frequency command (CLK_UP) is sent to the slave node to increase the output frequency of its crystal oscillator by modifying the PLL frequency division coefficient.

[0058] 5) Steady-State Convergence: When the difference between the interrupt count value of the slave node and the interrupt count value of the master node in the interrupt clock deviation calibration table is the same as the corresponding difference in the initial calibration table (all nodes have updated the interrupt count, refer to Table 1), it is considered to reach the next synchronization cycle. In each synchronization cycle, step 4) is iteratively executed. Finally, the fluctuation range of ΔT of all slave nodes converges spirally until it fluctuates within ±1 ms and the trend is stable.

[0059] Table 1: Calibration Tables for Each Synchronization Cycle and the Initial Calibration Table

[0060]

[0061] 6) Dynamic Reference Calibration: When nodes are added or deleted or the network topology changes, the master node generates a new interrupt clock deviation calibration table and restarts the interrupt synchronization process based on the new interrupt clock deviation calibration table to ensure that the synchronization mechanism adapts to the dynamic environment.

[0062] Such as Figure 1As shown, through the cooperation of hardware-level clock fine-tuning and software feedback control, the deviation ΔT of the interruption timing of distributed slave nodes in the interruption synchronization algorithm continuously converges and approaches 0. That is, the interruption trigger timestamp T1 of the slave node and the interruption trigger timestamp T1 of the master node continuously approach each other, and finally achieve a synchronization effect that is indistinguishable to the human eye, and the whole process does not require the intervention of the host computer.

[0063] Frame sequence synchronization algorithm:

[0064] 1) Frame synchronization controller election: It is generally the same as the dynamic master node election mechanism, but in the election decision, the node corresponding to the largest value is selected as the master control node to assume the responsibility of the frame synchronization controller; the purpose of this difference is to separate from the interruption master node and achieve the diversion of computing load;

[0065] 2) PTS (Presentation Time Stamp) data acquisition: When each node receives new frame data, after decoding and cropping, it is stored in the double buffer queue, and the PTS information (64 bytes) of this frame is sent to the frame synchronization controller;

[0066] 3) Frame synchronization decision: The frame synchronization controller dynamically filters the intersection of the PTS of each node, issues a frame switching instruction, and clears the expired PTS information. It cannot be simply switched according to the video frame order to prevent frame misalignment caused by frame loss of a certain node;

[0067] 4) Precise trigger of the switching instruction: The instruction sending moment is strictly aligned with the midpoint of the master node VBI (that is, the trailing edge of the VSync signal + Blanking Interval / 2), avoiding the critical area of frame acquisition by VO, and ensuring that each node completes the video memory frame buffer switching at the leading edge of the next VBI;

[0068] 5) Video memory exchange mechanism: After each node receives the instruction, it performs an atomic video memory pointer switching operation in the hardware interruption context, activates the frame to be displayed in the double buffer, and clears the expired frame buffer;

[0069] 6) Dynamic fault tolerance: When the number of failures of dynamically filtering the intersection of the PTS of each node > 3, the fault tolerance mechanism is activated. Clear the double buffer queue of each node and re-perform PTS data acquisition.

[0070] Based on interruption synchronization, this algorithm realizes sub-millisecond (<1ms) multi-screen synchronization of 30 / 60fps video streams, and supports the flexible deployment of dynamic nodes, completely eliminating the dynamic blur and frame tearing phenomena of cross-screen videos.

[0071] Although the present invention has been described herein with reference to illustrative embodiments thereof, the above embodiments are only preferred embodiments of the present invention, and the embodiments of the present invention are not limited by the above embodiments. It should be understood that those skilled in the art can design many other modifications and embodiments, which will fall within the scope of the principles and spirit disclosed in this application.

Claims

1. A distributed multi-screen synchronization method, characterized in that Including: Step S1: Multiple devices form an output node cluster, and a master node is dynamically elected in the output node cluster. The master node serves as a global synchronization controller; Step S2: Synchronize the interruption timings of distributed nodes to achieve alignment of the frame capture moments of the device video output VO modules; Step S3: Elect a frame synchronization controller in the distributed nodes. The frame synchronization controller collects data from the distributed nodes and performs frame synchronization control to achieve synchronized display of the same frame data by multiple devices.

2. The distributed multi-screen synchronization method according to claim 1, characterized in that The method for dynamically electing the master node in step S1 is: a dynamic master node election mechanism based on node status awareness, which elects the master node in the output node cluster through autonomous negotiation between devices and updates the master node in real time.

3. A distributed multi-screen synchronization method according to claim 2, characterized in that The method for electing the master node in the output node cluster through autonomous negotiation between devices and updating the master node in real time based on the dynamic master node election mechanism based on node status awareness is specifically as follows: Each node, based on the two-way active heartbeat detection mechanism, periodically sends a survival status detection packet through a unicast UDP message; The node selects the node corresponding to the minimum / maximum value of the device identifier as the master node according to the sorting of device identifiers in the real-time status table; Through a dynamic arbitration mechanism triggered by multiple events, the network topology change is monitored in real time. When it is detected that the master node is offline or the device identifier of the newly connected node is the minimum / maximum value, a preemptive master node switching process is triggered.

4. A distributed multi-screen synchronization method according to claim 1, characterized in that, In step S2, the interruption timings of the distributed nodes are synchronized through the synergistic effect of hardware-level clock fine-tuning and software feedback control.

5. A distributed multi-screen synchronization method according to claim 4, characterized in that, The method for synchronizing the interruption timings of the distributed nodes through the synergistic effect of hardware-level clock fine-tuning and software feedback control is specifically as follows: Step A1: All nodes enable a VO interruption counter. For each occurrence of a VO interruption event, the counter increments its count and sends the counter value to the master node in real time; Step A2: The time when the master node receives the interruption count is recorded as T0. The average round-trip delay RTT of each node is calculated using a sliding window algorithm, and the interruption trigger timestamp T1 = T0 - RTT / 2 is deduced; when collecting its own information, the average round-trip delay RTT of the master node is 0, so the interruption trigger timestamp T1 of the master node = T0; Step A3: The master node maintains an interruption clock deviation calibration table, which is used to record the IPv4 addresses, interruption count values, interruption trigger timestamps T1 of all nodes, and the deviation amount ΔT of the interruption trigger timestamp T1 of the slave node relative to the interruption trigger timestamp T1 of the master node; after the number of nodes stabilizes, the data in the interruption clock deviation calibration table is backed up, and the backup table is the initial calibration table; Phase-locked loop (PLL) frequency adjustment: When the ΔT of the slave node is greater than the set value N1, the slave node is relatively faster than the master node, and a clock down-frequency command CLK_DOWN is sent to the slave node to reduce its crystal oscillator output frequency by modifying the PLL frequency division coefficient; when the ΔT of the slave node is less than the set value N2, the slave node is relatively slower than the master node, and a clock up-frequency command CLK_UP is sent to the slave node to increase its crystal oscillator output frequency by modifying the PLL frequency division coefficient; Step A5: When the difference between the node interruption count value and the master node interruption count value in the interrupted clock deviation calibration table is consistent with the corresponding difference in the initial calibration table, it is considered that the next synchronization cycle has arrived; in each synchronization cycle, Step A4 is iteratively executed until the fluctuation range of ΔT of all nodes spirally converges until it spirally fluctuates within the set range and the trend is stable. Step A6: Dynamic reference calibration: When nodes are added or deleted or the network topology changes, the master node generates a new interrupted clock deviation calibration table and restarts Steps A1 - A5 based on the new interrupted clock deviation calibration table.

6. A distributed multi-screen synchronization method according to claim 5, characterized in that, N1 is +200 μs; N2 is -200 μs; the set range is ±1 ms.

7. A distributed multi-screen synchronization method according to claim 1, characterized in that, In Step S3, the method for the frame synchronization controller to collect data from distributed nodes and perform frame synchronization control includes: Based on the frame sequence synchronization algorithm of the presentation timestamp PTS, the frame synchronization controller performs PTS data collection, dynamically filters the intersection of PTS of each node, and issues a frame switching instruction. After each node receives the frame switching instruction, it performs video memory exchange and updates the frame to be displayed.

8. A distributed multi-screen synchronization method according to claim 7, characterized in that, Step S3 specifically includes: Step S31: Dynamically elect a frame synchronization controller in the output node cluster. Step S32: Presentation timestamp PTS data collection: When each node receives new frame data, after decoding and cropping, it stores the data in a double - buffer queue and sends the PTS information of this frame to the frame synchronization controller. Step S33: Frame synchronization decision: The frame synchronization controller dynamically filters the intersection of PTS information of each node, issues a frame switching instruction, and clears the expired PTS information; the sending time of the frame switching instruction is aligned with the mid - point of the vertical blanking interval (VBI) of the master node. VBI mid - point = trailing edge of the vertical synchronization signal + vertical blanking interval / 2, avoiding the critical area of frame fetching by VO, and ensuring that each node completes the video memory frame buffer switching at the leading edge of the next VBI. Step S34: Video memory exchange mechanism: After each node receives the frame switching instruction, it performs an atomic video memory pointer switching operation in the hardware interrupt context, activates the frame to be displayed in the double - buffer queue, and clears the expired frame buffer.

9. A distributed multi-screen synchronization method according to claim 8, wherein, It also includes: Step S35: Dynamic fault tolerance: When the number of failures in dynamically filtering the intersection of PTS of each node > the set number of times, activate the fault tolerance mechanism, clear the double - buffer queue of each node, and return to Step S32.

10. A distributed multi-screen synchronization method according to claim 8, characterized in that, The frame synchronization controller is not the same as the master node.

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