Cache replacement method, system and device based on binary tree status bit management and medium

Abstract

The invention relates to the technical field of computers, and discloses a cache replacement method, system and device based on binary tree status bit management and a medium. The method comprises the following steps: firstly mapping N cache lines of a cache unit into N leaf nodes of a binary tree, then setting status bits of internal nodes and leaf nodes of the binary tree, preferentially replacing the empty cache lines when accessing the cache, then judging whether the cache is hit or not, and if the cache is hit, judging whether the cache is hit or not. Determining state transition of the internal node according to whether the path node corresponding to the hit cache line is the same as the internal node, and updating the state of the leaf node; when the cache is not hit, the historical queue is checked firstly, then the sub-tree is selected according to the node state value to search and replace the cache line, and whether replacement is carried out or not is determined according to the leaf node and the state bit of the new cache. According to the method, relatively low hardware overhead can be kept, frequency locality and time locality can be better balanced, a higher cache hit rate is provided, and relatively good performance is achieved when data of different access modes are processed.

Description

Technical Field

[0001] This application relates to the field of computer technology, for example, to a cache replacement method, system, device and medium based on binary tree status bit management. Background Art

[0002] In a parallel computing architecture, the performance of the cache is crucial to the overall computing efficiency. Due to the characteristics of high parallelism and large-scale data processing in parallel computing, how to improve the cache hit rate and reduce the access latency under limited hardware resources has always been the focus of research. Especially with the wide application of parallel computing in fields such as deep learning, image processing, and scientific computing, the performance requirements for the cache system are getting higher and higher. Traditional single strategies, such as the LRU (Least Recently Used) and LFU (Least Frequency Used) cache replacement strategies, have clear advantages and disadvantages in parallel computing: for example, LRU performs well in scenarios with good temporal locality, but performs poorly in the case of scan traversal, where new large amounts of data will flush the cache. LFU needs to maintain a frequency counter, which occupies a large amount of space, has high complexity and large area overhead, and performs poorly in handling burst traffic. Pseudo-LRU (approximate LRU) is an algorithm for cache replacement, aiming to approximately implement the LRU strategy and reduce the implementation complexity through a simpler data structure. However, it cannot handle low-frequency repeated accesses, and for some sporadic and periodic batch operations, it will cause a sharp drop in the LRU hit rate, and in this case, this strategy may not be the optimal one. Compared with single strategies, LRU-K (Least Recently Used with K frequency) combines the ideas of LRU and LFU and eliminates the data item that has not been accessed for the longest time in the last K accesses. It can better balance temporal locality and frequency locality and improve the cache hit rate. However, its implementation complexity is relatively high: it is necessary to maintain the access history of each data item, and the implementation is relatively complex. And in a large-scale cache environment of parallel computing, the required hardware overhead (such as the storage and logic circuits required to maintain and update the linked list) becomes very large, resulting in an increase in chip area and power consumption.

[0003] Patent 202311634767.5 discloses a cache line replacement method and device, including: receiving a replacement request, determining the root node in the binary tree structure corresponding to the data block partition as the first target node and obtaining its node information; if the target node is a non-leaf node, determining the child node of the target node in the replacement direction indicated by the processing status of the current target node as the next target node and updating the target counter of the target node until the determined target node is a leaf node, then determining the data block to be searched based on the leaf node; using the PLRU algorithm to find the replaceable cache line in the data block to be searched; generating a search result according to the data block ID of the data block to be searched and the cache line ID of the replaceable cache line. While increasing the cache storage capacity, it reduces the time required for the hit test, and at the same time realizes balanced cache line replacement.

[0004] Patent 202210214699.6 discloses a method and device for selecting a replaceable cache line. By adding a blocking status binary tree to replace the replacement status binary tree and selecting the cache line to be replaced according to the blocking status binary tree and the usage status binary tree, at a small cost, in the blocking cache, it can more accurately find the oldest cache line among the replaceable cache lines as the cache line to be replaced, which is more in line with the temporal and spatial continuity of memory access and improves the hit rate of the cache system.

[0005] Through analysis, it can be seen that the internal nodes of the above patents have nothing to do with the access times and frequencies of cache lines, that is, they do not represent cache lines that have not been accessed for a long time, and each child node does not represent the access frequency of the cache line, so it is impossible to better balance frequency locality and temporal locality, and there are defects in processing data with different access patterns.

[0006] It should be noted that the information disclosed in the above background art section is only used to strengthen the understanding of the background of the present application, so it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0007] To have a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. The summary is not a general review, nor is it intended to identify key / important constituent elements or delineate the protection scope of these embodiments, but rather serves as a preface to the subsequent detailed description.

[0008] Embodiments of the present disclosure provide a cache replacement method, system, device and medium based on binary tree status bit management, aiming to reduce the hardware resource overhead by optimizing the replacement algorithm while improving the cache performance.

[0009] In some embodiments, the cache replacement method based on binary tree status bit management includes:

[0010] Step A: Map the N cache lines of the cache unit to the N leaf nodes of a binary tree, where N is a positive integer. The internal nodes form the branches of the binary tree. Each internal node is set with a status bit to indicate the subtree that may contain the target cache line, and each leaf node is set with a status bit to indicate whether the leaf node belongs to the high-frequency access category;

[0011] Step B: In the initial state, set the status bits of all nodes in the binary tree to 0 and clear the cache lines. When the processor accesses the cache unit, access the subtree according to the status of the binary tree nodes until reaching the leaf node, fill the empty cache line, and then flip the status values of the nodes on the path;

[0012] Step C: Cache replacement. When the cache is hit, if the status of the access path nodes of the hit cache line is the same as the status of the internal node, the status of the internal node is flipped; if different, it is not flipped. The status of the nodes outside the access path of the hit cache line remains unchanged. If the status bit of the leaf node at this time indicates that it does not belong to the high-frequency access, the status bit is flipped; if the status bit of the leaf node indicates that it belongs to the high-frequency access, the status bit remains unchanged; Evict the cache line from the corresponding history queue;

[0013] When the cache is not hit, replace the cache line. First, check whether the cache line exists in the history queue. If the cache line exists in the history queue, set its status bit to 1 and evict the cache line; if the cache line does not exist in the history queue, add the cache line to the history queue, set the status bit to 0, and then access the subtree according to the status of the binary tree nodes until reaching the leaf node. This leaf node is the selected leaf node. Compare the status bit of the selected leaf node with the status bit of the miss cache line. If the status bit of the selected leaf node is greater than the status bit of the miss cache line, do not replace the cache line; otherwise, perform cache line replacement.

[0014] As a further improvement, in Step A, the status bit of each internal node has two values: 0 and 1. When the status bit is 0, it means that the left subtree may contain the target cache line; when the status bit is 1, it means that the right subtree may contain the target cache line; for the leaf node, its status bit also has two values: 0 and 1. When the status bit is 0, it means that the leaf node does not belong to the high-frequency access; when the status bit is 1, it means that the leaf node belongs to the high-frequency access.

[0015] As a further improvement, in Step B or C, the process of accessing the subtree according to the status of the binary tree nodes is as follows: Start searching from the root node of the binary tree. When encountering a status bit of 0, go left; when encountering a status bit of 1, go right, and recursively traverse the subtree until reaching the leaf node.

[0016] As a further improvement, in step C, comparing the status bit of the selected leaf node with the status bit of the cache line that misses includes: if the status bit of the selected leaf node is 0 and the status bit of the cache line that misses is 0, then replace the selected leaf node with the cache line that misses; if the status bit of the selected leaf node is 0 and the status bit of the cache line that misses is 1, then replace the selected leaf node with the cache line that misses; if the status bit of the selected leaf node is 1 and the status bit of the cache line that misses is 0, then no replacement is performed; if the status bit of the selected leaf node is 1 and the status bit of the cache line that misses is 1, then replace the selected leaf node with the cache line that misses.

[0017] As a further improvement, the destination cache line is the least recently used cache line.

[0018] As a further improvement, this method is used for parallel computing cache replacement.

[0019] In some embodiments, the cache replacement system based on binary tree status bit management includes:

[0020] An N-way set associative cache unit;

[0021] A binary tree, there is a mapping relationship between the cache unit and the binary tree, N cache lines of the cache unit are mapped to N leaf nodes of the binary tree, and the internal nodes form the branches of the binary tree;

[0022] Status bits, each internal node stores 1 status bit for indicating the subtree that may contain the destination cache, and each leaf node stores 1 status bit for indicating whether the leaf node belongs to the high-frequency access category;

[0023] In the initial state, set the status bits of all nodes of the binary tree to 0, clear the cache lines. When the processor accesses the cache, access the subtree according to the status of the binary tree nodes until reaching the leaf node, fill in the empty cache line, and after filling in the cache line, flip the status values of the nodes on the path;

[0024] When a cache hit occurs, if the status of the access path nodes required by the hit cache is the same as the status of the internal nodes, then the status of the internal nodes flips, if not, then it does not flip, and the other internal nodes remain unchanged. If at this time the status bit of the leaf node indicates that it does not belong to the high-frequency access, then the status bit flips, if the status bit of the leaf node indicates that it belongs to the high-frequency access, then the status bit remains unchanged; evict the cache from the corresponding history queue.

[0025] When a cache miss occurs, a cache line needs to be replaced. First, check whether the cache exists in the history queue. If the cache exists in the history queue, set its status bit to 1 and evict the cache; if the cache does not exist in the history queue, add the cache to the history queue, set the status bit to 0, and then access the subtree according to the binary tree node status until reaching the leaf node. This leaf node is the selected leaf node. Compare the status bit of the selected leaf node with the status bit of the cache line with a miss. If the status bit of the selected leaf node is greater than the status bit of the cache with a miss, do not replace the cache; otherwise, perform cache replacement.

[0026] As a further improvement, the present system is used for parallel computing cache replacement.

[0027] In some embodiments, the device includes a processor and a memory storing program instructions. The processor is configured to execute the aforementioned cache replacement method based on binary tree status bit management when running the program instructions.

[0028] In some embodiments, the storage medium stores program instructions. When the program instructions are running, they execute the aforementioned cache replacement method based on binary tree status bit management.

[0029] The cache replacement method, system, device, and medium based on binary tree status bit management provided by the embodiments of the present disclosure can achieve the following technical effects: The present invention uses a binary tree and other simple data structures to track the usage of cache lines, simplifies the design through the tree structure, identifies cache lines that have not been accessed for a long time according to internal nodes, and can identify frequently accessed cache lines through leaf node labels, so as to make a replacement decision comprehensively. When a cache hit occurs, determine the internal node status conversion according to whether the path nodes corresponding to the hit cache line are the same as the internal nodes, and update the leaf node status at the same time; when a cache miss occurs, first check the history queue, then select a subtree to find a replacement cache line according to the node status value, and determine whether to replace according to the status bits of the leaf node and the new cache. While maintaining a low hardware overhead, the present invention can better balance frequency locality and temporal locality, provide a higher cache hit rate, and have good performance when processing data with different access patterns.

[0030] The above general description and the following description are only exemplary and explanatory, and are not used to limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations and the drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

[0032] Figure 1It is a flowchart of cache replacement;

[0033] Figure 2 It is a schematic diagram of the initial state of the binary tree in Embodiment 1;

[0034] Figure 3 It is a schematic illustration of the state change of the binary tree in Embodiment 1 Figure 1 ;

[0035] Figure 4 It is a schematic illustration of the state change of the binary tree in Embodiment 1 Figure 2 ;

[0036] Figure 5 It is a schematic illustration of the state change of the binary tree in Embodiment 1 Figure 3 ;

[0037] Figure 6 It is a schematic illustration of the state change of the binary tree in Embodiment 1 Figure 4 ;

[0038] Figure 7 It is a schematic diagram of the device described in Embodiment 3. Detailed implementation manners

[0039] In order to more comprehensively understand the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, numerous details are provided to give a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other instances, well-known structures and devices may be shown in a simplified manner to simplify the drawings.

[0040] In the embodiments of the present disclosure, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0041] Unless otherwise specified, the term "plurality" means two or more.

[0042] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0043] The term "and / or" is a description of the associated relationship of an object, indicating that there can be three relationships. For example, A and / or B means: A or B, or, the three relationships of A and B.

[0044] The term "correspondence" can refer to an association relationship or a binding relationship. A corresponding to B means that there is an association relationship or a binding relationship between A and B.

[0045] Embodiment 1

[0046] This embodiment discloses a cache replacement method based on binary tree status bit management, as Figure 1 shown, including:

[0047] Step A: Map the N-way associative cache to N leaf nodes of a binary tree. N is a positive integer. The internal nodes form the branches of the binary tree. Each internal node stores one status bit, which is used to indicate the subtree that may contain the target cache. Each leaf node stores one status bit, which is used to indicate whether the leaf node belongs to the high-frequency access category.

[0048] In this embodiment, a 4-way associative cache unit is set up, as Figure 2 shown. The root node, the left subtree of the second layer, and the right subtree of the second layer of the binary tree are internal nodes. Denote the (first layer) root node, the (second layer) left subtree, and the (second layer) right subtree status as state = {state_root, state_left, state_right}. This status is used to indicate the subtree that may contain the target cache. The third row of the binary tree is the leaf node, which is used to map N target cache lines. Denote the target cache lines from left to right as line0, line1, line2, line3. Each cache line is also set with one status bit, which is used to indicate whether the leaf node belongs to the high-frequency access category.

[0049] In this embodiment, the status bit of each internal node has two values: 0 and 1. When the status bit is 0, it means that the left subtree may contain the target cache. When the status bit is 1, it means that the right subtree may contain the target cache. For the leaf node, its status bit also has two values: 0 and 1. When the status bit is 0, it means that the leaf node does not belong to the high-frequency access. When the status bit is 1, it means that the leaf node belongs to the high-frequency access. For example, use (A, 0) to indicate that the leaf node A does not belong to the high-frequency access, and (A, 1) to indicate that the leaf node A belongs to the high-frequency access.

[0050] Step B: In the initial state, set the status bits of all nodes of the binary tree to 0, clear the cache lines. When the processor accesses the cache, access the subtree according to the status of the binary tree nodes until reaching the leaf node, fill in the empty cache line, and after filling in the cache line, flip the status values of the nodes on the path.

[0051] Step C, cache replacement: When a cache hit occurs, if the access path node state required by the hit cache is the same as the internal node state, the internal node state is flipped; if not, it is not flipped, and other internal nodes remain unchanged. If the status bit of the leaf node at this time indicates that it does not belong to high-frequency access, the status bit is flipped; if the status bit of the leaf node indicates that it belongs to high-frequency access, the status bit remains unchanged; Evict the cache from the corresponding history queue.

[0052] When a cache miss occurs, a cache line needs to be replaced. First, check whether the cache exists in the history queue. If the cache exists in the history queue, set its status bit to 1 and evict the cache; if the cache does not exist in the history queue, add the cache to the history queue, set the status bit to 0, and then access the subtree according to the binary tree node state until reaching the leaf node. This leaf node is the selected leaf node for comparison. If the status bit of the selected leaf node is greater than the status bit of the cache miss, the cache is not replaced; otherwise, cache replacement is performed.

[0053] In Step B or Step C, the process of accessing the subtree according to the binary tree node state is as follows: Start searching from the root node of the binary tree. When encountering a status bit of 0, go left; when encountering a status bit of 1, go right, and recursively traverse the subtree until reaching the leaf node.

[0054] In Step C, comparing the status bit of the selected leaf node with the status bit of the cache miss includes four cases: If the status bit of the selected leaf node is 0 and the status bit of the cache miss is 0, replace the selected leaf node with the cache miss; if the status bit of the selected leaf node is 0 and the status bit of the cache miss is 1, replace the selected leaf node with the cache miss; if the status bit of the selected leaf node is 1 and the status bit of the cache miss is 0, no replacement is performed; if the status bit of the selected leaf node is 1 and the status bit of the cache miss is 1, replace the selected leaf node with the cache miss.

[0055] In this embodiment, the target cache line is the least recently used cache line. Long-unaccessed cache lines can be identified through internal nodes.

[0056] This method is used for parallel computing cache replacement, which can improve the cache performance of the parallel computing system and provide a basis for the application of parallel computing in fields such as deep learning, image processing, and scientific computing.

[0057] In this embodiment, if the access order of the cache unit is ABCDCE in sequence, the process of cache replacement is as follows:

[0058] 1. Initial state: Set the status bits of all nodes to 0, state = 3'b000, clear the cache line. At this time, the binary tree state is as attachedFigure 2 as shown

[0059] 2. Access cache A: The arrows in the state diagram follow the rule that 0 points to the left and 1 points to the right; according to the state value state = 3'b000, the root node points to the left subtree, and the left subtree points to line0, so A is filled in the position of line0. Since the cache line is not full and cache A is accessed for the first time, (A,0) indicates that cache line A does not belong to high-frequency access. Flip the state of the path node, that is, state = 3'b110. At this time, the state of the binary tree is as shown in the appendix Figure 3 as shown

[0060] 3. Access caches B, C, and D: By analogy with step 2, cache B is filled in line2, cache C is filled in line1, and cache D is filled in lin3. At this time, the cache lines are full, and at this time state = 3'b000. The state of the binary tree is as shown in the appendix Figure 4 as shown

[0061] 4. Access cache C: Cache hit. The state of the path corresponding to accessing cache C is state = 3'b01x. Compare it with the states of the internal corresponding path, leaf node, and root node state = 3'b000. If the cache line corresponding to the accessed path node is the same as the internal node, the state of the internal node needs to be converted; if not, it does not need to be changed, and other nodes remain unchanged. Therefore, state changes to 3'b100. At this time, the state value of leaf node C is 0, so the state is converted to 1. At this time, the state of the binary tree is as shown in the appendix Figure 5 as shown

[0062] 5. Access cache E: Cache miss, need to replace the cache line. First, check that the history queue does not have this cache, then add it to the history queue, and the status bit is 0. Then, according to the state value of the node state = 3'b100, select the (B,0) of the cache line line0 to be pre-replaced, and compare the node states of the two caches. Since the status bit of the selected leaf node B is 0 and the status bit of cache E is 0, it is replaced with the new cache E. At this time, the state of the binary tree is as shown in the appendix Figure 6 as shown

[0063] Embodiment 2

[0064] This embodiment discloses a cache system based on binary tree status bit management, including

[0065] an N-way associative cache unit; a binary tree, there is a mapping relationship between the cache unit and the binary tree, and the N cache lines of the cache unit are mapped to the N leaf nodes of the binary tree, and the internal nodes form the branches of the binary tree

[0066] Status bits. Each internal node stores one status bit, which is used to indicate the subtree that may contain the target cache. Each leaf node stores one status bit, which is used to indicate whether the leaf node belongs to the high-frequency access category. The status bit of each internal node has two values: 0 and 1. When the status bit is 0, it means that the left subtree may contain the target cache line; when the status bit is 1, it means that the right subtree may contain the target cache line. For leaf nodes, its status bit also has two values: 0 and 1. When the status bit is 0, it means that the leaf node does not belong to high-frequency access; when the status bit is 1, it means that the leaf node belongs to high-frequency access.

[0067] In the initial state, set the status bits of all nodes in the binary tree to 0 and clear the cache lines. When the processor accesses the cache, it accesses the subtree according to the status of the binary tree nodes until it reaches the leaf node, fills the empty cache line, and after filling the cache line, flips the status values of the nodes on the path.

[0068] When a cache hit occurs, if the status of the access path nodes required by the hit cache is the same as the status of the internal node, the status of the internal node is flipped; if not, it is not flipped, and the status of other internal nodes remains unchanged. If the status bit of the leaf node at this time indicates that it does not belong to high-frequency access, the status bit is flipped; if the status bit of the leaf node indicates that it belongs to high-frequency access, the status bit remains unchanged; evict the cache from the corresponding history queue.

[0069] When a cache miss occurs, a cache line needs to be replaced. First, check whether the cache exists in the history queue. If the cache exists in the history queue, set its status bit to 1 and evict the cache; if the cache does not exist in the history queue, add the cache to the history queue, set the status bit to 0, and then access the subtree according to the status of the binary tree nodes until it reaches the leaf node. This leaf node is the selected leaf node for comparison. If the status bit of the selected leaf node is greater than the status bit of the missed cache, the cache is not replaced; otherwise, the cache is replaced.

[0070] In the above process, the process of accessing the subtree according to the status of the binary tree nodes is as follows: start searching from the root node of the binary tree, go left when encountering a status bit of 0, go right when encountering a status bit of 1, and recursively traverse the subtree until reaching the leaf node.

[0071] Comparing the status bit of the selected leaf node with the status bit of the cache line miss includes: If the status bit of the selected leaf node is 0 and the status bit of the cache line miss is 0, then replace the selected leaf node with the cache line miss; If the status bit of the selected leaf node is 0 and the status bit of the cache line miss is 1, then replace the selected leaf node with the cache line miss; If the status bit of the selected leaf node is 1 and the status bit of the cache line miss is 0, then no replacement is made; If the status bit of the selected leaf node is 1 and the status bit of the cache line miss is 1, then replace the selected leaf node with the cache line miss.

[0072] This system is used for parallel computing cache replacement, which can improve the cache performance of the parallel computing system and provide a basis for the application of parallel computing in fields such as deep learning, image processing, and scientific computing.

[0073] Embodiment 3

[0074] Combined Figure 7 As shown, an embodiment of the present disclosure provides a cache replacement device 300 based on binary tree status bit management, including a processor 304 and a memory 301. Optionally, the device may further include a communication interface 302 and a bus 303. Among them, the processor 304, the communication interface 302, and the memory 301 can complete mutual communication through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can call the logical instructions in the memory 301 to execute the cache replacement method based on binary tree status bit management described in Embodiment 1.

[0075] In addition, when the logical instructions in the above-mentioned memory 301 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0076] The memory 301, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 304 executes functional applications and data processing by running the program instructions / modules stored in the memory 301, that is, implements the cache replacement method based on binary tree status bit management described in Embodiment 1.

[0077] The memory 301 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 301 may include high-speed random access memory and may also include non-volatile memory.

[0078] Example 4

[0079] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, which are configured to execute the cache replacement method based on binary tree status bit management described in Embodiment 1.

[0080] The above computer-readable storage medium may be a transient computer-readable storage medium or a non-transient computer-readable storage medium.

[0081] The technical solution of the embodiment of the present disclosure may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The foregoing storage medium may be a non-transient storage medium, including: various media capable of storing program codes such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc, or may also be a transient storage medium.

[0082] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure, enabling those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. The embodiments only represent possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only for describing the embodiments and do not limit the scope of protection. As used in the description herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. Similarly, as used in this application, the term "and / or" refers to any and all possible combinations including one or more of the associated listed items. Additionally, when used in this application, the term "comprise" and its variants "comprises" and / or "comprising" etc. mean the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, or apparatus comprising the element. In this document, each embodiment may focus on the differences from other embodiments, and the same or similar parts among the embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method parts disclosed in the embodiments, the relevant parts may refer to the description of the method parts.

[0083] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner may depend on the specific application and design constraints of the technical solution. The technical personnel can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the embodiments of the present disclosure. The technical personnel can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated herein.

[0084] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Additionally, the couplings, direct couplings, or communication connections shown or discussed among each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms. The units described as separate components can be either physically separated or not. The components shown as units can be either physical units or not, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. Additionally, in the embodiments of the present disclosure, the various functional units can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

Claims

1. A cache replacement method based on binary tree status bit management, characterized in that Including: Step A: Map N cache lines of the cache unit to N leaf nodes of a binary tree, where N is a positive integer. The internal nodes form the branches of the binary tree. Each internal node is set with a status bit to indicate the subtree that may contain the target cache line, and each leaf node is set with a status bit to indicate whether the leaf node belongs to the high-frequency access category; Step B: In the initial state, set the status bits of all nodes of the binary tree to 0 and clear the cache lines. When the processor accesses the cache unit, access the subtree according to the status of the binary tree nodes until reaching the leaf node, fill the empty cache line, and then flip the status values of the nodes on the path; Step C: Cache replacement. When a cache hit occurs, if the status of the access path nodes of the hit cache line is the same as that of the internal node, the status of the internal node is flipped; if different, it is not flipped. The status of the nodes outside the access path of the hit cache line remains unchanged. If the status bit of the leaf node at this time indicates that it does not belong to the high-frequency access, the status bit is flipped; if the status bit of the leaf node indicates that it belongs to the high-frequency access, the status bit remains unchanged; evict the cache line from the corresponding history queue; When a cache miss occurs, replace the cache line. First, check whether the cache line exists in the history queue. If the cache line exists in the history queue, set its status bit to 1 and evict the cache line; if the cache line does not exist in the history queue, add the cache line to the history queue, set the status bit to 0, and then access the subtree according to the status of the binary tree nodes until reaching the leaf node. This leaf node is the selected leaf node. Compare the status bit of the selected leaf node with the status bit of the missed cache line. If the status bit of the selected leaf node is greater than the status bit of the missed cache line, do not replace the cache line; otherwise, perform cache line replacement.

2. The cache replacement method based on binary tree status bit management according to claim 1, wherein In Step A, the status bit of each internal node has two values: 0 and 1. When the status bit is 0, it means that the left subtree may contain the target cache line; when the status bit is 1, it means that the right subtree may contain the target cache line. For the leaf node, its status bit also has two values: 0 and 1. When the status bit is 0, it means that the leaf node does not belong to the high-frequency access; when the status bit is 1, it means that the leaf node belongs to the high-frequency access.

3. The cache replacement method based on binary tree status bit management according to claim 2, wherein In Step B or C, the process of accessing the subtree according to the status of the binary tree nodes is as follows: Start searching from the root node of the binary tree. When encountering a status bit of 0, go left; when encountering a status bit of 1, go right, and recursively traverse the subtree until reaching the leaf node.

4. The cache replacement method based on binary tree status bit management according to claim 2, wherein In Step C, comparing the status bit of the selected leaf node with the status bit of the missed cache line includes: If the status bit of the selected leaf node is 0 and the status bit of the missed cache line is 0, replace the selected leaf node with the missed cache line; if the status bit of the selected leaf node is 0 and the status bit of the missed cache line is 1, replace the selected leaf node with the missed cache line; if the status bit of the selected leaf node is 1 and the status bit of the missed cache line is 0, do not perform replacement; if the status bit of the selected leaf node is 1 and the status bit of the missed cache line is 1, replace the selected leaf node with the missed cache line.

5. The cache replacement method based on binary tree status bit management according to claim 1 or 2, characterized in that The target cache line is the least recently accessed cache line.

6. The cache replacement method based on binary tree status bit management according to claim 1, wherein This method is used for parallel computing cache replacement.

7. A cache replacement system based on binary tree status bit management, characterized in that, It includes: An N-way set associative cache unit; A binary tree, there is a mapping relationship between the cache unit and the binary tree, the N cache lines of the cache unit are mapped to the N leaf nodes of the binary tree, and the internal nodes form the branches of the binary tree; Status bits, each internal node stores 1 status bit, which is used to indicate the subtree that may contain the target cache, and each leaf node stores 1 status bit, which is used to indicate whether the leaf node belongs to the high-frequency access category; In the initial state, set the status bits of all nodes of the binary tree to 0 and clear the cache lines. When the processor accesses the cache unit, access the subtree according to the status of the binary tree nodes until reaching the leaf node, fill the empty cache line, and after filling the cache line, flip the status values of the nodes on the path; When a cache hit occurs, if the status of the access path nodes required by the hit cache line is the same as the status of the internal node, the status of the internal node is flipped. If not, there is no need to flip. The nodes outside the access path required by the hit cache line keep their status bits unchanged. If the status bit of the leaf node at this time indicates that it does not belong to high-frequency access, the status bit is flipped. If the status bit of the leaf node indicates that it belongs to high-frequency access, the status bit remains unchanged; Evict the cache from the corresponding history queue; When a cache miss occurs and a cache line needs to be replaced, first check whether there is such a cache line in the history queue. If there is such a cache line in the history queue, set its status bit to 1 and evict the cache line; if there is no such cache line in the history queue, add the cache line to the history queue, set the status bit to 0, and then access the subtree according to the status of the binary tree nodes until reaching the leaf node. This leaf node is the selected leaf node. Compare the status bit of the selected leaf node with the status bit of the miss cache line. If the status bit of the selected leaf node is greater than the status bit of the miss cache line, do not replace the cache line, otherwise replace the cache line.

8. The cache replacement system based on binary tree status bit management according to claim 7, wherein This system is used for parallel computing cache replacement.

9. A cache replacement device based on binary tree status bit management, comprising a processor and a memory storing program instructions, characterized in that The processor is configured to execute the cache replacement method based on binary tree status bit management according to any one of claims 1 to 6 when running the program instructions.

10. A storage medium stores program instructions, characterized in that, When the program instructions are running, execute the cache replacement method based on binary tree status bit management according to any one of claims 1 to 6.

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