Neural network employing variable resolution

Abstract

The invention discloses neural networks employing variable resolution. Devices, systems, and techniques using one or more neural networks with adjusted resolution information are disclosed. In at least one embodiment, for example, one or more neural network low resolution encoders are trained to one or more higher resolutions. In at least one embodiment, as another example, a processor is to adjust a resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks.

Description

Technical Field

[0001] At least one embodiment relates to adjusting the resolution of information for use with one or more neural networks. For example, at least one embodiment relates to a processor and / or computing system for adjusting the resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks. Background Art

[0002] Techniques for using neural networks (e.g., to generate images) require a significant resource investment. Techniques for performing neural networks can be improved. Brief Description of the Drawings

[0003] Figure 1 is a block diagram showing a training circuit communicating with a neural network according to at least one embodiment;

[0004] Figure 2 is a block diagram showing the information flow within a training circuit communicating with a neural network according to at least one embodiment;

[0005] Figure 3 is a block diagram showing a processor and modules according to at least one embodiment;

[0006] Figure 4 is a block diagram showing a neural network training module according to at least one embodiment;

[0007] Figure 5 is a block diagram showing one or more neural networks adjusting resolution according to at least one embodiment;

[0008] Figure 6 is a block diagram showing one or more neural networks adjusting to a higher resolution using one or more neural network results according to at least one embodiment;

[0009] Figure 7 is a flowchart showing a process for adjusting resolution according to at least one embodiment;

[0010] Figure 8 is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more APIs according to at least one embodiment;

[0011] Figure 9A shows logic according to at least one embodiment;

[0012] Figure 9B shows logic according to at least one embodiment;

[0013] Figure 10Shows the training and deployment of a neural network according to at least one embodiment;

[0014] Figure 11 Shows an example data center system according to at least one embodiment;

[0015] Figure 12A Shows an example of an autonomous vehicle according to at least one embodiment;

[0016] Figure 12B Shows according to at least one embodiment Figure 12A An example of the camera position and field of view of an autonomous vehicle;

[0017] Figure 12C Is a block diagram showing an example system architecture of an autonomous vehicle according to at least one embodiment Figure 12A Of an autonomous vehicle;

[0018] Figure 12D Is a diagram showing a system for communication between one or more cloud-based servers and Figure 12A An autonomous vehicle according to at least one embodiment;

[0019] Figure 13 Is a block diagram showing a computer system according to at least one embodiment;

[0020] Figure 14 Is a block diagram showing a computer system according to at least one embodiment;

[0021] Figure 15 Shows a computer system according to at least one embodiment;

[0022] Figure 16 Shows a computer system according to at least one embodiment;

[0023] Figure 17A Shows a computer system according to at least one embodiment;

[0024] Figure 17B Shows a computer system according to at least one embodiment;

[0025] Figure 17C Shows a computer system according to at least one embodiment;

[0026] Figure 17D Shows a computer system according to at least one embodiment;

[0027] Figure 17E And Figure 17F Shows a shared programming model according to at least one embodiment;

[0028] Figure 18Shows an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0029] Figures 19A - 19B Shows an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0030] Figures 20A - 20B Shows additional exemplary graphics processor logic in accordance with at least one embodiment;

[0031] Figure 21 Shows a computer system in accordance with at least one embodiment;

[0032] Figure 22A Shows a parallel processor in accordance with at least one embodiment;

[0033] Figure 22B Shows a partitioning unit in accordance with at least one embodiment;

[0034] Figure 22C Shows a processing cluster in accordance with at least one embodiment;

[0035] Figure 22D Shows a graphics multiprocessor in accordance with at least one embodiment;

[0036] Figure 23 Shows a multi-graphics processing unit (GPU) system in accordance with at least one embodiment;

[0037] Figure 24 Shows a graphics processor in accordance with at least one embodiment;

[0038] Figure 25 Is a block diagram showing a processor microarchitecture for a processor in accordance with at least one embodiment;

[0039] Figure 26 Shows a deep learning application processor in accordance with at least one embodiment;

[0040] Figure 27 Is a block diagram showing an example neuromorphic processor in accordance with at least one embodiment;

[0041] Figure 28 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0042] Figure 29 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0043] Figure 30 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0044] Figure 31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figures 33A - 33B illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0047] Figure 34 illustrates a parallel processing unit (“PPU”) according to at least one embodiment;

[0048] Figure 35 illustrates a general processing cluster (“GPC”) according to at least one embodiment;

[0049] Figure 36 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment;

[0050] Figure 37 illustrates a streaming multiprocessor according to at least one embodiment;

[0051] Figure 38 is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0052] Figure 39 is a system diagram of an example system for training, adapting, instantiating, and deploying a machine learning model in an advanced computing pipeline according to at least one embodiment;

[0053] Figure 40 includes an example illustration of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0054] Figure 41A includes an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Figure 41B includes an example data flow diagram of a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Figure 42A illustrates a data flow diagram of a process for training a machine learning model according to at least one embodiment;

[0057] Figure 42B is an example illustration of a client - server architecture that utilizes a pre - trained annotation model to enhance an annotation tool according to at least one embodiment; and

[0058] Figure 43 Shows components of a system for accessing a large language model according to at least one embodiment. Detailed implementation

[0059] In at least one embodiment, the systems and methods implemented in accordance with the present disclosure are used to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part, based on one or more performance metrics of the one or more neural networks.

[0060] Figure 1 Is a block diagram showing a training circuit 102 communicating with a neural network 116 according to at least one embodiment. In at least one embodiment, the system 100 includes one or more training circuits 102 (e.g., training circuit 202), one or more processors 110 (e.g., processors 210, 302, 502, and / or 602), one or more image processors 112 (e.g., image processor 212), one or more result processors 114 (e.g., result processor 214), one or more neural networks 116 (e.g., neural networks 216, 510, 610, and / or 816), and / or combinations thereof. In at least one embodiment, the system 100 receives and / or uses one or more data sets (e.g., one or more low-resolution data sets 104, one or more medium-resolution data sets 106, and / or one or more high-resolution data sets 108) as input.

[0061] Training a neural network can use a large number of images to improve accuracy during inference, and each pixel of these images requires additional computational resources to process, which makes it costly to train a neural network with higher resolution (e.g., 1080x1080 pixels) images. A neural network trained with lower resolution images is easier and cheaper than one trained with higher resolution images, but cannot understand finer details and cannot accurately examine detailed images, such as images containing text. In at least one embodiment, system 100 includes a neural network 116 for performing image inference, which is trained using a series of images, starting from low resolution images (e.g., a low resolution dataset), and then progressing to higher resolution images (e.g., high resolution dataset 108), until the model reaches a desired resolution level (e.g., parity and / or sufficient results 512 and / or 612). For example, in at least one embodiment, for the first 80% of the training of neural network 116, one or more neural networks 510 are trained using one or more datasets 104-108 having a low resolution (e.g., 224x224 pixels) (e.g., including information such as images). In at least one embodiment, system 100 trains neural network 116 using one or more second datasets 104-108 having a higher resolution (e.g., 448x448 pixels) (e.g., including information such as the same images as in the first 80% of the training). In at least one embodiment, as the training of neural network 116 progresses, additional datasets of increasingly higher resolution (e.g., of image information) are used to train neural network 116 until a final resolution (e.g., 1120x1120 pixels) is reached. In at least one embodiment, the final resolution is reached when there is parity, e.g., a desired level of similarity between the ground truth image and the generated image. In at least one embodiment, each time the resolution is increased, the amount of data present in the dataset (e.g., including image data) of each dataset can be reduced, resulting in a reduction in the resource and time expenditure necessary to train the neural network to perform the image generation task. In at least one embodiment, the low resolution capable neural network 116 encoder progresses to being capable of high resolution encoding at least in part based on one or more of the training processes described herein. In at least one embodiment, by way of example, system 100 trains the neural network at least in part based on adjusting the resolution of one or more datasets, e.g., by increasing (e.g., adjusting) the resolution while reducing the time spent training at that resolution, thereby reducing the total resource expenditure but reaching a similar model for the target resolution at the end of the training.

[0062] In at least one embodiment, system 100 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 100 is a software program executed on computer hardware, an application executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 100 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU) (described below)) in any suitable manner, including sequentially, in parallel, and / or variants thereof. In at least one embodiment, system 100 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVETOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that also includes at least a GPU (e.g., an AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., an ADAM OPTIMIZER), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using a GAN loss).

[0063] In at least one embodiment, system 100 is composed of modules (e.g., modules 304 - 310) such that the system adjusts the resolution of information to be used by one or more neural networks and / or otherwise performs the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks. In at least one embodiment, a module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions as described. In at least one embodiment, a module includes one or more circuits that form part of a larger system (e.g., integrated circuit (IC), system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), etc.). In at least one embodiment, a controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions as described. In at least one embodiment, software includes a software package, code, programming language, driver, instruction, instruction set, or some combination thereof. In at least one embodiment, hardware includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, firmware storing instructions executed by programmable circuitry, or some combination thereof.

[0064] In at least one embodiment, system 100 includes one or more logic units. In at least one embodiment, a logic unit includes firmware logic, hardware logic, or some combination thereof configured to provide any of the functions further described herein. In at least one embodiment, a logic unit includes circuitry that forms part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit includes logic circuitry for implementing firmware and / or hardware to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks.

[0065] In at least one embodiment, system 100 includes one or more engines. In at least one embodiment, an engine includes modules and / or logic units as further described herein. In at least one embodiment, a component includes modules and / or logic units as further described herein. In at least one embodiment, an engine includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality further described herein. In at least one embodiment, a component includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality further described herein. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via software modules, which may be embodied as software packages, code, and / or instruction sets. In at least one embodiment, a logic unit may also utilize a portion of software to implement its functionality.

[0066] In at least one embodiment, system 100 receives one or more inputs, such as one or more data sets 104-108. In at least one embodiment, system 100 receives an input including one or more data sets having information of one or more ground truth images 104, masked ground truth images, captions, videos, video frames, sequence images, audio, text, symbols, previous inputs, trained neural networks, expert neural networks, feature maps, and / or other inputs described herein. In at least one embodiment, one or more neural networks 116 receive one or more data sets 104-108, which include information such as one or more ground truth images, feature maps, and / or captions (e.g., embedding information). In at least one embodiment, neural network 116 is a base neural network, such as an encoder that uses or does not use one or more captions.

[0067] In at least one embodiment, one or more data sets 104-108 include information such as data of one or more images, audio data, video data, and / or other inputs described herein. In at least one embodiment, the resolution of one or more low-resolution data sets 104 is relatively lower than the resolution of the medium-resolution data sets 106, for example, the low resolution is 224x224 (e.g., a matrix representing pixels and / or features in an image) and / or 300x300 pixels. In at least one embodiment, the resolution of one or more medium-resolution data sets 106 is relatively lower than the resolution of the high-resolution data sets 108, for example, the medium resolution is 400x400, 448x448, 512x512, 700x700, and / or 896x896 pixels. In at least one embodiment, the resolution of one or more high-resolution data sets 108 is relatively higher than the resolution of the medium-resolution data sets 106, for example, 1024x1024 and / or 1120x1120 pixels. In at least one embodiment, one or more data sets 104-108 are used for one or more resolutions (e.g., a matrix representing one or more pixels of an image). In at least one embodiment, the matrix is described as a tensor.

[0068] In at least one embodiment, the system 100 including the neural network 116 uses the data sets 104-108 to perform data processing (e.g., image processing). In at least one embodiment, image processing (or the processing of an image) is the analysis or manipulation of a digital image, such as generating an image from a noisy image, improving quality, and / or generating an image in a form that can be received as an input. In at least one embodiment, an image may include a digital image, a photograph, a training image, a video frame, a video game frame, and / or a set of frames of a video or a video game. In at least one embodiment, an image is a compilation of pixels, features, data, tensors, and / or other representative forms of an image. In at least one embodiment, a pixel is a point on an image that presents a shade, opacity, or color. In at least one embodiment, a pixel is represented in data form (e.g., grayscale, RGB, RGBA, or other variants). In at least one embodiment, one or more pixels are represented as one or more matrices (e.g., tensors). In at least one embodiment, image processing is performed by a processor including circuitry for analyzing or manipulating an image. In at least one embodiment, image processing is performed by a neural network. In at least one embodiment, examples of image processing include scaling, undistorting, cropping, visualizing, recognizing, sharpening, restoring, pattern recognition, and / or image retrieval. In at least one embodiment, the neural network 116 is Figures 9A to 43 one or more neural networks described in

[0069] In at least one embodiment, the processor 110 (e.g.,Figures 9A to 43 One or more processors (e.g., the one or more processors shown in any of Figure 4 ) include an image processor 112 and / or a result processor 114. In at least one embodiment, the image processor 112 receives input from one or more data sets (e.g., data sets 104-108) and modifies the data in the data sets to generate the data at an adjusted resolution for the processor. In at least one embodiment, by way of example, the image processor 114 receives a high-resolution data set 108 (e.g., 1200x1200) including one or more images and generates a lower-resolution data set (e.g., 400x400) by cropping the images to include only the resolution being generated (e.g., 400x400 pixels) and then changing it to a data format that can be received by the neural network 116 (e.g., so that the same encoder can use pixelated low-resolution images and high-resolution images that will be received in the same data format). In at least one embodiment, the image processor 114 adjusts one or more image resolutions, e.g., by performing Figure 4 one or more operations described in

[0070] In at least one embodiment, the processor 110 provides data (e.g., one or more images) to train the neural network 116 (e.g., neural networks 216, 510, 610, and / or 816; see Figure 1 , Figure 5 , Figure 6 and / or Figure 8 ) for inference and / or to determine the capabilities of the neural network 116 (e.g., sufficient results 512). In at least one embodiment, the processor 110 is provided with input from the neural network 116 (e.g., inference data) and / or the training data set (e.g., resolution data sets 104-108). In at least one embodiment, the processor 110 internally provides these inputs to the image processor 112 and / or the result processor 114. In at least one embodiment, the processor 110 provides an output (e.g., the training data set) to the neural network 116. In at least one embodiment, the result processor 114 determines whether the results of the neural network 116 are sufficient (e.g., sufficient results 512 and / or 612) for the neural network 116 to progress to a higher-resolution training data set than the one currently being used. In at least one embodiment, the result is sufficient when the data generated by the neural network reaches a threshold similarity (e.g., parity) with the expert's ground truth. In at least one embodiment, the processor 110 performs one or more processes (e.g., process 700, see Figure 7 ).

[0071] In at least one embodiment, system 100 adjusts the resolution of information to be used by one or more neural networks and / or otherwise performs the operations described herein, at least in part, based on one or more performance metrics of the one or more neural networks. In at least one embodiment, system 100 is Figures 1 to 8 the system shown in for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of the one or more neural networks, including in the system and / or otherwise including the system. In at least one embodiment, system 100 performs Figures 1 to 8 one or more processes shown in, such as for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of the one or more neural networks. In at least one embodiment, system 100 includes Figures 9A to 43 one or more hardware shown in, such as for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein.

[0072] Figure 2 is a block diagram showing the information flow within training circuit 202 in communication with neural network 216 according to at least one embodiment. In at least one embodiment, system 200 includes one or more training circuits 202 (e.g., training circuit 102), one or more processors 210 (e.g., processors 110, 302, 502, and / or 602), one or more image processors 212 (e.g., image processor 112), one or more result processors 214 (e.g., result processor 114), one or more neural networks 216 (e.g., neural networks 116, 510, 610, and / or 816), and / or combinations thereof. In at least one embodiment, system 200 receives and / or uses one or more data sets (e.g., one or more low-resolution data sets 204, one or more medium-resolution data sets 206, and / or one or more high-resolution data sets 208) as inputs.

[0073] In at least one embodiment, system 200 progressively trains an encoder with low-resolution capabilities to have high-resolution capabilities using one or more processes. In at least one embodiment, system 200 builds a visual encoder with high-resolution capabilities at least in part starting from a low-resolution encoder and periodically increases the resolution of the neural network 216 training once the results have converged with the lower-resolution results. In at least one embodiment, as an example, when there is a threshold similarity to the results previously capable of being obtained at a lower resolution, the result processor 214 determines that the results are sufficient (e.g., sufficient results 512 and / or 612) to progress to a higher resolution. In at least one embodiment, to this end, system 200 starts training with a low-resolution dataset 204 of images (e.g., 224x224 pixels), then doubles it to a medium resolution 206 (e.g., 448x448 pixels), then doubles the resolution to a medium and / or high-resolution dataset 206 and / or 208 (e.g., 896x896), and finally increases to a high-resolution dataset 208 (e.g., 1120x1120). In at least one embodiment, the datasets 204-208 are generated at least in part based on the image dataset received by the image processor 212.

[0074] In at least one embodiment, the training circuit 102 trains the neural network 116 to perform a data processing task, such as processing of an image. In at least one embodiment, by way of example, the training circuit has four progressively scaled image resolution data sets 104-108 (e.g., data set A can be a 360x360 pixel image, data set B can be a 720x720 pixel image, data set C can be a 1440x1140 pixel image, data set D can be a 2280x2280 pixel image). In at least one embodiment, for example, each progressive data set (e.g., data sets 104-108) includes fewer data points than the previous data set (e.g., data set A includes 10,000 images, data set B includes 1,000 images, data set C includes 100 images, data set D includes 10 images). For example, in at least one embodiment, the training circuit 102 trains one or more neural networks 116 on a given data set until a predetermined level of ability is shown (e.g., a neural network 116 intended for image reconstruction may require an 80% average of image pixel reconstruction). For example, in at least one embodiment, the system 100 tests the neural network 116 for image reconstruction until the training circuit 102 calculates an 80% ability on a first data set (e.g., data set 104), at which point the training circuit 102 can progress to the next data set (e.g., data sets 106 and / or 108) to perform inference at a higher resolution. In at least one embodiment, the system 100 that performs the process described herein iterates until a desired resolution and ability are reached, at which point the process performs one or more of the operations described herein and / or ends. In at least one embodiment, the system 100 trains the neural network 116 to the same ability and / or resolution in the same or less time using fewer computing resources. In at least one embodiment, for example, the processor 110 including circuitry uses one or more processors that at least partially train the neural network 116 based on the neural network 116 image training circuit 102 to perform tasks based on high-resolution images and / or otherwise perform the operations described herein.

[0075] In at least one embodiment, the system 200 adjusts the resolution of the information to be used by one or more neural networks and / or otherwise performs the operations described herein based at least in part on one or more performance metrics of the one or more neural networks. In at least one embodiment, the system 200 is Figures 1 to 8 the system shown in for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein based at least in part on one or more performance metrics of the one or more neural networks, included in the system and / or otherwise including the system. In at least one embodiment, the system 200 performsFigures 1 to 8 One or more processes as shown, e.g., for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein based at least in part on one or more performance metrics of one or more neural networks. In at least one embodiment, system 200 includes Figures 9A to 43 One or more hardware as shown, e.g., for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein based at least in part on one or more performance metrics of one or more neural networks.

[0076] Figure 3 is a block diagram showing a processor 302 and modules 304 - 310 according to at least one embodiment. In at least one embodiment, system 300 includes a processor 302 and modules 304 - 512. In at least one embodiment, the processor 302 executes one or more processes (e.g., the processes described herein) to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein based at least in part on one or more performance metrics of one or more neural networks (e.g., sufficient results 512 and / or 612). In at least one embodiment, the processor 302 executes neural network training and / or image generation processes (e.g., as described above in connection with Figures 1 to 8 described).

[0077] In at least one embodiment, the processor 302 includes one or more circuits for performing one or more operations as described below. In at least one embodiment, the processor 302 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof, including those further described herein. In at least one embodiment, the processor 302 includes one or more neural network training modules 304, encoder modules 306, training convergence modules 308, and / or image resolution modules 310.

[0078] In at least one embodiment, the neural network training module 304, encoder module 306, training convergence module 308, and / or resolution adjustment module 310 include one or more circuits of the processor 302 and / or one or more other processors. In at least one embodiment, the neural network training module 304, encoder module 306, training convergence module 308, and / or resolution adjustment module 310 are distributed among multiple processors that communicate via a bus, network, write to shared memory, and / or any suitable communication process (e.g., the communication processes described herein).

[0079] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software is embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein includes (e.g., individually or in any combination) hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by the programmable circuitry. In at least one embodiment, a module is collectively or individually embodied as circuitry that forms part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), etc.). In at least one embodiment, a module executes one or more processes in conjunction with any suitable processing unit and / or combination of processing units (e.g., one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof, including those further described herein).

[0080] In at least one embodiment, the neural network training module 304 (e.g., the neural network training module 402) is a module that, if executed, causes one or more processors 302 to train one or more neural networks to perform one or more processing tasks, such as by at least partially adjusting the resolution of information to be used by the neural network (e.g., in training) based on one or more performance metrics. In at least one embodiment, the neural network training module 304 causes one or more processors 302 to execute one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause or are otherwise available for execution of the one or more processes by the one or more processors 302. For example, in at least one embodiment, the neural network training module 304 causes one or more processors 302 to perform training of a neural network to perform image processing and / or generate images, videos, and / or image sequences. In at least one embodiment, the neural network training module 304 includes a resolution adjustment module 310 and / or a training convergence module 308. In at least one embodiment, the neural network training module 304 obtains or otherwise has one or more instructions and / or identifiers of one or more instructions (including Figure 1 the instructions therein). For example, in at least one embodiment, the neural network training module 304 trains a neural network (e.g., a base model or a vision model) that includes one or more encoders to generate captions for images and / or otherwise perform the operations described herein by at least partially adjusting the resolution of information using performance metrics.

[0081] In at least one embodiment, the encoder module 306 is a module that causes one or more processors to generate and / or execute one or more software instructions (e.g., software instructions of an executable software program, including executable code) to use a base (e.g., vision) neural network. For example, in at least one embodiment, the encoder module 306 causes one or more processors 302 to use one or more neural networks to encode information into one or more data sets (e.g., data sets representing images) and / or to otherwise perform the operations described herein. In at least one embodiment, the encoder module 306 causes one or more processors 302 to execute an encoding neural network, e.g., the pixel masking and encoding neural network used by the neural network training module 304 (e.g., to train a neural network or by a neural network training). In at least one embodiment, the encoder module 306 causes one or more processors 302 to execute one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise available for the execution of the one or more processes. As an example, in at least one embodiment, software causes one or more processors 302 to use an encoding neural network, e.g., a transformer.

[0082] In at least one embodiment, the training convergence module 308 is a module that causes one or more processors 302 to determine whether training performed at a resolution has converged to a previous resolution (e.g., a lower resolution) (e.g., parity). As an example, in at least one embodiment, instructing the neural network to be trained at a higher resolution is performed by the training convergence module 308, e.g., in conjunction with Figures 1 to 8 as described. In at least one embodiment, the training convergence module 308 causes one or more processors 302 to execute the one or more processes, e.g., the processes described herein, by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise available for the execution of the one or more processes. In at least one embodiment, as an example, the training convergence module 308 causes one or more processors 302 to calculate whether the neural network has achieved sufficient results 512 and / or 612 at the resolution of training, e.g., by using the results of the encoder module 306 and / or determining that the neural network will be adjusted to a higher resolution module in conjunction with the resolution adjustment module 310. In at least one embodiment, the training convergence module 308 is a module that causes one or more processors to generate and / or execute one or more software instructions, e.g., to determine whether one or more results of a neural network using a loss function are sufficient using one or more performance characteristics.

[0083] In at least one embodiment, the resolution adjustment module 310 is a module that causes one or more processors 302 to adjust the resolution of information, such as when training a neural network in conjunction with the neural network training module 304. For example, in at least one embodiment, the processor uses the resolution adjustment module 310 to adjust the resolution at least in part based on one or more performance characteristics of the neural network (e.g., parity, similarity of the generated image to the ground truth, accuracy, and / or one or more loss calculations), as Figures 1 to 8 shown. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions to perform the one or more processes by at least executing instructions that cause the execution of one or more processes or are otherwise available for the execution of one or more processes, such as the processes described herein. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions of a software program, such as increasing the use of the neural network to a higher resolution at least in part based on segmenting an original image into a desired resolution and changing the data format of the image of the desired resolution. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to execute one or more instructions to perform one or more processes, such as in conjunction with Figures 1 to 8 the processes described. In at least one embodiment, the resolution adjustment module 310 causes one or more processors 302 to adjust the resolution of information (e.g., a data set including information such as an image) at least in part based on the performance characteristics of the neural network, such as by using one or more loss functions for the results of the encoder related to the encoder module 306.

[0084] In at least one embodiment, the system 300 adjusts the resolution of information to be used by one or more neural networks and / or otherwise performs the operations described herein at least in part based on one or more performance metrics of one or more neural networks. In at least one embodiment, the system 300 is Figures 1 to 8 the system shown in for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein at least in part based on one or more performance metrics of one or more neural networks, including in the system and / or otherwise including the system. In at least one embodiment, the system 300 performs Figures 1 to 8 the one or more processes shown in, such as for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein at least in part based on one or more performance metrics of one or more neural networks. In at least one embodiment, the system 300 includes Figures 9A to 43One or more of the hardware shown, such as to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks.

[0085] Figure 4 is a block diagram showing a neural network training module 402 according to at least one embodiment. In at least one embodiment, the neural network training module 402 (e.g., neural network training module 304) includes a training convergence module 308. In at least one embodiment, the system 400 executes the neural network training module 402.

[0086] In at least one embodiment, the neural network training module 402 is a module that causes one or more processors 302 to perform the training of a neural network by at least partially adjusting the resolution of information (e.g., image information) based on performance characteristics, such as when the neural network training module 402 determines whether training at a certain resolution has converged to a previous resolution (e.g., a lower resolution) (e.g., parity). As an example, in at least one embodiment, training one or more neural networks at one or more information resolutions is performed by the neural network training module 402, such as in conjunction with Figures 1 to 8 as described. In at least one embodiment, the neural network training module 402 causes one or more processors 302 to perform the one or more processes by at least including or otherwise encoding instructions that cause the execution of one or more processes or are otherwise available for the execution of one or more processes, such as the processes described herein. In at least one embodiment, as an example, the neural network training module 402 causes one or more processors 302 to calculate whether a neural network has achieved sufficient results 512 and / or 612 at a training resolution, such as by using the results of the encoder module 306 and / or determining that the neural network will be adjusted to a higher resolution module in conjunction with the resolution adjustment module 310. In at least one embodiment, the neural network training module 402 is a module that causes one or more processors to generate and / or execute one or more software instructions, such as for training a neural network by at least partially adjusting the resolution of information based on one or more performance characteristics (e.g., one or more loss functions (e.g., visual reconstruction loss, contrast caption loss, feature matching loss, object recognition loss correction, text recognition loss correction, and / or generated caption loss)).

[0087] In at least one embodiment, the neural network training module 402 includes training one or more neural network encoders to receive one or more images of lower resolution pixelization 404 and higher resolution pixelization 406 when training of the lower resolution pixelization has converged to a desired result (e.g., using one or more performance characteristics) at a lower resolution. In at least one embodiment, the neural network training module 402 generates information at one or more resolutions at a high resolution (e.g., 1200x1200 pixelization) by using a data set with a relatively small amount of training data 410 (e.g., the amount of training data 410 is relatively small compared to a low-resolution data set with a relatively large amount of training data 408). In at least one embodiment, by way of example, in the first set of low-resolution pixelization 404 training, the image is cropped to 224x224, for medium resolution, the same original image (e.g., 1000x1000) will be cropped to 448x448, and when the training converges at a lower resolution determined using one or more performance characteristics, this is repeated for the higher resolution pixelization 406 (e.g., 896x896 and 1120x1120).

[0088] In at least one embodiment, the system 400 uses an encoder with low-resolution capabilities, which progresses to an encoder with high-resolution capabilities through one or more of the described training processes. In at least one embodiment, although the received images have different resolutions, the data format of the received images remains consistent. In at least one embodiment, the neural network training module 402 intercepts the cropped 224x224 portion of the image and increases the data format size of the image to fit the preferred data format of the encoder (e.g., the matrix size for the highest resolution). In at least one embodiment, by way of example, if there is an image of a road and sky at a high resolution, the image will be cropped to 224x224 and then enlarged, resulting in a decrease in resolution (e.g., becoming more pixelated). In at least one embodiment, in this more pixelated version of a portion of the road and sky, the data format received by the encoder will still have a high resolution (e.g., 1120x1120), however, when creating the feature map, one or more assigned values can be repeatedly assigned for a set of pixels corresponding to the 224x224 resolution.

[0089] In at least one embodiment, one or more neural networks are confidence-aware neural networks, where the received data format is the sum of learned filters, e.g., by automatically adjusting via training. In at least one embodiment, one or more neural networks are transformer neural networks that adjust the resolution pixelated data format (e.g., 404 and / or 406) by interpolating the position embeddings learned at one resolution to another resolution, e.g., performing an interpolation operation when adjusting (e.g., changing) to a higher resolution. In at least one embodiment, as an example, when the resolution changes from a 10x10 grid to a 20x20 grid resolution pixelation (e.g., higher resolution pixelation 406), the image information is stretched and one or more embeddings are re-learned (e.g., extracting the previously learned embeddings and placing them within one or more new embeddings). In at least one embodiment, the transformer neural network learns scale invariance. In at least one embodiment, the neural network adjusts the representation to one or more higher resolutions. In at least one embodiment, one or more neural networks use bilinear interpolation of pixels, e.g., performing an average and / or approximation (e.g., linear) between two pixels.

[0090] In at least one embodiment, one or more convolutional data formats can receive one or more data formats that vary with resolution, where the encoder is adjusted to a data format. In at least one embodiment, interpolation is added to the original tensor and it is considered bilinear interpolation to obtain a higher resolution. In at least one embodiment, another variation is to add null values (e.g., 0) to the matrix to account for the change in resolution to achieve a sufficient data format, although it will rely on differential gradients to change the bias away from zero. In at least one embodiment, the neural network can also copy the values of the nearest neighbors when transitioning (e.g., adjusting) between one or more resolutions. In at least one embodiment, the convolutional neural network adjusts the processing to one or more parameters of the input dimension and / or one or more matrices. In at least one embodiment, one or more neural networks include vision transformers for interpolating one or more position embeddings.

[0091] In at least one embodiment, the neural network training module 412 adjusts the resolution, e.g., by using progressive scaling, upscaling, downscaling, variable scaling (e.g., a combination of upscaling and / or downscaling), cyclic scaling (e.g., the resolution moves from low resolution to medium resolution to high resolution and then from high resolution to medium resolution to low resolution), repeated progressive scaling, or combinations thereof. In at least one embodiment, by way of example, the neural network training module 412 performs a round of training, e.g., using 100 lower resolution images, 20 higher resolution images, repeating one or more iterations. In at least one embodiment, the amount of training data varies at least in part based on the resolution of the information, e.g., the lower resolution pixelation 404 uses a greater amount of training data 408 than the higher resolution pixelation 405 that uses a lesser amount of training data 410 (e.g., less than the low resolution data set). In at least one embodiment, use otherwise is generate, train, execute, and / or run.

[0092] In at least one embodiment, the system 400 adjusts the resolution of the information to be used by one or more neural networks and / or otherwise performs the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks. In at least one embodiment, the system 400 is Figures 1 to 8 the system shown in for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks, including in the system and / or otherwise including the system. In at least one embodiment, the system 400 performs Figures 1 to 8 one or more of the processes shown in, e.g., for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks. In at least one embodiment, the system 400 includes Figures 9A to 43 one or more of the hardware shown in, e.g., for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein.

[0093] Figure 5It is a block diagram showing one or more neural networks 510 for adjusting resolution according to at least one embodiment. In at least one embodiment, system 500 includes one or more processors 502 (e.g., one or more of processors 110, 210, 302, 502A-C, and / or 602) and one or more neural networks 510 (e.g., neural networks 116, 216, 610, and / or 816). In at least one embodiment, neural network 510 includes one or more of the neural networks shown herein, such as one or more neural networks including a transformer, an image and / or text encoder, a contrast loss operation, a pixel mask, an object depth identifier, a text identifier, an object identifier, a task expert neural network, an image and / or text decoder, or a combination thereof.

[0094] In at least one embodiment, neural network 510 includes a decoder. In at least one embodiment, the decoder decodes 104 an input video frame or image (e.g., a visual decoder) after receiving the input. In at least one embodiment, the decoded image is to convert the encoded image back to an uncompressed bitmap, which can then be rendered. In at least one embodiment, the step of decoding the image is a process opposite to that of the encoded image. In at least one embodiment, by way of example, a processor (e.g., an image processing engine, an image processing unit, or an image signal processor) includes circuitry for decoding an image. In at least one embodiment, the decoded image is performed by at least one neural network.

[0095] In at least one embodiment, system 500 includes one or more data sets (e.g., data sets 504-508, which are generated at one or more resolutions (e.g., from an original data set)). In at least one embodiment, one or more data sets 504-508 (e.g., data sets 604-608 and / or 104-108) include information, such as one or more images, audio data, video data, and / or other input data described herein. In at least one embodiment, the resolution of one or more low-resolution data sets 504 is relatively lower than the resolution of medium-resolution data sets 506, e.g., low resolution 224x224 (e.g., a matrix representing pixels and / or features in an image) and / or 300x300 pixels. In at least one embodiment, the resolution of one or more medium-resolution data sets 506 is relatively lower than the resolution of high-resolution data sets 508, e.g., medium resolution 400x400, 448x448, 512x512, 700x700, and / or 896x896 pixels. In at least one embodiment, the resolution of one or more high-resolution data sets 508 is relatively higher than the resolution of medium-resolution data sets 506, e.g., 1024x1024 and / or 1120x1120 pixels. In at least one embodiment, one or more data sets 104-108 are used for one or more resolutions (e.g., a matrix representing one or more pixels of an image). In at least one embodiment, the matrix is described as a tensor.

[0096] In at least one embodiment, neural network 510 is in a cloud processing environment (e.g., a cloud network), e.g., where one or more processors access neural network 510. In at least one embodiment, 502A-C are all the same processor that executes neural network 510. In at least one embodiment, one or more processors 502A-C call a neural network stored on another processor, e.g., by using one or more APIs. In at least one embodiment, by way of example, one or more processors 502 execute one or more of datasets 504-508 to train neural network 510 and measure the performance for low-resolution dataset 504 using one or more performance metrics (e.g., accuracy, convergence to the true value, and / or loss function) of the result 514 of neural network 510 until the result 514 reaches a sufficient result 512 (e.g., reaches a threshold of one or more performance metrics). In at least one embodiment, by way of example, processor 502A executes the low-resolution dataset to train neural network 510 and measures the performance for low-resolution dataset 504 using one or more performance metrics (e.g., accuracy, convergence to the true value, and / or loss function) of the result 514A of neural network 510 until the reached result 514A is used to calculate a sufficient performance result 512A (e.g., reaches a threshold of one or more performance metrics). In at least one embodiment, system 100 including neural network 116 uses datasets 104-108 to perform data processing (e.g., image processing).

[0097] In at least one embodiment, system 500 adjusts the resolution of the information to be used by one or more neural networks and / or otherwise performs the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks. In at least one embodiment, system 500 is Figures 1 to 8 the system shown in for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks, included in the system and / or otherwise including the system. In at least one embodiment, system 500 executes Figures 1 to 8 one or more of the processes shown in, e.g., for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks. In at least one embodiment, system 500 includes Figures 9A to 43 one or more of the hardware shown in, e.g., for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks.

[0098] Figure 6 It is a block diagram showing that one or more neural networks 610 adjust to a higher resolution using the results 614 of one or more neural networks 610 according to at least one embodiment. In at least one embodiment, system 600 includes one or more processors 602 (e.g., one or more of processors 110, 210, 302, 502, and / or 602A-C) and one or more neural networks 610. In at least one embodiment, neural network 610 includes one or more of the neural networks shown herein (e.g., neural networks 116, 216, 510, and / or 816), such as one or more neural networks including a transformer, an image and / or text encoder, a contrast loss operation, a pixel mask, an object depth identifier, a text identifier, an object identifier, a task expert neural network, an image and / or text decoder, or a combination thereof.

[0099] In at least one embodiment, system 600 includes one or more data sets (e.g., data sets 604-608, which are generated at one or more resolutions (e.g., from an original data set)). In at least one embodiment, one or more of data sets 604-608 include information, such as one or more images, audio data, video data, and / or other input data described herein. In at least one embodiment, the resolution of one or more low-resolution data sets 604 is relatively lower than the resolution of medium-resolution data set 606, e.g., low resolution 224x224 (e.g., a matrix representing pixels and / or features in an image) and / or 300x300 pixels. In at least one embodiment, the resolution of one or more medium-resolution data sets 606 is relatively lower than the resolution of high-resolution data set 608, e.g., medium resolution 400x400, 448x448, 612x612, 700x700, and / or 896x896 pixels. In at least one embodiment, the resolution of one or more high-resolution data sets 608 is relatively higher than the resolution of medium-resolution data set 606, e.g., 1024x1024 and / or 1120x1120 pixels. In at least one embodiment, one or more of data sets 104-108 are used for one or more resolutions (e.g., a matrix representing one or more pixels of an image). In at least one embodiment, the matrix is described as a tensor.

[0100] In at least one embodiment, the neural network 610 is in a cloud processing environment (e.g., a cloud network), e.g., where one or more processors access the neural network 610. In at least one embodiment, 602A-C are all the same processor that executes the neural network 610. In at least one embodiment, one or more processors 602A-C call a neural network stored on another processor, e.g., by using one or more APIs. In at least one embodiment, by way of example, one or more processors 602 execute one or more of the datasets 604-608 to train the neural network 610 and measure the performance for the low-resolution dataset 604 using one or more performance metrics (e.g., accuracy, convergence to the ground truth, and / or loss function) of the results 614 of the neural network 610 until the results 614 reach a sufficient result 612 (e.g., reach a threshold of one or more performance metrics). In at least one embodiment, by way of example, processor 602A executes the low-resolution dataset to train the neural network 610 and measures the performance for the low-resolution dataset 604 using one or more performance metrics (e.g., accuracy, convergence to the ground truth, and / or loss function) of the results 614A of the neural network 610 until the reached results 614A are used to calculate a sufficient performance result 612A (e.g., reach a threshold of one or more performance metrics). In at least one embodiment, the system 100 including the neural network 116 uses the datasets 104-108 to perform data processing (e.g., image processing).

[0101] In at least one embodiment, one or more neural networks 610 receive a masked input 616 (e.g., an image with randomized one or more pixel values), a ground truth 618 input, and / or one or more of the inputs described herein. In at least one embodiment, the neural network 610 includes one or more differentiable expert systems 624 (e.g., one or more vision foundation models), such as for performing the training of the neural network 610 at least in part by comparing the generated information with the information generated or included in the ground truth using one or more loss functions. In at least one embodiment, the differentiable expert system 624 includes one or more of the neural networks described herein. In at least one embodiment, the differentiable expert system receives one or more inputs from one or more vision decoders 622. In at least one embodiment, the system 600 uses the neural network 610 to generate one or more results 614 using one or more loss calculations 630 (e.g., visual reconstruction loss, contrast caption loss, feature matching loss, object recognition loss correction, text recognition loss correction, and / or generative caption loss), e.g., the neural network 610 with or without the differentiable expert system 624.

[0102] In at least one embodiment, neural network 610 includes one or more visual decoders 622. In at least one embodiment, visual decoder 622 decodes the input (e.g., an image and / or video frame) received from visual encoder 620 (e.g., visual decoder). In at least one embodiment, decoding an image is to convert the encoded image back to an uncompressed bitmap, which can then be rendered. In at least one embodiment, the step of decoding an image is a process opposite to that of encoding an image. In at least one embodiment, by way of example, a processor (e.g., an image processing engine, an image processing unit, or an image signal processor) includes circuitry for decoding an image. In at least one embodiment, decoding an image is performed by at least one neural network 610.

[0103] In at least one embodiment, differentiable expert system 624 receives the output of visual decoder 622 and performs one or more loss calculations 630 described herein, such as feature matching loss 632, using the output 626 generated from the masked input and the output 628 generated from the ground truth. In at least one embodiment, the values of one or more loss calculations 630 are used as result 614 for one or more processors 602. In at least one embodiment, processor 602 then uses result 614 to perform one or more performance calculations (e.g., comparing with an expected result) to generate one or more performance metrics to determine whether neural network 610 has achieved sufficient results to progress to a higher resolution dataset. In at least one embodiment, by way of example, result 614B of neural network 610 performing medium resolution dataset 606 is determined by processor 602B to have sufficient results 612B to progress to be trained by processor 602C using high resolution dataset 608.

[0104] In at least one embodiment, system 600 adjusts the resolution of the information to be used by one or more neural networks and / or otherwise performs the operations described herein, at least in part based on one or more performance metrics of one or more neural networks. In at least one embodiment, system 600 is Figures 1 to 8 the system shown in for adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of one or more neural networks, including in the system and / or otherwise including the system. In at least one embodiment, system 600 performs Figures 1 to 8 one or more processes shown in, such as adjusting the resolution of the information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of one or more neural networks. In at least one embodiment, system 600 includesFigures 9A to 43 One or more of the hardware shown, such as for adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, based at least in part on one or more performance metrics of the one or more neural networks.

[0105] Figure 7 is a flowchart showing a process 700 for adjusting resolution according to at least one embodiment. In at least one embodiment, process 700 starts 702 (e.g., begins) when called, such as by one or more processors (e.g., using API 810). In at least one embodiment, process 700 includes one or more steps for training using a low-resolution dataset 705, training using a high-resolution dataset 515, performing one or more of the operations described herein, or a combination thereof.

[0106] In at least one embodiment, part or all of process 700 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) to be executed jointly by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions usable to execute process 700 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 700 is executed at least in part on a computer system (e.g., the computer systems described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes process 700.

[0107] In at least one embodiment, a low-resolution data set is a data set with a pixel resolution lower than that of a subsequent data set (e.g., low-resolution data sets 104, 204, 504, and / or 604). In at least one embodiment, a high-resolution data set is a data set with a pixel resolution higher than that of a previous data set used in training (e.g., high-resolution data sets 108, 208, 508, and / or 608). In at least one embodiment, the processor executes process 700 to include training using a lower-resolution data set 705 to generate results (e.g., results 514 and / or 614) of one or more neural networks (e.g., neural networks 116, 216, 510, 610, and / or 816) to be received by decision block 710. In at least one embodiment, if a desired result (e.g., a performance metric, ability, convergence, and / or parity) is achieved, the decision in decision block 710 is "yes"; otherwise, the decision is "no". In at least one embodiment, if the decision in decision block 710 is "no", the processor continues to train using the lower-resolution data set 705 to generate one or more results. In at least one embodiment, if the decision in decision block 710 is "yes", the processor continues to train the neural network using the high-resolution data set 715. In at least one embodiment, the processor executes process 700 to include training using a higher-resolution data set 715 to generate results (e.g., results 514 and / or 614) of one or more neural networks (e.g., neural networks 116, 216, 510, 610, and / or 816) to be received by decision block 720. In at least one embodiment, if a desired result (e.g., a performance metric, ability, convergence, and / or parity) is achieved, the decision in decision block 720 is "yes"; otherwise, the decision is "no". In at least one embodiment, if the decision in decision block 720 is "no", the processor continues to train using the high-resolution data set 715 to generate one or more results. In at least one embodiment, if the decision in decision block 720 is "yes", the processor continues to perform one or more operations described herein (e.g., training at another resolution) and / or ends 725.

[0108] In at least one embodiment, one or more processors use process 700 to, for example, adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks. In at least one embodiment, as an example, a set of instructions is stored on a machine-readable medium (e.g., non-transitory) that, if executed by one or more processors, causes the one or more processors to perform process 700 to, for example, adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks. In at least one embodiment, process 700 is Figures 1 to 8 the process shown in to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks, including in and / or otherwise including the process. In at least one embodiment, Figures 1 to 8 one or more systems shown in perform process 700 to, for example, adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks. In at least one embodiment, Figures 9A to 43 one or more hardware shown in uses process 700 to, for example, adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of the one or more neural networks.

[0109] Figure 8 is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more APIs according to at least one embodiment.

[0110] Figure 8 is block diagram 800 showing a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 802 is a software module. In at least one embodiment, software program 802 includes one or more software modules. In at least one embodiment, the software modules are further described non-exclusively as Figure 8 shown in. In at least one embodiment, one or more APIs 810 are software instruction sets that, if executed, cause one or more processors (e.g., Figure 5810) performs one or more computing operations. In at least one embodiment, one or more APIs 810 are distributed or otherwise provided as part of one or more libraries 806, driver / runtime 804, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 810 perform one or more computing operations in response to a call by a software program 802. In at least one embodiment, a software program 802 is a collection of software codes, commands, instructions, or other text sequences for instructing a computing device to perform one or more computing operations and / or call one or more other instruction sets (e.g., API 810 or API function 812) to be executed. In at least one embodiment, the functionality provided by one or more APIs 810 includes software functions 812, such as software functions that can be used to accelerate one or more parts of a software program 802 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)).

[0111] In at least one embodiment, the API 810 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 810 described herein are implemented as one or more circuits for performing the following combined Figures 1 to 8 In at least one embodiment, one or more software programs 802 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform operations in conjunction with Figures 1 to 8 One or more techniques further described.

[0112] In at least one embodiment, a software program 802, such as a user-implemented software program, utilizes one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, which respectively perform one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, one or more APIs 810 provide functions 812 to cause a neural network to generate one or more images, such as using one or more images with or without subtitles, and / or otherwise perform operations described herein.

[0113] In at least one embodiment, one or more software programs 802 interact or otherwise communicate with one or more APIs 810 to perform one or more computational operations using one or more PPUs (such as GPUs). In at least one embodiment, one or more computational operations using one or more PPUs include at least one set or more of computational operations that will be accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 802 interact with one or more APIs 810 to perform audio-to-text processing.

[0114] In at least one embodiment, an interface is software instructions that, when executed, provide access to one or more functions 812 provided by one or more APIs 810. In at least one embodiment, a software program 802 uses a native interface when a software developer compiles one or more software programs 802 in conjunction with one or more libraries 806 that include one or more APIs 810 or otherwise provide access to one or more APIs 810. In at least one embodiment, one or more software programs 802 are statically compiled in conjunction with a pre-compiled library 806 or uncompiled source code that includes instructions to execute one or more APIs 810. In at least one embodiment, one or more software programs 802 are dynamically compiled, and the one or more software programs utilize a linker to link to one or more pre-compiled libraries 806 that include one or more APIs 810.

[0115] In at least one embodiment, a software program 802 uses a remote interface when a software developer executes a software program that utilizes a library 806 that includes one or more APIs 810 or otherwise communicates with a library 806 that includes one or more APIs 810 via a network or other remote communication medium. In at least one embodiment, one or more libraries 806 that include one or more APIs 810 will be executed by a remote computing service (such as a computing resource service provider). In another embodiment, one or more libraries 806 that include one or more APIs 810 will be executed by any other computing host that provides the one or more APIs 810 to one or more software programs 802.

[0116] In at least one embodiment, a processor (e.g., processor 502) that executes or uses one or more software programs 802 invokes, uses, executes, or otherwise implements one or more APIs 810 to allocate and otherwise manage the memory 814 to be used by the software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 to allocate and otherwise manage the memory 814 to be used by one or more portions of the software program 802 for acceleration using one or more PPUs (e.g., GPU or any other accelerator or processor further described herein). These software programs 802 request the neural network to perform signal processing using functions 812 provided by one or more APIs 810 in one embodiment.

[0117] In at least one embodiment, the API 810 is an API that facilitates parallel computing. In at least one embodiment, the API 810 is any other API further described herein. In at least one embodiment, the API 810 is provided by a driver and / or runtime 804. In at least one embodiment, the API 810 is provided by a CUDA user mode driver. In at least one embodiment, the API 810 is provided by the CUDA runtime. In at least one embodiment, the driver 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of the API 810 during the loading and execution of one or more portions of the software program 802. In at least one embodiment, the runtime 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of the API 810 during the execution of the software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by the driver and / or runtime 804 to perform combined arithmetic operations by the one or more software programs 802 during execution by one or more PPUs such as a GPU.

[0118] In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to perform combined arithmetic operations of one or more PPUs, such as a GPU. In at least one embodiment, as described above, one or more APIs 810 provide combined arithmetic operations via a driver and / or runtime 804. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve one or more blocks of memory 814 of one or more PPUs (e.g., GPU). In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve memory blocks. In at least one embodiment, one or more APIs 810 call a neural network to cause 816 the neural network, e.g., in conjunction with Figures 1 to 8 any of the neural networks described in the figures.

[0119] To improve the usability of software program 802 and / or to improve the optimization of one or more portions of the software program 802 for acceleration by one or more PPUs (e.g., GPU), in one embodiment, one or more APIs 810 provide one or more API functions 812 to cause 816 a neural network as described herein, e.g., in conjunction with Figures 1 to 8 described neural networks. In at least one embodiment, exemplary block diagram 800 depicts a processor (e.g., processor 106) that includes one or more circuits for causing one or more neural networks (e.g., a task neural network and / or a base neural network) to generate one or more images.

[0120] In the foregoing and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the possible ways of implementing the techniques. However, it will also be apparent that the techniques described below can be practiced in different configurations without specific details. Additionally, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0121] Logic

[0122] Figure 9A illustrates logic 915 according to at least one embodiment, such as described elsewhere herein, which can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 915 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Below in conjunction with Figure 9A and / orFigure 9B Provide details regarding logic 915. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, where the logic can be embodied jointly or separately as circuitry that forms part of a larger system (e.g., an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0123] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of the neural network used or trained in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any part of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0124] In at least one embodiment, any part of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0125] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 905 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 905 stores the weight parameters and / or input / output data for each layer of the neural network that is trained or used in conjunction with one or more embodiments during backpropagation of the input / output data and / or weight parameters. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information is loaded to configure the logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0126] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0127] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0128] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logic and / or mathematical operations at least in part based on and / or as directed by training and / or inference code (e.g., graph code), the result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 920, which are a function of input / output and / or weight parameter data stored in code and / or data store 901 and / or code and / or data store 905. In at least one embodiment, the activations stored in activation store 920 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 910 in response to executing instructions or other code, where the weight values stored in code and / or data store 905 and / or code and / or data store 901 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 905 or code and / or data store 901 or other on-chip or off-chip storage.

[0129] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processors or other hardware logic devices or circuits using them (e.g., coprocessors). In at least one embodiment, ALU 910 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 901, code and / or data store 905, and activation store 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 920 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of a processor or system memory. Additionally, inference and / or training code may be stored along with other code accessible to the processor or other hardware logic or circuits and may be extracted and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0130] In at least one embodiment, the activation store 920 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 920 can be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 920 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements for performing training and / or inference functions, the batch size of the data used in inferring and / or training a neural network, or some combination of these factors.

[0131] In at least one embodiment, Figure 9A the logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9A the logic 915 shown in can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., field programmable gate array (“FPGA”)).

[0132] Figure 9B FIG. shows the logic 915 according to at least one embodiment. In at least one embodiment, the logic 915 is inference and / or training logic. In at least one embodiment, the logic 915 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B the logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9BThe logic 915 shown in FIG. may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as a field programmable gate array (FPGA)). In at least one embodiment, the logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which may be used to store code (such as graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 9B In at least one embodiment shown in FIG., each of the code and / or data storage 901 and the code and / or data storage 905 is respectively associated with dedicated computing resources (such as computing hardware 902 and computing hardware 906). In at least one embodiment, each of the computing hardware 902 and the computing hardware 906 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in the code and / or data storage 901 and the code and / or data storage 905, and the results are stored in the activation storage 920.

[0133] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 respectively corresponds to a different layer of a neural network, such that the activation obtained from one storage / computation pair 901 / 902 of the code and / or data storage 901 and the computing hardware 902 is provided as the input to the next storage / computation pair 905 / 906 of the code and / or data storage 905 and the computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0134] Neural Network Training and Deployment

[0135] Figure 10Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 1002 is used to train an untrained neural network 1006. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0136] In at least one embodiment, supervised learning is used to train the untrained neural network 1006, where the training dataset 1002 includes inputs paired with desired outputs for the inputs, or where the training dataset 1002 includes inputs with known outputs and the outputs of the neural network 1006 are manually graded. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processes inputs from the training dataset 1002, and compares the resulting outputs to a set of desired or wanted outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (such as the trained neural network 1008) suitable for generating correct answers (such as results 1014) based on input data (such as a new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to perform any number of machine learning operations.

[0137] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "groundtruth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how each input relates to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 1008, which is capable of performing operations useful for reducing the dimensionality of a new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 1012 that deviate from the normal pattern of the new dataset 1012.

[0138] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge injected into the trained neural network 1008 during initial training.

[0139] In at least one embodiment, the training framework 1004 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed by Intel Corporation of Santa Clara, California, for example. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0140] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0141] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, action recognition, coloring, and / or variants thereof.

[0142] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of neural network models. In at least one embodiment, the Model Optimizer optimizes neural network models for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model that are used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variants thereof.

[0143] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0144] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0145] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are executed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0146] Data center

[0147] Figure 11 An example data center 1100 in which at least one embodiment can be used is shown. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0148] In at least one embodiment, as Figure 11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“node C.R.”) 1116(1)-1116(N), where “N” represents a positive integer (which may be a different integer “N” from the integers used in other figures). In at least one embodiment, the node C.R. 1116(1)-1116(N) may include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (such as dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1116(1)-1116(N) may be a server having one or more of the above computing resources.

[0149] In at least one embodiment, the grouped computing resources 1114 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) at various geographical locations. In at least one embodiment, a separate grouping of node C.R. within the grouped computing resources 1114 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0150] In at least one embodiment, the resource coordinator 1112 may configure or otherwise control one or more of the node C.R. 1116(1)-1116(N) and / or the grouped computing resources 1114. In at least one embodiment, the resource coordinator 1112 may include a software design infrastructure (“SDI”) management entity for the data center 1100. In at least one embodiment, the resource coordinator 1112 may include hardware, software, or some combination thereof.

[0151] In at least one embodiment, as Figure 11As shown, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework for supporting software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may respectively include web-based service software or applications, such as the service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 1128 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1122 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different layers, such as the software layer 1130 and the framework layer 1120 including Spark and the distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing the clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0152] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least respective parts of the nodes C.R. 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0153] In at least one embodiment, one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least respective portions of nodes C.R. 1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0154] In at least one embodiment, any one of the configuration manager 1124, the resource manager 1126, and the resource coordinator 1112 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1100 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0155] In at least one embodiment, the data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1100. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 1100 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0156] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0157] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9BProvide details regarding Logic 915. In at least one embodiment, Logic 915 may be used in Data Center 1100 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0158] In at least one embodiment, Figure 9A and / or Figure 9B one or more of the systems depicted in are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and procedures (such as those associated with Figure 1 those described). In at least one embodiment, Figure 9A and / or Figure 9B one or more of the systems depicted in are used to implement one or more systems and / or procedures such as those shown in conjunction with Figures 1 to 8 such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein based at least in part on one or more performance metrics of one or more neural networks.

[0159] Autonomous Vehicle

[0160] Figure 12A Shows an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1200 may be an airplane, robotic vehicle, or other type of vehicle.

[0161] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) in “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and future versions of the standard). In at least one embodiment, vehicle 1200 may be capable of functions according to one or more of Levels 1 through 5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 1200 may be capable of conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0162] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the driveline of vehicle 1200, which may include, but is not limited to, a transmission for enabling the propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from a throttle / accelerator 1252.

[0163] In at least one embodiment, when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive a signal from a steering actuator 1256. In at least one embodiment, for fully automated (Level 5) functions, the steering wheel may be optional. In at least one embodiment, a brake sensor system 1246 may be used to operate vehicle brakes in response to receiving a signal from a brake actuator 1248 and / or a brake sensor.

[0164] In at least one embodiment, one or more controllers 1236, which may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 12A(not shown in the figure) and / or a graphics processing unit (“GPU”), to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 may send signals to operate the vehicle brakes via a brake actuator 1248, to operate the steering system 1254 via one or more steering actuators 1256, and to operate the propulsion system 1250 via one or more throttle / accelerators 1252. In at least one embodiment, one or more controllers 1236 may include one or more on-vehicle (e.g., integrated) computing devices that process sensor signals and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, and two or more controllers may handle a single function and / or any combination thereof.

[0165] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data may be received from sensors such as, but not limited to: one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more Inertial Measurement Unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), remote cameras ( Figure 12A (not shown in the figure), mid-range cameras ( Figure 12A(not shown), one or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more braking sensors (e.g., as part of a braking sensor system 1246), and / or other sensor types.

[0166] In at least one embodiment, one or more controllers 1236 may receive inputs (e.g., represented by input data) from the instrument panel 1232 of vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, a sound signaler, a speaker, and / or via other components of vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 12A (not shown), location data (e.g., the location of vehicle 1200, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0167] In at least one embodiment, vehicle 1200 further includes a network interface 1224, which may communicate via one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 may be capable of communicating via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0168] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9BDetails regarding logic 915 are provided. In at least one embodiment, logic 915 may be used in vehicle 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0169] In at least one embodiment, Figure 11 one or more of the systems depicted in are used to perform operations described herein using one or more neural networks with various algorithms, formulas, and processes (such as those combined with Figure 1 those described). In at least one embodiment, Figure 11 one or more of the systems depicted in are used to implement one or more systems and / or processes such as those shown in combination with Figures 1 to 8 those shown, such as adjusting the resolution of information to be used by one or more neural networks based at least in part on one or more performance metrics of one or more neural networks and / or otherwise performing operations described herein.

[0170] Figure 12B An example of the camera positions and fields of view of an autonomous vehicle 1200 according to at least one embodiment is shown. In at least one embodiment, the cameras and respective fields of view are one example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on vehicle 1200. Figure 12A

[0171] ​In at least one embodiment, the camera type for a camera may include, but is not limited to, a digital camera that may be adapted to be used with components and / or systems of vehicle 1200. In at least one embodiment, one or more cameras may operate at an Automotive Safety Integrity Level (“ASIL”) B and / or other ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a Red Clear Clear Clear (“RCCC”) color filter array, a Red Clear Clear Blue (“RCCB”) color filter array, a Red Blue Green Clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0172] In at least one embodiment, one or more cameras may be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera may be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0173] In at least one embodiment, one or more cameras may be mounted in a mounting component, such as a custom-designed (three-dimensional (“3D”) printed) component, to remove stray light and reflected light from within vehicle 1200 (e.g., reflected light from the dashboard reflected in the windshield mirror) that may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting component, in at least one embodiment, the rearview mirror component may be 3D printed customized such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0174] In at least one embodiment, a camera (e.g., a forward camera) having a view of portions of the environment in front of the vehicle 1200 can be used for surround view to help identify the forward path and obstacles and, with the help of one or more controllers 1236 and / or the control SoC, assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0175] In at least one embodiment, a variety of cameras can be used in a forward configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although only one wide-angle camera 1270 is shown Figure 12B in the figures, in other embodiments, any number (including zero) of wide-angle cameras can be on the vehicle 1200. In at least one embodiment, any number of long-range cameras 1298 (e.g., a long-range stereo camera pair) can be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long-range cameras 1298 can also be used for object detection and classification and basic object tracking.

[0176] In at least one embodiment, any number of stereo cameras 1268 can also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1268 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 can include, but are not limited to, a compact stereo vision sensor that can include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1200 to a target object and use the information generated (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 can be used in addition to or in place of those described herein.

[0177] In at least one embodiment, a camera (e.g., a side-view camera) having a view of portions of the environment including the side of vehicle 1200 can be used for surround view, which provides information for creating and updating an occupancy grid, as well as generating a side-impact collision warning. For example, in at least one embodiment, surround cameras 1274 (e.g., four surround cameras as shown Figure 12B ) can be positioned on vehicle 1200. In at least one embodiment, one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1200. In at least one embodiment, vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround camera.

[0178] In at least one embodiment, a camera (e.g., a rear-view camera) having a view of portions of the environment including the rear of vehicle 1200 can be used for parking assistance, surround view, rear-collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0179] In at least one embodiment, Figure 12B one or more of the systems depicted in are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and processes (such as those associated with Figure 1 ). In at least one embodiment, Figure 12B one or more of the systems depicted in are used to implement one or more systems and / or processes such as those associated with Figures 1 to 8 shown in, such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein based at least in part on one or more performance metrics of one or more neural networks.

[0180] Figure 12C is a block diagram showing an example system architecture of autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, Figure 12A of. In at least one embodiment, Figure 12CEach of the components, features, and systems of vehicle 1200 is shown as being connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1200 for assisting in controlling various features and functions of vehicle 1200, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1202 may be read to find steering wheel angle, ground speed, revolutions per minute of the engine ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0181] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1202, which may include, but is not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoC") 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0182] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12A In at least one embodiment, controller 1236 may be used for a variety of functions. In at least one embodiment, controller 1236 may be coupled to any of the various other components and systems of vehicle 1200 and may be used to control vehicle 1200, the artificial intelligence of vehicle 1200, the infotainment of vehicle 1200, and / or other functions.

[0183] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., a system of vehicle 1200), and the HD map 1222 may obtain map refreshes and / or updates from one or more servers ( Figure 12C not shown in the figure).

[0184] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or a CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each of which has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which enables any combination of the clusters of one or more CPUs 1206 to be active at any given time.

[0185] In at least one embodiment, one or more CPUs 1206 may implement power management functions, which may include, but are not limited to, one or more of the following features: automatically clock-gating individual hardware blocks during idle to save dynamic power; clock-gating each core clock when the core is not actively executing instructions due to execution of wait-for-interrupt (“WFI”) / wait-for-event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement enhanced algorithms for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power states to enter for cores, clusters, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0186] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (alternatively referred to herein as “iGPU”). In at least one embodiment, one or more GPUs 1208 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use one or more compute application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0187] In at least one embodiment, one or more GPUs 1208 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include a plurality of mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or an orderer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads with a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable more fine-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0188] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, which in some examples is used to provide a peak memory bandwidth of approximately 900GB / second. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0189] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, Address Translation Service (“ATS”) support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two CPUs in one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thus simplifying the programming of one or more GPUs 1208 and porting applications to one or more GPUs 1208.

[0190] In at least one embodiment, one or more GPUs 1208 may include any number of access counters, which may track the frequency of access of one or more GPUs 1208 to the memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that most frequently accesses the pages, thus improving the efficiency of sharing memory ranges among processors.

[0191] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level three (“L3”) cache that may be available to both one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to one or more CPUs 1206 and one or more GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, depending on the embodiment, the L3 cache may include 4MB of memory or more, although smaller cache sizes may be used.

[0192] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks from one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or regional convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0193] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types, floating point operations, and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single instance convolution functions for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for security and / or safety-related events.

[0194] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0195] In at least one embodiment, one or more accelerators 1214 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0196] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0197] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0198] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines) and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0199] In at least one embodiment, each vector processor can include an instruction cache and can be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor can be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA can execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA can execute different computer vision algorithms simultaneously on one image, or even execute different algorithms on a sequence of images or parts of an image. In at least one embodiment, any number of PVAs can be included in a hardware acceleration cluster, and any number of vector processors can be included in each PVA. In at least one embodiment, the PVA can include additional error correction code (“ECC”) memory for enhancing overall system security.

[0200] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using the APB).

[0201] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standard, although other standards and protocols may be used.

[0202] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0203] In at least one embodiment, one or more accelerators 1214 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency are a good match for algorithm domains that require predictable processing. In other words, PVA excels in semi-dense or dense conventional computations, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1200, PVA can be designed to run classical computer vision algorithms because they can be efficient in object detection and integer math operations.

[0204] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0205] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0206] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example but not limited to, a neural network, the output of which is a measure of the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measure enables the system to make further decisions, namely, which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), and the output of one or more IMU sensors 1266 related to the vehicle 1200 direction, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0207] In at least one embodiment, one or more SoCs 1204 can include one or more data stores 1216 (e.g., memories). In at least one embodiment, one or more data stores 1216 can be on-chip memories of one or more SoCs 1204, which can store neural networks to be executed on one or more GPUs 1208 and / or the DLA. In at least one embodiment, one or more data stores 1216 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data stores 1216 can include one or more L2 or L3 caches.

[0208] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoC 1204 thermal and temperature sensors, and / or manage one or more SoC 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1204 in a lower power state and / or place the vehicle 1200 in the driver's safe parking mode (e.g., safely park the vehicle 1200).

[0209] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors, which may be used as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0210] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine, which may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0211] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (such as timers, interrupt controllers, etc.) and / or routing logic. In the secure mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high-dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0212] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1204, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make phone calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, otherwise they are disabled.

[0213] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0214] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic lens frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0215] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals that are not committed to a specific role.

[0216] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which can be connected via Ethernet channels), data from the bus 1202 (e.g., the speed of the vehicle 1200, the steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to free one or more CPUs 1206 from conventional data management tasks.

[0217] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3 - 5, thus providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible, reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy - efficient and space - efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast, efficient platform for level 3 - 5 autonomous vehicles.

[0218] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high - level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real - time, which are used in in - vehicle ADAS applications and actual level 3 - 5 autonomous vehicles.

[0219] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined together to achieve level 3 - 5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1220) can include text and word recognition, thus allowing traffic signs to be read and understood, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of the signs, and passing that semantic understanding to a path - planning module running on a CPU complex.

[0220] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network can be operated on multiple frames to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can be run simultaneously, e.g., within the DLA and / or on one or more GPUs 1208.

[0221] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or the owner of the vehicle 1200. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a secure mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0222] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from the microphone 1296 to detect and recognize emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use CNNs to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute an emergency vehicle safety routine, slow down the vehicle, drive the vehicle to the side of the road, stop, and / or idle the vehicle until the emergency vehicle passes.

[0223] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 may include, for example, X86 processors. One or more CPUs 1218 can be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or the on-chip infotainment system (“Infotainment SoC”) 1230. In at least one embodiment, SoC 1204 includes one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0224] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs (e.g., sensor data) from sensors of vehicle 1200.

[0225] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include but is not limited to one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and another vehicle and / or an indirect link may be established (e.g., via a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in the vicinity of vehicle 1200 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1200). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 1200.

[0226] In at least one embodiment, network interface 1224 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0227] In at least one embodiment, vehicle 1200 may further include one or more data stores 1228, which may include but are not limited to off-chip (e.g., one or more off-chip SoCs 1204) storage. In at least one embodiment, one or more data stores 1228 may include but are not limited to one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0228] In at least one embodiment, vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including for example but not limited to GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0229] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, the one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 1260 may use the CAN bus and / or bus 1202 (e.g., for transmitting data generated by the one or more RADAR sensors 1260) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0230] In at least one embodiment, the one or more RADAR sensors 1260 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for the adaptive cruise control function. In at least one embodiment, the long range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, the one or more RADAR sensors 1260 may assist in differentiating between static and moving objects and may be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more of the sensors 1260 included in the long range RADAR system may include, but are not limited to, a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1200 at a relatively high speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1200.

[0231] In at least one embodiment, by way of example, a mid-range RADAR system can include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system can include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two beams that continuously monitor the rear direction of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0232] In at least one embodiment, the vehicle 1200 can further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262 that can be positioned at the front, rear, and / or side positions of the vehicle 1200 can be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 can be used, and different ultrasonic sensors 1262 can be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 can operate at a functional safety level of ASIL B.

[0233] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. In at least one embodiment, one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1264 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0234] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, and have a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0235] In at least one embodiment, LIDAR technologies (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one deployed on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use class I (eye-safe) laser pulses of 5 nanoseconds per frame and may capture the reflected laser as 3D range point clouds and co-registered intensity data.

[0236] In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0237] In at least one embodiment, one or more IMU sensors 1266 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm, for providing an estimate of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1266 may enable vehicle 1200 to estimate its heading by directly observing and correlating the speed changes from GPS to one or more IMU sensors 1266 without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 may be combined in a single integrated unit.

[0238] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0239] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of vehicle 1200. In at least one embodiment, the type of cameras used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary according to the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera is described in more detail previously herein with reference to Figure 12A and Figure 12B Each camera is described in more detail previously herein with reference to

[0240] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure the vibration of components of vehicle 1200 (e.g., an axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine the friction or slip of the road surface (e.g., when there is a vibration difference between a powered drive axle and a free-rotating axle).

[0241] In at least one embodiment, vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples but not limited to, a SoC. In at least one embodiment, the ADAS system 1238 may include but not limited to any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0242] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1200 and automatically adjusts the speed of vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that vehicle 1200 change lanes when needed. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0243] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via the network interface 1224 and / or one or more wireless antennas 1226 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of and in the same lane as vehicle 1200), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles in front of a given vehicle 1200, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0244] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of sound, visual warnings, vibration, and / or rapid braking pulses.

[0245] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0246] In at least one embodiment, when vehicle 1200 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to warn the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1200 starts to leave its lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0247] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of a vehicle. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0248] In at least one embodiment, when the vehicle 1200 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, auditory, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0249] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1200 itself decides whether to follow the results of the main computer or the auxiliary computer (e.g., the first controller or the second controller in the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to the supervisory MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0250] In at least one embodiment, the main computer can be configured to provide a confidence score to the supervisory MCU, which indicates the main computer's confidence in the selected result. In at least one embodiment, if this confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the main computer, regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the main computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0251] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, at least in part, based on outputs from a primary computer and outputs from a secondary computer, conditions under which the secondary computer provides an error alert. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying metal objects that are not actually dangerous, such as drain grates or manhole covers that would trigger an alert. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there is a bicyclist or pedestrian present and when lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can be included as and / or be a component of one or more SoCs 1204.

[0252] In at least one embodiment, the ADAS system 1238 can include a secondary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the secondary computer can use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the overall system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the primary computer and the not-identical software code running on the secondary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the primary computer will not result in a major error.

[0253] In at least one embodiment, the output of the ADAS system 1238 can be fed into the perception block of the primary computer and / or the dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, as described herein, the secondary computer can have its own neural network that is trained to reduce the risk of false alarms.

[0254] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1200. For example, infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1200, such as information from ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0255] In at least one embodiment, infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 via bus 1202. In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1236 (e.g., the main computer and / or backup computer of vehicle 1200). In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 into a driver-to-safe parking mode as described herein.

[0256] In at least one embodiment, vehicle 1200 may further include a dashboard 1232 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, dashboard 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, dashboard 1232 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, airbag information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the dashboard 1232. In at least one embodiment, dashboard 1232 may be included as part of the infotainment SoC 1230, and vice versa.

[0257] In at least one embodiment, Figure 12C one or more of the systems depicted therein are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and processes, such as those incorporated Figure 1 with those described. In at least one embodiment, Figure 12C one or more of the systems depicted therein are used to implement one or more systems and / or processes such as those shown in conjunction with Figures 1 to 8 those shown, such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of one or more neural networks.

[0258] Figure 12D is according to at least one embodiment between one or more cloud-based servers and Figure 12A1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but are not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0259] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1278 may send updated neural networks 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but are not limited to, updates to the HD map 1222, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0260] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data may be labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or may undergo other preprocessing. In at least one embodiment, no amount of training data may be labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle).

[0261] In at least one embodiment, one or more servers 1278 may receive data from a vehicle and apply the data to a most recent real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer powered by one or more GPUs 1284 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure of a data center powered by a CPU.

[0262] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of performing fast, real-time inference and may use that capability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as an image sequence and / or objects located in that image sequence by vehicle 1200 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them to the objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1200 is malfunctioning, one or more servers 1278 may send a signal to vehicle 1200 that instructs the fail-safe computer in vehicle 1200 to take control, notify the passengers, and complete a safe parking operation.

[0263] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, for example, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. This document combines Figure 9A and / or Figure 9B to provide details about the hardware structure 915.

[0264] Computer system

[0265] Figure 13 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system can be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that can include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 1300 may include, but is not limited to, components such as a processor 1302 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 1300 may include a processor such as those available from Intel Corporation of Santa Clara, California, processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, the computer system 1300 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0266] Embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0267] In at least one embodiment, computer system 1300 can include, but is not limited to, a processor 1302, which can include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1300 is a single-processor desktop or server system, but in another embodiment, computer system 1300 can be a multi-processor system. In at least one embodiment, processor 1302 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 can be coupled to a processor bus 1310, which can transfer data signals between processor 1302 and other components in computer system 1300.

[0268] In at least one embodiment, processor 1302 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1302. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1306 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0269] In at least one embodiment, execution unit 1308, which includes, but is not limited to, logic for performing integer and floating point operations, is also located in processor 1302. In at least one embodiment, processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general-purpose processor and the associated circuitry to execute instructions, operations used by many multimedia applications can be performed using packed data in processor 1302. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0270] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0271] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage and for the storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can direct data signals among the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals among the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 can be coupled to the memory 1320 via the high-bandwidth memory path 1318, and the graphics / video card 1312 can be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0272] In at least one embodiment, the computer system 1300 can use the system I / O interface 1322 as a proprietary hub interface bus to couple the MCH 1316 to an I / O controller hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 can provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1320, the chipset, and the processor 1302. Examples can include, but are not limited to, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 that includes a user input and keyboard interface 1325, a serial expansion port 1327 (such as a Universal Serial Bus (“USB”) port), and a network controller 1334. In at least one embodiment, the data storage 1324 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0273] In at least one embodiment, Figure 13 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 13 an exemplary SoC can be shown. In at least one embodiment, Figure 13The devices shown in the figure can be interconnected using proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using Compute Express Link (CXL) interconnections.

[0274] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0275] In at least one embodiment, Figure 13 one or more of the systems depicted in the figure are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and procedures (such as those associated with Figure 1 In at least one embodiment, Figure 13 one or more of the systems depicted in the figure are used to implement one or more systems and / or processes such as those shown in connection with Figures 1 to 8 to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein, at least in part based on one or more performance metrics of one or more neural networks.

[0276] Figure 14 is a block diagram showing an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0277] In at least one embodiment, the electronic device 1400 can include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as I 2The C bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 14 A system is shown that includes interconnected hardware devices or “chips”, and in other embodiments, Figure 14 An exemplary SoC may be shown. In at least one embodiment, Figure 14 The devices shown in may be interconnected using proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components of are interconnected using Compute Express Link (CXL) interconnections.

[0278] In at least one embodiment, Figure 14 May include a display 1424, a touch screen 1425, a touchpad 1430, a Near Field Communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Embedded Controller (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, BIOS / Firmware / Flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a Solid State Drive (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented, for example, to the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0279] In at least one embodiment, other components may be communicatively coupled to the processor 1410 via the components described herein. In at least one embodiment, an accelerometer 1441, an ambient light sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 may be communicatively coupled to the EC 1435. In at least one embodiment, a speaker 1463, a headset 1464, and a microphone (“mic”) 1465 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1462, which may in turn be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1457 may be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450, the Bluetooth unit 1452, and the WWAN unit 1456 may be implemented in a next-generation form factor (“NGFF”).

[0280] Logic 915 is for performing inference and / or training operations associated with one or more embodiments. Details regarding the logic 915 are provided herein in conjunction with Figure 9A and / or Figure 9B In at least one embodiment, the logic 915 may be used in the electronic device 1400 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0281] In at least one embodiment, Figure 14 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and procedures such as those described in conjunction with Figure 14 In at least one embodiment, Figures 1 to 8 one or more of the systems depicted in

[0282] Figure 15FIG. 1500 shows a computer system according to at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0283] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502, which is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, a main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1504, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using the computer system 1500.

[0284] In at least one embodiment, the computer system 1500 includes, but is not limited to, an input device 1508, a parallel processing system 1512, and a display device 1506 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0285] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 may be used in the computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0286] In at least one embodiment, Figure 15 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and processes (such as those described in connection with Figure 15One or more of the systems depicted are used to implement one or more systems and / or processes such as those shown in conjunction with Figures 1 to 8 one or more systems and / or processes such as those shown in Figures 1 to 8 , such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part based on one or more performance metrics of one or more neural networks.

[0287] Figure 16 FIG. 1600 shows a computer system according to at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, computer 1610 and USB drive 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0288] In at least one embodiment, USB drive 1620 includes, but is not limited to, processing unit 1630, USB interface 1640, and USB interface logic 1650. In at least one embodiment, processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1630 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1630 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1630 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1630 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0289] In at least one embodiment, USB interface 1640 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 may include any number and type of logic that enables processing unit 1630 to interface with a device (such as computer 1610) via USB connector 1640.

[0290] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9BProvide details regarding Logic 915. In at least one embodiment, Logic 915 may be used in computer system 1500 for performing inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0291] In at least one embodiment, Figure 16 one or more of the systems depicted in are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and processes (such as those combined with Figure 1 those described). In at least one embodiment, Figure 16 one or more of the systems depicted in are used to implement one or more systems and / or processes such as those shown in combination with Figures 1 to 8 those shown, such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein at least in part based on one or more performance metrics of one or more neural networks.

[0292] Figure 17A An exemplary architecture is shown where multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support a communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, whose values may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1710(1)-1710(N) include one or more graphics cores (also simply referred to as "cores") 2000 as disclosed in Figure 20A and Figure 20B those. In at least one embodiment, one or more graphics cores 2000 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where in this context, a slice may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors or schedulers).

[0293] In addition, in at least one embodiment, two or more GPUs 1710 are interconnected by high-speed links 1729(1)-1729(2), which can be implemented using a protocol / link similar to or different from the protocol / link used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 can be connected by a high-speed link 1728, which can be a symmetric multi-processor (SMP) bus operating at speeds of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used to accomplish Figure 17A all communications between the various system components shown in

[0294] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memories 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memories 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N), respectively. In at least one embodiment, memory interconnects 1726 and 1750 can utilize similar or different memory access techniques. By way of example and not limitation, processor memories 1701(1)-1701(M) and GPU memory 1720 can be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1701 can be volatile memory while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0295] As described herein, although the respective multi-core processors 1705 and GPUs 1710 can be physically coupled to specific memories 1701, 1720, and / or a unified memory architecture can be implemented, in which the virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, processor memories 1701(1)-1701(M) can each include 64 GB of system memory address space, and GPU memories 1720(1)-1720(N) can each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0296] Figure 17B Additional details of the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 are shown in accordance with an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip having the processor 1707.

[0297] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A - 1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A - 1761D and one or more caches 1762A - 1762D. In at least one embodiment, the cores 1760A - 1760D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1762A - 1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included within the caches 1762A - 1762D and shared by groups of cores 1760A - 1760D. For example, one embodiment of the processor 1707 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include Figure 17A processor memories 1701(1) - 1701(M).

[0298] In at least one embodiment, coherence is maintained for data and instructions stored in the respective caches 1762A - 1762D, 1756, and the system memory 1714 via an inter-core communication through a coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the coherence bus 1764 to snoop on cache accesses.

[0299] In at least one embodiment, the proxy circuit 1725 communicatively couples the graphics acceleration module 1746 to the coherence bus 1764, allowing the graphics acceleration module 1746 to participate in the cache coherence protocol as a peer of the cores 1760A - 1760D. In particular, in at least one embodiment, the interface 1735 provides a connection to the proxy circuit 1725 via the high-speed link 1740, and the interface 1737 connects the graphics acceleration module 1746 to the high-speed link 1740.

[0300] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 1731(1) - 1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1) - 1731(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1731(1) - 1731(N) of the graphics acceleration module 1746 includes one or more graphics cores 2000 as discussed in connection with Figure 20A and Figure 20B . In at least one embodiment, the graphics processing engines 1731(1) - 1731(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having a plurality of graphics processing engines 1731(1) - 1731(N), or the graphics processing engines 1731(1) - 1731(N) may be individual GPUs integrated on a common package, line card, or chip.

[0301] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, a fetch unit 1744 may be used to keep the data stored in the cache 1738 and the graphics memories 1733(1)-1733(M) coherent with the core caches 1762A-1762D, 1756, and system memory 1714. As previously described, this may be representative of the cache 1738 and the memories 1733(1)-1733(M) being implemented via the proxy circuitry 1725 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1762A-1762D, 1756 to the cache 1738 and receiving updates from the cache 1738).

[0302] In at least one embodiment, a set of registers 1745 stores context data for the threads executed by the graphics processing engines 1731(1)-1731(N), and a context management circuit 1748 manages thread contexts. For example, the context management circuit 1748 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1748, during a context switch, may store the current register values into a specified area in memory (e.g., identified by a context pointer). Then, the register values can be restored when returning to the context. In at least one embodiment, an interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0303] In at least one embodiment, the MMU 1739 converts virtual / valid addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1731(1)-1731(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0304] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge for the system of the graphics accelerator modules 1746 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities to the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1731(1)-1731(N).

[0305] In at least one embodiment, since the hardware resources of the graphics processing engines 1731(1)-1731(N) are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1736 is the physical separation of the graphics processing engines 1731(1)-1731(N) such that they appear as independent units to the system.

[0306] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each of the graphics processing engines 1731(1)-1731(N), and N = M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store the instructions and data being processed by each of the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0307] In at least one embodiment, to reduce data traffic on the high-speed link 1740, a biasing technique can be used to ensure that the data stored in the graphics memories 1733(1)-1733(M) is the data most frequently used by the graphics processing engines 1731(1)-1731(N), and preferably is data not used (at least not frequently used) by the cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data required by the cores (and preferably not required by the graphics processing engines 1731(1)-1731(N)) in the caches 1762A-1762D, 1756, and the system memory 1714.

[0308] Figure 17C Another exemplary embodiment is shown in which the accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via the interfaces 1737 and 1735 (again, which can be any form of bus or interface protocol) over the high-speed link 1740. In at least one embodiment, the accelerator integrated circuit 1736 can perform operations similar to those described with respect to Figure 17B but may have higher throughput due to its close proximity to the coherence bus 1764 and the caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models can include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0309] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to the graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0310] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, a shared model can use a hypervisor to virtualize the graphics processing engines 1731(1)-1731(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0311] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1731(1)-1731(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0312] Figure 17D An exemplary accelerator integration slice 1790 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, an application is an effective address space 1782 in the system memory 1714 that stores process elements 1783. In at least one embodiment, in response to a GPU call 1781 from an application 1780 executing on the processor 1707, the process elements 1783 are stored. In at least one embodiment, the process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0313] In at least one embodiment, the graphics acceleration module 1746 and / or each of the graphics processing engines 1731(1)-1731(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure may be included for setting the process state and sending the WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0314] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0315] In at least one embodiment, in operation, the WD fetch unit 1791 in the accelerator integration slice 1790 fetches the next WD 1784, which includes an indication of work to be completed by one or more of the graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, the data from the WD 1784 may be stored in the register 1745 and used by the MMU 1739, the interrupt management circuit 1747, and / or the context management circuit 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing the segment / page table 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuit 1747 may process the interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing a graphics operation, the effective address 1793 generated by the graphics processing engines 1731(1)-1731(N) is translated to a real address by the MMU 1739.

[0316] In at least one embodiment, the register 1745 is replicated for each of the graphics processing engines 1731(1)-1731(N) and / or the graphics acceleration module 1746, and the register 1745 may be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integration slice 1790. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

[0317] Table 1 - Registers Initialized by the Hypervisor

[0318]

[0319] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0320] Table 2 - Registers for Operating System Initialization

[0321]

[0322] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1731(1)-1731(N) to do its job, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0323] Figure 17E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798 in which a list of process elements 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 can be accessed via the hypervisor 1796, which virtualizes the graphics acceleration module engine for the operating system 1795.

[0324] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions, namely time slice sharing and graphics directed sharing.

[0325] In at least one embodiment, in this model, the system hypervisor 1796 owns the graphics acceleration module 1746 and makes its functions available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the system hypervisor 1796, the graphics acceleration module 1746 may have to comply with certain requirements, such as (1) job requests from applications must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that job requests from applications are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) when operating in a directed sharing programming model, it must be ensured that the graphics acceleration module 1746 is fair among processes.

[0326] In at least one embodiment, an application 1780 needs to use a graphics acceleration module type, a work descriptor (WD), a privilege mask register (AMR) value, and a context save / restore area pointer (CSRP) to make an operating system 1795 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1746.

[0327] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the user privilege mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1796 can selectively apply the current privilege mask override register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the valid address of a region in the application's valid address space 1782 for the graphics acceleration module 1746 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save the state between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0328] Upon receiving the system call, the operating system 1795 can verify that the application 1780 is registered and has been granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 uses the information shown in Table 3 to call the hypervisor 1796.

[0329] Table 3 - Operating System to Hypervisor Call Parameters

[0330]

[0331] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1796 verifies that the operating system 1795 is registered and has been granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the hypervisor 1796 places the process element 1783 into a process element linked list corresponding to the type of the graphics acceleration module 1746. In at least one embodiment, the process element may include the information shown in Table 4.

[0332] Table 4 - Process Element Information

[0333]

[0334]

[0335] In at least one embodiment, the hypervisor initializes the registers 1745 of multiple accelerator integrated slices 1790.

[0336] As Figure 17F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1701(1)-1701(N) and the GPU memories 1720(1)-1720(N). In this implementation, operations executed on the GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access the processor memories 1701(1)-1701(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1701(1), a second portion is allocated to the second processor memory 1701(N), a third portion is allocated to the GPU memory 1720(1), and so on. In at least one embodiment, thus the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memories 1701 and the GPU memories 1720, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0337] In at least one embodiment, the bias / coherency management circuits 1794A-1794E within one or more MMUs 1739A-1739E ensure cache coherency between one or more host processors (e.g., 1705) and the caches of the GPUs 1710, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 17FMultiple instances of the bias / coherence management circuits 1794A - 1794E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0338] One embodiment allows the GPU memory 1720 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full - system cache coherence. In at least one embodiment, the ability of the GPU memory 1720 to be accessed as system memory without heavy cache - coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1705 to set operands and access computed results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1720 without cache - coherence overhead can be critical for the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache - coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1710. In at least one embodiment, the efficiency of operand setting, result access, and GPU computation may play a role in determining the effectiveness of GPU offloading.

[0339] In at least one embodiment, the selection of GPU bias and host - processor bias is driven by a bias - tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page - granularity structure (e.g., controlled at the granularity of memory pages), and this page - granularity structure includes 1 or 2 bits per GPU - attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1710 (e.g., for caching frequently / most - recently - used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1720. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0340] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1720 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1710 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1705 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1710. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0341] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrating from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0342] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1705. In at least one embodiment, to access these pages, the processor 1705 can request access from the GPU 1710, and the GPU 1710 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that the GPU bias pages are pages required by the GPU rather than the host processor 1705, and vice versa.

[0343] One or more hardware structures 915 are used to execute one or more embodiments. Details regarding one or more hardware structures 915 may be provided herein in conjunction with Figure 9A and / or Figure 9B provide details regarding one or more hardware structures 915.

[0344] Figure 18An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0345] Figure 18 is a block diagram of an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an 2 S / I 2 C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0346] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 may be in the integrated circuit 1800 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0347] In at least one embodiment, Figure 18 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and procedures (such as those described in connection with Figure 18 one or more of the systems depicted inFigures 1 to 8 One or more systems and / or processes such as those shown in, e.g., adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein, at least in part, based on one or more performance metrics of one or more neural networks.

[0348] Figures 19A - 19B An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to those illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processor(s) / core(s), peripheral interface controllers, or general processor cores.

[0349] Figures 19A - 19B is a block diagram showing an exemplary graphics processor used within a SoC in accordance with embodiments described herein. Figure 19A An exemplary graphics processor 1910 of a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. Figure 19B An additional exemplary graphics processor 1940 of a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 19A the graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B the graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 may be Figure 18 a variant of the graphics processor 1810.

[0350] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A - 1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N - 1, and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1915A - 1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A - 1915N use the primitives and vertex data generated by the vertex processor 1905 to produce a frame buffer for display on a display device. In at least one embodiment, the one or more fragment processors 1915A - 1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0351] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A - 1920B, one or more caches 1925A - 1925B, and one or more circuit interconnects 1930A - 1930B. In at least one embodiment, the one or more MMUs 1920A - 1920B provide virtual - to - physical address mapping for the graphics processor 1910 (including for the vertex processor 1905 and / or the fragment processors 1915A - 1915N), and can also reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 1925A - 1925B. In at least one embodiment, the one or more MMUs 1920A - 1920B can be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 18 one or more application processors 1805, image processors 1815, and / or video processors 1820 such that each processor 1805 - 1820 can participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnects 1930A - 1930B enable the graphics processor 1910 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0352] In at least one embodiment, the graphics processor 1940 includes asFigure 19B One or more shader cores 1955A - 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N - 1 and 1955N) as shown, which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter - core task manager 1945 which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A - 1955N and a tiling unit 1958 to accelerate tiling operations for tile - based rendering where the rendering operation of a scene is subdivided in image space, e.g., to take advantage of local spatial coherence within the scene or optimize the use of internal caches.

[0353] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, the logic 915 can be used in the graphics processor 1910 and / or 1940 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0354] In at least one embodiment, Figure 19A and Figure 19B One or more of the systems depicted in are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and procedures (such as those described in connection with Figure 1 ). In at least one embodiment, Figure 19A and Figure 19B One or more of the systems depicted in are used to implement one or more systems and / or processes such as those shown in connection with Figures 1 to 8 such as to adjust the resolution of information to be used by one or more neural networks and / or otherwise perform the operations described herein at least in part based on one or more performance metrics of one or more neural networks.

[0355] Figures 20A - 20B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, shown and described in connection with Figures 20A - 20B in Figures 20A - 20BThe described components are integrated into a single system, such as a graphics processing unit (GPU), a system-on-a-chip (SoC), or another type of processor. In at least one embodiment, Figure 20A illustrates a graphics core 2000 that may be included within Figure 18 the graphics processor 1810, and in at least one embodiment, it may be a unified shader core 1955A - 1955N as Figure 19B illustrated. Figure 20B illustrates a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 2030 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1800 includes the graphics core 2000, e.g., for forming the integrated circuit and / or forming an SoC, where such integrated circuit and / or such SoC performs the operations described herein.

[0356] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and a cache / shared memory 2020 (e.g., including L1, L2, L3, last-level cache, or other caches) that are shared among the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A - 2001N or partitions per core, and the graphics processor may include multiple instances of the graphics core 2000. In at least one embodiment, each of the slices 2001A - 2001N refers to the graphics core 2000. In at least one embodiment, the slices 2001A - 2001N have sub-slices that are part of the slices 2001A - 2001N. In at least one embodiment, the slices 2001A - 2001N are independent of or dependent on other slices. In at least one embodiment, the slices 2001A - 2001N may include support logic that includes local instruction caches 2004A - 2004N, thread schedulers (orderers) 2006A - 2006N, thread dispatchers 2008A - 2008N, and a set of registers 2010A - 2010N. In at least one embodiment, the slices 2001A - 2001N may include a set of additional functional units (AFUs 2012A - 2012N), floating-point units (FPUs 2014A - 2014N), integer arithmetic logic units (ALUs 2016A - 2016N), address calculation units (ACUs 2013A - 2013N), double-precision floating-point units (DPFPUs 2015A - 2015N), and matrix processing units (MPUs 2017A - 2017N). In at least one embodiment, the MPUs 2017A - 2017N are referred to as matrix engines.

[0357] In at least one embodiment, each of slices 2001A - 2001N includes one or more engines for floating - point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large - dataset workloads. In at least one embodiment, one or more of slices 2001A - 2001N includes one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also referred to as "FP16"), 32 - bit floating - point (also referred to as "FP32"), or 64 - bit floating - point (also referred to as "FP64"). In at least one embodiment, one or more of slices 2001A - 2001N includes 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units of a processor or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of a processor. In at least one embodiment, the graphics core 2000 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0358] In at least one embodiment, one or more of slices 2001A - 2001N includes one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice in slices 2001A - 2001N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0359] In at least one embodiment, one or more of slices 2001A - 2001N includes a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video - quality operations on video data.

[0360] In at least one embodiment, one or more slices 2001A - 2001N are linked to an L2 cache and a memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HDMI3) stack, and a media engine. In at least one embodiment, one or more slices 2001A - 2001N include a plurality of cores (e.g., 16 cores) and a plurality of ray - tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A - 2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A - 2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back - ends. In at least one embodiment, slices 2001A - 2001N include a memory structure, such as an L2 cache.

[0361] In at least one embodiment, FPUs 2014A - 2014N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 2015A - 2015N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALUs 2016A - 2016N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPUs 2017A - 2017N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPUs 2017A - 2017N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFUs 2012A - 2012N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0362] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 9A and / or Figure 9B to provide details regarding Logic 915. In at least one embodiment, Logic 915 may be used in the graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0363] In at least one embodiment, the graphics core 2000 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge, which enables multiple graphics processors 2000 (e.g., 8) to be interconnected with each other without bonding through the load / store unit (LSU), data transfer unit, and synchronization semantics across multiple graphics processors 2000. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0364] In at least one embodiment, the graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where an individual die may be connected to the interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 2000 includes a compute tile, a memory tile (e.g., where the memory tile may be exclusively accessed by different tiles or different chip sets such as Rambo tiles), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are encapsulated together in the graphics core 2000 as part of the GPU. In at least one embodiment, the graphics core 2000 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, the compute tile may have 8 graphics cores 2000, an L1 cache; and the foundation tile may have a host interface to PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected by face-to-face (F2F) chip-on-chip bonding with fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 2000 includes a memory structure (which includes memory) and is a tile that can be accessed by multiple tiles. In at least one embodiment, the graphics core 2000 stores its own hardware context into the memory, accesses its own hardware context in the memory, or loads its own hardware context into the memory, where the hardware context is a set of data loaded from registers before process restoration, and where the hardware context may indicate the state of the hardware (e.g., the state of the GPU).

[0365] In at least one embodiment, the graphics core 2000 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or converts a parallel data stream into a serial data stream.

[0366] In at least one embodiment, the graphics core 2000 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, block data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0367] In at least one embodiment, the graphics core 2000 executes an API, where the API abstracts the hardware of the graphics core 2000 and accesses libraries with instructions to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0368] In at least one embodiment, Figure 20A one or more of the systems depicted are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and procedures such as those associated with Figure 1 those described. In at least one embodiment, Figure 20A one or more of the systems depicted are used to implement one or more systems and / or processes such as those associated with Figures 1 to 8 those shown, such as adjusting the resolution of information to be used by one or more neural networks and / or otherwise performing the operations described herein at least in part based on one or more performance metrics of one or more neural networks.

[0369] Figure 20BIllustrated is a GPGPU 2030 in at least one embodiment, which may be configured such that highly parallel computing operations can be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for enabling connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to allocate execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, the compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can be used as a higher-level cache for the cache memories within the compute clusters 2036A-2036H. In at least one embodiment, the compute clusters 2036A-2036H include slices or are referred to as "slices". In at least one embodiment, the GPGPU 2030 is part of a SoC, such as part of an integrated circuit 1800 ( Figure 18 ).

[0370] In at least one embodiment, the GPGPU 2030 includes memories 2044A-2044B, which are coupled to the compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, the memories 2044A-2044B can include various types of memory devices, which include dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0371] In at least one embodiment, each of the compute clusters 2036A-2036H includes a set of graphics cores, such as Figure 20AThe graphics core 2000, which can include various types of integer and floating-point logic units that can perform computational operations over a range of precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 2036A - 2036H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0372] In at least one embodiment, multiple instances of the GPGPU 2030 can be configured to operate as compute clusters. In at least one embodiment, the communication for synchronization and data exchange in the compute clusters 2036A - 2036H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 2030 communicate via the host interface 2032. In at least one embodiment, the GPGPU 2030 includes an I / O hub 2039 that couples the GPGPU 2030 to a GPU link 2040 that enables a direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 2030 are located in separate data processing systems and communicate via network devices accessible via the host interface 2032. In at least one embodiment, in addition to or instead of the host interface 2032, the GPU link 2040 can also be configured to enable a connection to a host processor.

[0373] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 2030 for inference, the GPGPU 2030 can include fewer compute clusters 2036A - 2036H compared to when using the GPGPU 2030 to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A - 2044B can vary between the inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions that can be used during the inference operations of a deployed neural network.

[0374] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9B details regarding Logic 915 are provided. In at least one embodiment, Logic 915 may be used in GPGPU 2030 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0375] In at least one embodiment, Figure 20B one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and processes (such as those described in connection with Figure 20B In at least one embodiment, one or more of the systems depicted in Figures 1 to 8 are used to implement one or more systems and / or processes such as those shown in connection with

[0376] Figure 21 is a block diagram showing a computing system 2100 according to at least one embodiment. In at least one embodiment, the computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 and system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that may enable the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 may enable a display controller, which may be included in one or more processors 2102, to provide output to one or more display devices 2110A. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0377] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to a memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can use any number of standards based on communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 2112 form a parallel or vector processing system in a computing center, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2112 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 can also include a display controller and a display interface (not shown) for implementing a direct connection to one or more display devices 2110B. In at least one embodiment, the one or more parallel processors 2112 include one or more cores, such as the graphics core 2000 discussed herein.

[0378] In at least one embodiment, the system storage unit 2114 can be connected to the I / O hub 2107 to provide a storage mechanism for the computing system 2100. In at least one embodiment, the I / O switch 2116 can be used to provide an interface mechanism for implementing connections between the I / O hub 2107 and other components, which can be, for example, a network adapter 2118 and / or a wireless network adapter 2119 integrated into the platform, as well as various other devices that can be added via one or more additional devices 2120. In at least one embodiment, the network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0379] In at least one embodiment, the computing system 2100 can include other components not explicitly shown that can also be connected to the I / O hub 2107, and the other components include USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol)) can be used to implement the communication paths of the various components Figure 21 in the middle.

[0380] In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry, and constituting a graphics processing unit (GPU). For example, one or more parallel processors 2112 include a graphics core 2000. In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, one or more processors 2102, and I / O hub 2107 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0381] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure In at least one embodiment, logic 915 may be used in computing system 2100 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0382] In at least one embodiment, ​ one or more of the systems depicted in ​ are used to perform the operations described herein using one or more neural networks and / or otherwise with various algorithms, formulas, and procedures (such as those described in connection with ​ In at least one embodiment, Figures 1 to 8 one or more of the systems depicted in

[0383] Processor

[0384] Figure 22AShows a parallel processor 2200 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2200 is a variant of the one or more parallel processors 2112 according to an exemplary embodiment. Figure 21 In at least one embodiment, the parallel processor 2200 includes one or more graphics cores 2000.

[0385] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 may be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices via the use of a hub or switch interface (e.g., a memory hub 2205). In at least one embodiment, the connection between the memory hub 2205 and the I / O unit 2204 forms a communication link 2213. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar 2216, where the host interface 2206 receives commands for performing processing operations and the memory crossbar 2216 receives commands for performing memory operations.

[0386] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 may direct the work operations for executing those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to a scheduler 2210 (which may be referred to as an sequencer), and scheduler 2210 is configured to allocate commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is properly configured and in an active state before tasks are allocated to clusters in processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 may be configured to perform complex scheduling and work allocation operations at both a coarse-grained and a fine-grained level, enabling fast preemption and context switching of threads executing on processing cluster array 2212. In at least one embodiment, host software may attest to the workload for scheduling on processing cluster array 2212 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on processing cluster array 2212 by scheduler 2210 logic within a microcontroller including scheduler 2210.

[0387] In at least one embodiment, processing cluster array 2212 may include up to “N” processing clusters (e.g., cluster 2214A, cluster 2214B through cluster 2214N), where “N” represents a positive integer (which may be a different integer “N” than the integer used in other figures). In at least one embodiment, each cluster 2214A - 2214N of processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to clusters 2214A - 2214N in processing cluster array 2212, and these algorithms may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2210, or may be assisted in part by compiler logic during compilation of program logic configured to be executed by processing cluster array 2212. In at least one embodiment, different clusters 2214A - 2214N in processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0388] In at least one embodiment, the processing cluster array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2212 may include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0389] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from the system memory via the I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to the system memory.

[0390] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 2214A - 2214N in the processing cluster array 2212. In at least one embodiment, various parts of the processing cluster array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, the first part may be configured to perform vertex shading and topology generation, the second part may be configured to perform tessellation and geometry shading, and the third part may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A - 2214N may be stored in a buffer to allow the transfer of intermediate data between the clusters 2214A - 2214N for further processing.

[0391] In at least one embodiment, the processing cluster array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from a front end 2208. In at least one embodiment, the processing tasks may include indices of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to obtain an index corresponding to the task, or may receive the index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing cluster array 2212 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., batch-buffer, push buffer, etc.).

[0392] In at least one embodiment, each of one or more instances of the parallel processing units 2202 may be coupled to a parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar 2216, which may receive memory requests from the processing cluster array 2212 as well as the I / O unit 2204. In at least one embodiment, the memory crossbar 2216 may access the parallel processor memory 2222 via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partitioning units (e.g., partitioning unit 2220A, partitioning unit 2220B to partitioning unit 2220N), each of which may be coupled to a portion (e.g., memory unit) of the parallel processor memory 2222. In at least one embodiment, the number of partitioning units 2220A - 2220N is configured to be equal to the number of memory units, such that the first partitioning unit 2220A has a corresponding first memory unit 2224A, the second partitioning unit 2220B has a corresponding second memory unit 2224B, and the Nth partitioning unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partitioning units 2220A - 2220N may not be equal to the number of memory units.

[0393] In at least one embodiment, the memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HBM3. In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across the memory units 2224A-2224N, allowing the partitioning units 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, a local instance of the parallel processor memory 2222 may be excluded in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0394] In at least one embodiment, any one of the clusters 2214A-2214N in the cluster array 2212 of processing clusters may process data to be written into any of the memory units 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 may be configured to transmit the output of each cluster 2214A-2214N to any of the partitioning units 2220A-2220N or to another cluster 2214A-2214N, and the other cluster 2214A-2214N may perform additional processing operations on the output. In at least one embodiment, each cluster 2214A-2214N may communicate with the memory interface 2218 via the memory crossbar 2216 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2216 has a connection to the memory interface 2218 for communicating with the I / O unit 2204, as well as a connection to a local instance of the parallel processor memory 2222, which enables processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to the parallel processing units 2202. In at least one embodiment, the memory crossbar 2216 may use virtual channels to separate the traffic flow between the clusters 2214A-2214N and the partitioning units 2220A-2220N.

[0395] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include floating-point units with higher precision relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0396] Figure 22B is a block diagram of a partitioning unit 2220 according to at least one embodiment. In at least one embodiment, the partitioning unit 2220 is Figure 22A an instance of one of the partitioning units 2220A - 2220N. In at least one embodiment, the partitioning unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a ROP 2226 (raster operation unit). In at least one embodiment, the L2 cache 2221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2225 for processing. In at least...

Claims

1. A processor, comprising: One or more circuits for adjusting a resolution of information to be used by the one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks.

2. The processor according to claim 1, wherein the resolution of the information is used to train one or more neural networks to generate one or more images.

3. The processor according to claim 1, wherein the one or more performance metrics include one or more loss operations.

4. The processor according to claim 1, wherein the one or more neural networks include one or more encoders.

5. The processor according to claim 1, wherein the one or more neural networks include one or more transformer neural networks for performing bilinear interpolation when adjusting the resolution.

6. The processor according to claim 1, wherein the resolution of the information is represented using a pixel matrix of one or more images.

7. The processor according to claim 1, wherein the resolution of the information is adjusted to increase.

8. A system, comprising: One or more processors for adjusting a resolution of information to be used by the one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks.

9. The system according to claim 8, wherein the resolution of the information is used to train one or more neural networks to generate one or more images.

10. The system according to claim 8, wherein the one or more performance metrics include one or more loss operations.

11. The system according to claim 8, wherein the one or more neural networks include one or more encoders.

12. The system according to claim 8, wherein the one or more neural networks include one or more transformer neural networks for performing bilinear interpolation when adjusting the resolution.

13. The system according to claim 8, wherein the resolution of the information is represented using a pixel matrix of one or more images.

14. The system according to claim 8, wherein the resolution of the information is adjusted to increase.

15. A method, comprising: Adjusting a resolution of information to be used by the one or more neural networks based at least in part on one or more performance metrics of the one or more neural networks.

16. The method according to claim 15, wherein the resolution of the information is used to train one or more neural networks to generate one or more images.

17. The method according to claim 15, wherein the one or more performance metrics include one or more loss operations.

18. The method according to claim 15, wherein the one or more neural networks include one or more encoders.

19. The method according to claim 15, wherein the one or more neural networks comprise one or more transformer neural networks, and the one or more transformer neural networks are configured to perform bilinear interpolation when adjusting the resolution.

20. The method according to claim 15, wherein the resolution of the information is adjusted to increase.

Images