Method for passive time service based on satellite navigation receiver

Abstract

The present invention relates to the application field of satellite navigation receiver timing. Specifically, a method for implementing passive timing for satellite navigation receivers is disclosed. The method comprises the following steps: S1: After receiving satellite positioning, a Beidou-3 baseband chip calculates the satellite navigation receiver clock error information, adjusts the receiver crystal oscillator frequency through hardware, and after several consecutive adjustments, synchronizes the clock with the Beidou navigation system. The receiver then outputs a second pulse and sends the time information to an FPGA via a serial port. S2: After receiving the accurate second pulse output by the Beidou-3 baseband chip, the internal timekeeping clock count of the FPGA is corrected. The time information received via the serial port is simultaneously placed in a time counter, and accurate time maintenance is performed based on the internal timekeeping clock count of the FPGA. This method for implementing passive timing for satellite navigation receivers, through software handshaking and hardware pulse interrupt mechanisms, solves the core issues of traditional active timing technologies, such as the inability to trigger on demand by users and low resource utilization.

Description

Technical Field

[0001] The present invention relates to the application field of satellite navigation receiver timing, and in particular to a method for realizing passive timing based on a satellite navigation receiver. Background Art

[0002] like Figure 2 As shown in the figure, current satellite navigation timing technology mainly relies on the receiver to actively output second pulses (1PPS) and UTC time information, continuously tracking satellite signals to complete positioning, speed measurement and timing (PVT solution), and using hardware to control the crystal oscillator frequency to achieve synchronization with the satellite system clock. For example, Beidou-2 and GPS receivers calculate clock error information and periodically output time signals to calibrate external device clocks. This type of technology has been widely used in key fields such as communications and power, relying on the global coverage and high precision characteristics of satellite systems.

[0003] However, the core mode of the existing technology is active timing, that is, the receiver outputs a time signal at a fixed period. The user needs to rely on external equipment to continuously receive and maintain time synchronization, and it cannot be triggered on demand. The user cannot actively obtain real-time time information at any time and can only passively receive periodic signals, resulting in response delays in scenarios with sudden timing needs (such as power fault recording and military command synchronization); transmission redundancy and resource waste, continuous output of time signals occupying communication bandwidth and power consumption, and causing energy waste in application scenarios that do not require high-frequency synchronization (such as field monitoring equipment).

[0004] Therefore, it is necessary to propose an implementation method based on passive timing of satellite navigation receivers to solve the above problems. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the defects of the existing technology. The present invention proposes an implementation method based on passive timing of a satellite navigation receiver, which solves the problems of the existing technology in the background technology.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] The method for implementing passive timing based on a satellite navigation receiver includes the following steps:

[0008] S1: After receiving satellite positioning, the BeiDou-3 baseband chip calculates the satellite navigation receiver clock error information and adjusts the receiver crystal oscillator frequency through hardware. After several consecutive adjustments, it achieves synchronization with the BeiDou navigation system clock, outputs second pulses, and sends the time information to the FPGA through the serial port.

[0009] S2: After receiving the accurate second pulse output by the Beidou third-generation baseband chip, the internal time-keeping clock count of the FPGA is corrected, and the time information received by the serial port is placed in the time counter, and the accurate time is maintained according to the internal time-keeping clock count of the FPGA;

[0010] S3: When the user has a time service requirement, an inquiry instruction is sent through the communication interface connected with the Beidou third-generation satellite navigation receiver;

[0011] S4: After receiving the instruction sent by the user, the Beidou third-generation satellite navigation receiver feeds back an answer;

[0012] S5: After accurately receiving the feedback instruction of the Beidou third-generation satellite navigation receiver, the user generates a synchronization pulse to the satellite navigation receiver, and records the time when the pulse is generated;

[0013] S6: The Beidou third-generation satellite navigation receiver responds to the first correct synchronization pulse after the answer feedback, latches the time information corresponding to the rising edge of the synchronization pulse and the clock count, and feeds back the time information to the user.

[0014] Preferably, the implementation steps of the Beidou third-generation baseband chip for receiving and positioning are as follows: the baseband chip receives Beidou third-generation B1I, B2I and B3I signals, suppresses noise through a low-noise amplifier and a band-pass filter, converts the radio frequency signals into baseband signals through digital down conversion, and completes signal acquisition based on an FFT parallel code phase search algorithm, and then adopts a phase-locked loop and a delay-locked loop to jointly track the carrier and the pseudo-code phase.

[0015] Preferably, the clock difference of the satellite navigation receiver is solved by a least square method, and the formula of the clock difference of the receiver is:

[0016] Where t sat,i is the signal transmission time of the i th satellite, t rcv,i is the local recording time of the signal of the i th satellite reaching the receiver, ∈ iono and ∈ tropo are ionospheric and tropospheric delay correction values corrected by Klobuchar model and Saastamoinen model respectively, and ∈noise is Gaussian noise.

[0017] Preferably, the regulation of the crystal frequency is dynamically adjusted by a PI control algorithm, and the formula of the crystal frequency is:

[0018] Where e(t)=t 北斗 -t 本地 , represents the real-time clock difference error, K p =0.1, represents the proportional gain coefficient, and K i= 0.01, represents the integral gain coefficient, t0 is the control algorithm start time;

[0019] When the clock difference fluctuation is less than 1 ns for 5 times in succession, it is determined that the synchronization is completed, and the 1PPS and UTC time are output to the FPGA.

[0020] Preferably, when the FPGA receives the 1PPS and UTC time of the baseband chip, a 32-bit counter is initialized, and the count value is N = 1 x 10 6 .

[0021] Preferably, in step S2, the current time is calculated in real time by a time interpolation algorithm, and the current accurate time calculation formula is:

[0022] Wherein f = 10 MHz, represents the clock frequency of the counter, represents the crystal oscillator drift compensation amount, N count is the counter count value after the last second pulse, T base is the UTC reference time provided by the baseband chip;

[0023] The second pulse of the baseband chip is forced to synchronize every 60 seconds to eliminate the cumulative error of the crystal oscillator, and if synchronization fails for 3 times in succession, the backup constant temperature crystal oscillator is switched to and an alarm is triggered.

[0024] Preferably, in step S3, the user sends a time service request instruction through an RS-422 interface, and the instruction format includes the following fields:

[0025] Start symbol: fixed as "GET_TIME";

[0026] Sequence number: 4-byte cycle count;

[0027] Timestamp: user local time;

[0028] Check code: 1-byte XOR check code.

[0029] Preferably, in step S4, after the Beidou third-generation satellite navigation receiver receives the instruction sent by the user, the steps for responding and feeding back are as follows: the FPGA analyzes the instruction and checks, returns an error code if the checking fails, and returns a ready response if the checking succeeds and the receiver is in an idle state, or stores the instruction in a FIFO queue if it is busy.

[0030] Preferably, in S5, the user end generates a standard synchronization pulse, which is transmitted to the receiver through a shielded twisted pair, and the pulse transmission delay is calculated by a pre-calibration formula, which is:

[0031] Wherein L is the line length, ∈ r is the dielectric constant, and c is the speed of light;

[0032] The user end uses the GPS to tame the rubidium clock to record the pulse generation time.

[0033] Preferably, in step S6, the FPGA detects the rising edge of the pulse, and then latches the counter value N capture , and calculates the precise time: Where τ sys = 200 ns represents the inherent delay of the system, and Δ temp = k (T-T0) represents the temperature compensation amount, where T represents the current actual ambient temperature, T0 represents the reference temperature or calibration temperature, T-T0 represents the deviation of the current temperature from the reference temperature, k is the temperature coefficient, and N capture represents the counter value latched by the FPGA.

[0034] The feedback data includes the UTC whole-second time and the nanosecond-level offset, and if the deviation is greater than 500 ns after verification by the user end, the time service is retriggered.

[0035] Compared with the prior art, the present application has the following beneficial effects:

[0036] The implementation method of the passive time service of the satellite navigation receiver solves the core problems of the traditional active time service technology, i.e., the user cannot trigger as needed and the resource utilization rate is low, through the software handshake and hardware pulse interrupt mechanism, and through the dynamic crystal oscillator frequency adjustment and temperature compensation technology, the time service accuracy is improved, which is significantly superior to the prior art, while retaining the global coverage and high reliability advantages of satellite time service, the core breakthroughs of user autonomous triggering and resource on-demand allocation are realized, and the advantages of high accuracy, low redundancy and strong adaptability are combined. BRIEF DESCRIPTION OF DRAWINGS

[0037] The disclosure of the present application will be described with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present application. In the drawings, the same reference numerals are used to refer to the same components. Among them:

[0038] Figure 1 The method step flowchart of the present application is schematically shown;

[0039] Figure 2 The active time service working block diagram of the prior art satellite navigation receiver is schematically shown;

[0040] Figure 3 The passive time service working block diagram of the third-generation Beidou satellite navigation receiver of the present application is schematically shown;

[0041] Figure 4 The passive time service detail flowchart of the third-generation Beidou satellite navigation receiver of the present application is schematically shown. DETAILED DESCRIPTION

[0042] It is easy to understand that according to the technical solutions of the present application, a person skilled in the art can propose a plurality of structure modes and implementation modes which can be replaced with each other without changing the essential spirit of the present application. Therefore, the following specific embodiments and drawings are only exemplary descriptions of the technical solutions of the present application, and should not be regarded as the whole or as the limitation or restriction of the technical solutions of the present application.

[0043] As shown in Figure 1 , Figure 3 , Figure 4 , the implementation method based on passive time service of the satellite navigation receiver comprises the following steps:

[0044] Step 1: Beidou third-generation baseband chip receives satellite positioning, specifically, the baseband chip receives Beidou third-generation B1I, B2I and B3I signals, suppresses noise through a low-noise amplifier and a band-pass filter, converts the radio frequency signal into a baseband signal through digital down conversion, extracts a rate of 10MS / s, and completes signal acquisition based on an FFT parallel code phase search algorithm, the acquisition time is less than 2 seconds, then a phase-locked loop and a delay-locked loop are used to jointly track the carrier and the pseudo-code phase, and then the satellite navigation receiver clock difference information is calculated, specifically, the satellite navigation receiver clock difference is solved by a least square method, and the receiver clock difference formula is:

[0045] Where t sat,i is the signal transmission time of the i-th satellite, t rcv,i is the local recording time of the signal of the i-th satellite reaching the receiver, ∈ iono and ∈ tropo are ionospheric and tropospheric delay correction values corrected by Klobuchar model and Saastamoinen model respectively, and ∈noise is Gaussian noise.

[0046] Then the receiver crystal oscillator frequency is regulated through hardware, after continuous adjustment for several times, the second pulse is output after synchronization with the Beidou navigation system clock, and the time information is sent to the FPGA through the serial port, specifically, the crystal oscillator frequency is dynamically adjusted through a PI control algorithm, and the crystal oscillator frequency formula is:

[0047] Where e(t)=t 北斗 -t 本地 , represents the real-time clock difference error, K p =0.1, represents the proportional gain coefficient, K i =0.01, represents the integral gain coefficient, and t0 is the control algorithm start time. When the clock difference fluctuation is less than 1ns for 5 consecutive times, it is determined that the synchronization is completed, and the 1PPS and UTC time are output to the FPGA.

[0048] Multi-system compatibility is also supported to improve the redundancy and reliability of time service. Specifically, the baseband chip hardware supports input of Beidou B1I, B2I, B3I and GPS L5 frequency signals, parallel processing of Beidou and GPS signals in the signal capture stage, and selection of signals with high signal-to-noise ratio. The time weighted fusion formula is:

[0049] wherein T final is the fused time, T 北斗 is the time calculated by the third-generation Beidou, T GPS is the time calculated by the GPS L5 signal, w 北斗 is the weight of the Beidou system, and the calculation formula is: wherein SNR 北斗 is the signal-to-noise ratio of the Beidou signal, SNR max is the maximum signal-to-noise ratio supported by the system, w GPS is the weight of the GPS system, and the calculation method is the same as w 北斗 .

[0050] Step 2: After receiving the accurate second pulse output by the third-generation Beidou baseband chip, correct the internal timekeeping clock count of the FPGA, and place the time information received by the serial port in the time counter. Accurate time maintenance is performed according to the internal timekeeping clock count of the FPGA. Specifically, when the FPGA receives the 1PPS and UTC time of the baseband chip, initialize the 32-bit counter, the clock source is a 10MHz temperature compensated crystal oscillator with a drift compensation amount of ±0.1ppm, and the count value is N=1×10 6 every 100ms. The current time is calculated in real time by a time interpolation algorithm, and the current accurate time calculation formula is:

[0051] wherein f=10MHz represents the clock frequency of the counter, represents the crystal oscillator drift compensation amount, N count is the counter count value since the last second pulse, and T base is the UTC reference time provided by the baseband chip. The second pulse of the baseband chip is forced to synchronize every 60 seconds to eliminate the cumulative error of the crystal oscillator. If synchronization fails for three consecutive times, switch to the backup oven-controlled crystal oscillator and trigger an alarm. If there is no user time service request for 5 minutes, the FPGA sends a control signal to turn off the baseband chip RF front end and only maintain the timekeeping counter running. The system power consumption can be reduced. During the receiver sleep period, the system can be awakened by a GPIO interrupt. The wake-up process is: the FPGA detects the interrupt signal, restores the power supply of the RF module, and restarts the signal capture and tracking of the baseband chip.

[0052] Step 3: When the user has a time service requirement, send a time inquiry instruction through a communication interface connected with the Beidou third-generation satellite navigation receiver. Specifically, the user sends a time service request instruction through an RS-422 interface, and the instruction format includes the following fields:

[0053] Start symbol: fixed as "GET_TIME";

[0054] Sequence number: 4-byte cycle count, in hexadecimal;

[0055] Timestamp: user local time, Unix format, reserved field;

[0056] Check code: 1-byte XOR check code, calculated byte by byte from the start symbol to the end symbol;

[0057] The communication protocol uses a sliding window mechanism with a window size of 3, supports instruction retransmission and out-of-order processing, a baud rate of 115200 bps, instruction frames with CRC-32 check, and channel noise suppression through an adaptive filter;

[0058] Step 4: After receiving the instruction sent by the user, the Beidou third-generation satellite navigation receiver sends a response feedback. The specific implementation is as follows: the FPGA parses the instruction and performs a check. If the check fails, an error status code is returned. If the check is successful, if the receiver is in an idle state, a ready response is immediately returned. If it is busy, the instruction is stored in a FIFO queue;

[0059] Step 5: After accurately receiving the feedback instruction from the Beidou third-generation satellite navigation receiver, the user generates a synchronization pulse for the satellite navigation receiver and records the time at which the pulse is generated. Specifically, the user end generates a standard synchronization pulse, which is transmitted to the receiver through a shielded twisted pair. The pulse transmission delay is calculated through a pre-calibration formula:

[0060] where L is the line length, ∈ r is the dielectric constant, and c is the speed of light;

[0061] The user end uses a GPS tamed rubidium clock to record the pulse generation time, and an EMI filter is deployed in the pulse path to suppress interference of 30 dBm and above.

[0062] Step 6: The Beidou third-generation satellite navigation receiver responds to the first correct synchronization pulse after the response feedback, latches the time information corresponding to the rising edge of the synchronization pulse and the clock count, and simultaneously feeds back the time information to the user. After the FPGA detects the rising edge of the pulse, the counter value N capture is latched, and the accurate time is calculated as follows: where τ sys = 200 ns represents the inherent delay of the system, and Δ temp= k (T-T0), indicates the temperature compensation amount, wherein T represents the current actual ambient temperature, the value is usually measured in real time by a temperature sensor installed inside the receiver or near the key chip, T0 represents a reference temperature or a calibration temperature, which is a pre-selected standard temperature point, usually the room temperature or the rated operating temperature of the device, T-T0 represents the deviation value of the current temperature relative to the reference temperature, and K is a temperature coefficient, which describes how many nanoseconds the system transmission delay will change when the temperature changes by 1 degree Celsius, N capture The counter value of the FPGA latch is represented, the feedback data contain UTC whole-second time and nanosecond-level offset, if the deviation is greater than 500 ns after the user checks, the time service is retriggered, and the data identification time source can be fed back, the source is Beidou III or GPS, and multi-system compatibility is supported.

[0063] After receiving the time information fed back by the Beidou III satellite navigation receiver, the user can obtain the accurate time of the received time through processing, so as to achieve the time service purpose.

[0064] In use, the user sends a time service request instruction through a communication interface, triggers the receiver to enter a time service preparation state, the baseband chip captures the Beidou satellite signal in real time, solves the clock difference and dynamically adjusts the frequency of the crystal oscillator, generates a high-precision second pulse and UTC time, transmits the high-precision second pulse and UTC time to the FPGA, the FPGA maintains the local time by using the temperature-compensated crystal oscillator, and realizes microsecond-level time keeping through an interpolation algorithm, after the user generates a synchronization pulse, the receiver latches the current time information, combines the pre-calibrated transmission delay and temperature compensation, and feeds back the accurate time stamp, the whole process realizes the closed-loop time service of "on-demand triggering-accurate latching-dynamic compensation" through the cooperation of software and hardware, breaks through the limitation of the traditional fixed cycle, and meets the sudden and high-precision time service demand.

[0065] The technical scope of the present application is not limited to the content in the above description, and those skilled in the art can make various modifications and changes to the above embodiments without departing from the technical idea of the present application, and these modifications and changes should all belong to the protection scope of the present application.

Claims

1. A method for implementing passive timing based on a satellite navigation receiver, characterized in that: The following steps are involved: S1: After receiving satellite positioning, the BeiDou-3 baseband chip calculates the satellite navigation receiver clock error information and adjusts the receiver crystal oscillator frequency through hardware. After several consecutive adjustments, it achieves synchronization with the BeiDou navigation system clock, outputs second pulses, and sends the time information to the FPGA through the serial port. S2: After receiving the accurate second pulse output by the BeiDou-3 baseband chip, it corrects the FPGA's internal timekeeping clock count and places the time information received by the serial port into the time counter. It then maintains accurate time based on the FPGA's internal timekeeping clock count. S3: When the user has timing requirements, the timing query command is sent through the communication interface connected to the BeiDou-3 satellite navigation receiver; S4: After receiving the command sent by the user, the BeiDou-3 satellite navigation receiver responds and provides feedback; S5: After the user accurately receives the feedback command from the BeiDou-3 satellite navigation receiver, a standard synchronization pulse is generated and transmitted to the receiver via a shielded twisted pair cable. The time when the pulse is generated is recorded. The pulse transmission delay is calculated using the pre-calibrated formula: Where L is the line length, ∈ r is the dielectric constant, c is the speed of light; The user end uses a GPS disciplined rubidium clock to record the pulse generation time; S6: The BeiDou-3 satellite navigation receiver responds to the first correct synchronization pulse after the response feedback, latches the time information and clock count corresponding to the rising edge of the synchronization pulse, and feeds back the time information to the user.

2. The method for implementing passive timing based on a satellite navigation receiver according to claim 1, characterized in that: The implementation steps of the Beidou-3 baseband chip for satellite positioning are as follows: the baseband chip receives the Beidou-3 B1I, B2I, and B3I signals, suppresses noise through a low-noise amplifier and a bandpass filter, converts the RF signal into a baseband signal through digital down-conversion, and completes signal capture based on the FFT parallel code phase search algorithm. Subsequently, a phase-locked loop and delay-locked loop are used to jointly track the carrier and pseudo-code phase.

3. The method for implementing passive timing based on a satellite navigation receiver according to claim 1, characterized in that: The satellite navigation receiver clock error is calculated by the least squares method, and the receiver clock error formula is: where t sat,i is the signal transmission time of the i-th satellite, t rcv,i is the local recording time when the signal from satellite i arrives at the receiver, ∈ iono and ∈ tropo are the ionospheric and tropospheric delay correction values ​​corrected by the Klobuchar model and Saastamoinen model, respectively, and ∈noise is Gaussian noise.

4. The method for implementing passive timing based on a satellite navigation receiver according to claim 1, wherein: The crystal oscillator frequency is dynamically adjusted by the PI control algorithm, and the crystal oscillator frequency formula is: where e(t) = t 北斗 -t 本地 , represents the real-time clock error, K p =0.1, indicating the proportional gain coefficient, K i =0.01, represents the integral gain coefficient, t0 is the start time of the control algorithm; When the clock difference fluctuates less than 1ns for five consecutive times, synchronization is determined to be complete and 1PPS and UTC time are output to the FPGA.

5. The method for implementing passive timing based on a satellite navigation receiver according to claim 4, characterized in that: After the FPGA receives the 1PPS and UTC time from the baseband chip, it initializes a 32-bit counter with a count value of N=1×10 every 100ms. 6 .

6. The method for implementing passive timing based on a satellite navigation receiver according to claim 5, characterized in that: In step S2, the current time is calculated in real time using a time interpolation algorithm. The current precise time calculation formula is: Where f = 10MHz, represents the counter clock frequency, δ drift =αt+βt 2 , represents the crystal oscillator drift compensation amount, N count is the counter count value since the last second pulse, T base UTC reference time provided for baseband chips; The baseband chip's pulse-per-second synchronization is forced every 60 seconds to eliminate the accumulated error of the crystal oscillator. If synchronization fails three times in a row, the backup oven-controlled crystal oscillator is switched to and an alarm is triggered.

7. The method for implementing passive timing based on a satellite navigation receiver according to claim 2, characterized in that: In step S3, the user sends a timing request command via the RS-422 interface. The command format includes the following fields: Start character: fixed to "GET_TIME"; Sequence number: 4-byte cycle count; Timestamp: user local time; Check code: 1-byte XOR check code.

8. The method for implementing passive timing based on a satellite navigation receiver according to claim 7, characterized in that: In step S4, after the BeiDou-3 satellite navigation receiver receives the instruction sent by the user, the steps for response feedback are as follows: FPGA parses the instruction and verifies it. If the verification fails, it returns an error status code. After the verification succeeds, if the receiver is in idle state, it immediately returns a ready response. If it is busy, it stores the instruction in the FIFO queue.

9. The method for implementing passive timing based on a satellite navigation receiver according to claim 6, characterized in that: In step S6, after the FPGA detects the rising edge of the pulse, it latches the counter value N capture , calculate the exact time: where τ sys =200ns, indicating the inherent delay of the system, Δ temp =k(T-T0), which represents the temperature compensation amount, where T represents the current actual ambient temperature, T0 represents the reference temperature or calibration temperature, T-T0 represents the deviation of the current temperature relative to the reference temperature, K is the temperature coefficient, and N capture Indicates the counter value latched by FPGA; The feedback data includes the UTC full second time and nanosecond offset. After verification by the user end, if the deviation is greater than 500ns, the timing will be retriggered.

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